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Add DMA to I2C reading/writing

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This commit is contained in:
Edward Emelianov
2023-01-08 18:37:08 +03:00
parent dd8d567464
commit c76d7aacb0
10 changed files with 251 additions and 101 deletions
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240
G0:G070/i2c/i2c.c
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@@ -17,19 +17,35 @@
*/
#include <stm32g0.h>
#include "strfunc.h" // mymemcpy
#include "usart.h"
#include "i2c.h"
/*
* GPIO Resources: I2C1_SCL - PB6 (AF6), I2C1_SDA - PB7 (AF6)
*/
I2C_SPEED curI2Cspeed = LOW_SPEED;
extern volatile uint32_t Tms;
static uint32_t cntr;
static uint8_t i2c_got_DMA_Rx = 0;
volatile uint8_t I2C_scan_mode = 0; // == 1 when I2C is in scan mode
static uint8_t i2caddr = I2C_ADDREND; // current address in scan mode
static volatile int I2Cbusy = 0, goterr = 0; // busy==1 when DMA active, goterr==1 if 't was error @ last sent
static uint8_t I2Cbuf[256], i2cbuflen = 0; // buffer for DMA tx/rx and its len
// macros for I2C rx/tx
#define DMARXCCR (DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE)
#define DMATXCCR (DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE | DMA_CCR_TEIE)
// macro for I2CCR1
#define I2CCR1 (I2C_CR1_PE | I2C_CR1_RXDMAEN | I2C_CR1_TXDMAEN)
// return 1 if I2Cbusy is set & timeout reached
static inline int isI2Cbusy(){
cntr = Tms;
do{
if(Tms - cntr > I2C_TIMEOUT){ USND("Timeout, DMA transfer in progress?\n"); return 1;}
}while(I2Cbusy);
return 0;
}
// GPIO Resources: I2C1_SCL - PB6 (AF6), I2C1_SDA - PB7 (AF6)
void i2c_setup(I2C_SPEED speed){
if(speed >= CURRENT_SPEED){
speed = curI2Cspeed;
@@ -38,6 +54,7 @@ void i2c_setup(I2C_SPEED speed){
}
RCC->IOPENR |= RCC_IOPENR_GPIOBEN;
I2C1->CR1 = 0;
I2C1->ICR = 0x3f38; // clear all errors
GPIOB->AFR[0] = (GPIOB->AFR[0] & ~(GPIO_AFRL_AFSEL6 | GPIO_AFRL_AFSEL7)) |
6 << (6 * 4) | 6 << (7 * 4);
GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODE6 | GPIO_MODER_MODE7)) |
@@ -53,74 +70,29 @@ void i2c_setup(I2C_SPEED speed){
}else{ // VERYLOW_SPEED - the lowest speed by STM register: ~7.7kHz
I2C1->TIMINGR = (0xF<<28) | (4<<20) | (2<<16) | (0xff<<8) | (0xff);
}
I2C1->CR1 = I2C_CR1_PE;
I2C1->CR1 = I2CCR1;
RCC->AHBENR |= RCC_AHBENR_DMA1EN;
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
I2Cbusy = 0;
}
/**
* write command byte to I2C
* @param addr - device address (TSYS01_ADDR0 or TSYS01_ADDR1)
* @param data - bytes to write
* @param nbytes - amount of bytes to write
* @param stop - to set STOP
* @return 0 if error
*/
static uint8_t write_i2cs(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t stop){
cntr = Tms;
I2C1->CR1 = 0; // clear busy flag
I2C1->ICR = 0x3f38; // clear all errors
I2C1->CR1 = I2C_CR1_PE;
while(I2C1->ISR & I2C_ISR_BUSY){
IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){
USND("Line busy\n");
return 0; // check busy
}}
cntr = Tms;
while(I2C1->CR2 & I2C_CR2_START){
IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){
return 0; // check start
}}
//I2C1->ICR = 0x3f38; // clear all errors
I2C1->CR2 = nbytes << 16 | addr;
if(stop) I2C1->CR2 |= I2C_CR2_AUTOEND; // autoend
// now start transfer
I2C1->CR2 |= I2C_CR2_START;
for(int i = 0; i < nbytes; ++i){
cntr = Tms;
while(!(I2C1->ISR & I2C_ISR_TXIS)){ // ready to transmit
IWDG->KR = IWDG_REFRESH;
if(I2C1->ISR & I2C_ISR_NACKF){
I2C1->ICR |= I2C_ICR_NACKCF;
//USND("NAK\n");
return 0;
}
if(Tms - cntr > I2C_TIMEOUT){
USND("Timeout\n");
return 0;
}
}
I2C1->TXDR = data[i]; // send data
// setup DMA for rx (tx==0) or tx (tx==1)
// DMAMUX: 10 - Rx, 11 - Tx
static void i2cDMAsetup(int tx, uint8_t len){
if(tx){
DMA1_Channel1->CCR = DMATXCCR;
DMA1_Channel1->CPAR = (uint32_t) &I2C1->TXDR;
DMAMUX1_Channel0->CCR = 11;
}else{
DMA1_Channel1->CCR = DMARXCCR;
DMA1_Channel1->CPAR = (uint32_t) &I2C1->RXDR;
DMAMUX1_Channel0->CCR = 10;
}
// wait for data gone
while(I2C1->ISR & I2C_ISR_BUSY){
IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){break;}
}
return 1;
DMA1_Channel1->CMAR = (uint32_t) I2Cbuf;
DMA1_Channel1->CNDTR = i2cbuflen = len;
}
uint8_t write_i2c(uint8_t addr, uint8_t *data, uint8_t nbytes){
return write_i2cs(addr, data, nbytes, 1);
}
/**
* read nbytes of data from I2C line
* all functions with `addr` should have addr = address << 1
* `data` should be an array with at least `nbytes` length
* @return 1 if all OK, 0 if NACK or no device found
*/
static uint8_t read_i2cb(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t busychk){
static uint8_t i2c_start(uint8_t busychk){
if(busychk){
cntr = Tms;
while(I2C1->ISR & I2C_ISR_BUSY){
@@ -137,9 +109,88 @@ static uint8_t read_i2cb(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t bu
USND("No start\n");
return 0; // check start
}}
return 1;
}
// start writing
static uint8_t i2c_startw(uint8_t addr, uint8_t nbytes, uint8_t stop){
if(!i2c_start(1)) return 0;
I2C1->CR2 = nbytes << 16 | addr;
if(stop) I2C1->CR2 |= I2C_CR2_AUTOEND; // autoend
// now start transfer
I2C1->CR2 |= I2C_CR2_START;
return 1;
}
/**
* write command byte to I2C
* @param addr - device address (TSYS01_ADDR0 or TSYS01_ADDR1)
* @param data - bytes to write
* @param nbytes - amount of bytes to write
* @param stop - to set STOP
* @return 0 if error
*/
static uint8_t write_i2cs(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t stop){
if(!i2c_startw(addr, nbytes, stop)) return 0;
for(int i = 0; i < nbytes; ++i){
cntr = Tms;
while(!(I2C1->ISR & I2C_ISR_TXIS)){ // ready to transmit
IWDG->KR = IWDG_REFRESH;
if(I2C1->ISR & I2C_ISR_NACKF){
I2C1->ICR |= I2C_ICR_NACKCF;
//USND("NAK\n");
return 0;
}
if(Tms - cntr > I2C_TIMEOUT){
USND("Timeout\n");
return 0;
}
}
I2C1->TXDR = data[i]; // send data
}
cntr = Tms;
// wait for data gone
while(I2C1->ISR & I2C_ISR_BUSY){
IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){break;}
}
return 1;
}
uint8_t write_i2c(uint8_t addr, uint8_t *data, uint8_t nbytes){
if(isI2Cbusy()) return 0;
return write_i2cs(addr, data, nbytes, 1);
}
uint8_t write_i2c_dma(uint8_t addr, uint8_t *data, uint8_t nbytes){
if(!data || nbytes < 1) return 0;
mymemcpy((char*)I2Cbuf, (char*)data, nbytes);
if(isI2Cbusy()) return 0;
i2cDMAsetup(1, nbytes);
goterr = 0;
if(!i2c_startw(addr, nbytes, 1)) return 0;
I2Cbusy = 1;
DMA1_Channel1->CCR = DMATXCCR | DMA_CCR_EN; // start transfer
return 1;
}
// start reading
static uint8_t i2c_startr(uint8_t addr, uint8_t nbytes, uint8_t busychk){
if(!i2c_start(busychk)) return 0;
// read N bytes
I2C1->CR2 = (nbytes<<16) | addr | 1 | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN;
I2C1->CR2 |= I2C_CR2_START;
return 1;
}
/**
* read nbytes of data from I2C line
* all functions with `addr` should have addr = address << 1
* `data` should be an array with at least `nbytes` length
* @return 1 if all OK, 0 if NACK or no device found
*/
static uint8_t read_i2cb(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t busychk){
if(!i2c_startr(addr, nbytes, busychk)) return 0;
uint8_t i;
for(i = 0; i < nbytes; ++i){
cntr = Tms;
@@ -161,23 +212,38 @@ static uint8_t read_i2cb(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t bu
}
uint8_t read_i2c(uint8_t addr, uint8_t *data, uint8_t nbytes){
if(isI2Cbusy()) return 0;
return read_i2cb(addr, data, nbytes, 1);
}
uint8_t read_i2c_dma(uint8_t addr, uint8_t nbytes){
if(nbytes < 1) return 0;
if(isI2Cbusy()) return 0;
i2cDMAsetup(0, nbytes);
goterr = 0;
if(!i2c_startr(addr, nbytes, 1)) return 0;
I2Cbusy = 1;
DMA1_Channel1->CCR = DMARXCCR | DMA_CCR_EN; // start transfer
return 1;
}
// read register reg
uint8_t read_i2c_reg(uint8_t addr, uint8_t reg, uint8_t *data, uint8_t nbytes){
if(isI2Cbusy()) return 0;
if(!write_i2cs(addr, &reg, 1, 0)) return 0;
return read_i2cb(addr, data, nbytes, 0);
}
// read 16bit register reg
uint8_t read_i2c_reg16(uint8_t addr, uint16_t reg16, uint8_t *data, uint8_t nbytes){
if(isI2Cbusy()) return 0;
if(!write_i2cs(addr, (uint8_t*)&reg16, 2, 0)) return 0;
return read_i2cb(addr, data, nbytes, 0);
}
void i2c_init_scan_mode(){
i2caddr = 0;
i2caddr = 1; // start from 1 as 0 is a broadcast address
I2C_scan_mode = 1;
}
@@ -185,12 +251,50 @@ void i2c_init_scan_mode(){
// if addresses are over, return 1 and set addr to I2C_NOADDR
// if scan mode inactive, return 0 and set addr to I2C_NOADDR
int i2c_scan_next_addr(uint8_t *addr){
if(isI2Cbusy()) return 0;
*addr = i2caddr;
if(i2caddr == I2C_ADDREND){
*addr = I2C_ADDREND;
I2C_scan_mode = 0;
return 0;
}
/*while(!u3txrdy);
USND("Addr: "); USND(uhex2str(i2caddr)); USND("\n");
usart3_sendbuf();*/
if(!read_i2c_reg((i2caddr++)<<1, 0, NULL, 0)) return 0;
return 1;
}
// dump I2Cbuf
void i2c_bufdudump(){
if(goterr){
USND("Last transfer ends with error!\n");
goterr = 0;
}
USND("I2C buffer:\n");
hexdump(usart3_sendstr, I2Cbuf, i2cbuflen);
}
void i2c_have_DMA_Rx(){
if(!i2c_got_DMA_Rx) return;
i2c_got_DMA_Rx = 0;
i2c_bufdudump();
}
int i2cdma_haderr(){
int r = goterr;
goterr = 0;
return r;
}
// Rx/Tx interrupts
void dma1_channel1_isr(){
uint32_t isr = DMA1->ISR;
if(isr & (DMA_ISR_TCIF1 | DMA_ISR_TEIF1)){
if(isr & DMA_ISR_TEIF1) goterr = 1;
if(!(DMA1_Channel1->CCR & DMA_CCR_DIR)) i2c_got_DMA_Rx = 1; // last transfer was Rx
DMA1_Channel1->CCR = 0;
I2Cbusy = 0;
}
DMA1->IFCR = 0xf; // clear all flags for channel1
}