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added blink for STM32G0B1, next -> add USART

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This commit is contained in:
Edward Emelianov
2026-03-01 23:11:22 +03:00
parent 061fd8bec8
commit 1f4f111c52
18 changed files with 454 additions and 88 deletions
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37
G0:G070/inc/Fx/stm32g0.h
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@@ -19,8 +19,6 @@
* MA 02110-1301, USA.
*/
#pragma once
#ifndef __STM32F0_H__
#define __STM32F0_H__
#include "vector.h"
#include "stm32g0xx.h"
@@ -37,14 +35,14 @@
* R=2..8, Q=2..8, P=2..32; N=8..86, M=1..8
* fvco = 64..344MHz (after /M should be 2.66..16 -> for 8MHz HSE M=1..3!!!)
* For 8MHZ:
* fvco = (8/M)*N -> N(144)=18, M(144)=1
* fpllp = fvco/P (<=122MHz) -> P(72)=2
* fpllq = fvco/Q (<=128MHz) -> Q(48)=3
* fpllr = fvco/R (<=64MHz) -> R(48)=3
* AHB prescaler (36MHz) = 72/36 = 2
* APB prescaler (36MHz) = 36/36 = 1
* fvco = (8/M)*N -> N(128)=16, M(128)=1
* fpllp = fvco/P (<=122MHz) -> P(64)=2
* fpllq = fvco/Q (<=128MHz) -> Q(64)=2
* fpllr = fvco/R (<=64MHz) -> R(64)=2
* AHB prescaler (64MHz) = 1
* APB prescaler (64MHz) = 1
*
* fp=fq=fr=fsys=64MHz => M=1, N=8, P=1, Q=1, R=1
* fp=fq=fr=fsys=64MHz => M=1, N=16, P=2, Q=2, R=2
*/
#ifndef PLLN
#define PLLN 16
@@ -61,6 +59,12 @@
#ifndef PLLR
#define PLLR 2
#endif
#ifndef PPRE
#define PPRE 1
#endif
#ifndef HPRE
#define HPRE 1
#endif
#define WAITWHILE(x) do{register uint32_t StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){nop();}}while(0)
TRUE_INLINE void StartHSEHSI(int isHSE){
@@ -76,18 +80,19 @@ TRUE_INLINE void StartHSEHSI(int isHSE){
WAITWHILE(PWR->SR2 & PWR_SR2_VOSF);
if(isHSE){
RCC->PLLCFGR = ((PLLR-1)<<29) | ((PLLQ-1)<<25) | ((PLLP-1)<<17) | (PLLN<<8) | ((PLLM-1)<<4)
| RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLPEN /* | RCC_PLLCFGR_PLLQEN */
| RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN /* | RCC_PLLCFGR_PLLPEN */
| RCC_PLLCFGR_PLLSRC_HSE;
}else{ // 64MHz from HSI16
RCC->PLLCFGR = (8<<8) | (1<<4)
// enable P and/or Q if need
| RCC_PLLCFGR_PLLREN /* | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN */
// enable P if need
| RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN /* | RCC_PLLCFGR_PLLPEN */
| RCC_PLLCFGR_PLLSRC_HSI;
}
RCC->CR |= RCC_CR_PLLON;
WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_1;
RCC->CFGR = RCC_CFGR_SW_1; // set sysclk switch to pll
FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2; // FLASH_ACR_LATENCY_2 for 64MHz
// set sysclk switch to pll, setup AHB/APB
RCC->CFGR = RCC_CFGR_SW_1 | PPRE << 12 | HPRE << 8;
}
#define StartHSE() do{StartHSEHSI(1);}while(0)
@@ -253,7 +258,3 @@ TRUE_INLINE void StartHSEHSI(int isHSE){
//#define do{}while(0)
#endif // __STM32F0_H__

40
G0:G070/inc/Fx/stm32g0xx.h
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@@ -48,43 +48,9 @@
* @brief STM32 Family
*/
#if !defined (STM32G0)
#define STM32G0
#error "DEFINE STM32G0 first!"
#endif /* STM32G0 */
/* Uncomment the line below according to the target STM32G0 device used in your
application
*/
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \
&& !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \
&& !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \
&& !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx)
/* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */
/* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */
/* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */
/* #define STM32G070xx */ /*!< STM32G070xx Devices */
/* #define STM32G071xx */ /*!< STM32G071xx Devices */
/* #define STM32G081xx */ /*!< STM32G081xx Devices */
/* #define STM32G050xx */ /*!< STM32G050xx Devices */
/* #define STM32G051xx */ /*!< STM32G051xx Devices */
/* #define STM32G061xx */ /*!< STM32G061xx Devices */
/* #define STM32G030xx */ /*!< STM32G030xx Devices */
/* #define STM32G031xx */ /*!< STM32G031xx Devices */
/* #define STM32G041xx */ /*!< STM32G041xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number $VERSION$
*/
@@ -226,10 +192,6 @@ typedef enum
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32g0xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */

20
G0:G070/inc/Fx/vector.h
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@@ -35,34 +35,36 @@ void WEAK sys_tick_handler(void);
#if defined STM32G0
void WEAK wwdg_isr(void);
void WEAK pvd_vddio2_isr(void);
void WEAK rtc_isr(void);
void WEAK flash_isr(void);
void WEAK rcc_isr(void);
void WEAK exti0_1_isr(void);
void WEAK exti2_3_isr(void);
void WEAK exti4_15_isr(void);
void WEAK usb_ucpd1_2_isr(void);
void WEAK dma1_channel1_isr(void);
void WEAK dma1_channel2_3_isr(void);
void WEAK dmamux_isr(void);
void WEAK dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr(void);
void WEAK adc_comp_isr(void);
void WEAK tim1_brk_up_trg_com_isr(void);
void WEAK tim1_cc_isr(void);
void WEAK tim2_isr(void);
void WEAK tim3_4_isr(void);
void WEAK tim6_dac_isr(void);
void WEAK tim7_isr(void);
void WEAK tim6_dac_lptim1_isr(void);
void WEAK tim7_lptim2_isr(void);
void WEAK tim14_isr(void);
void WEAK tim15_isr(void);
void WEAK tim16_isr(void);
void WEAK tim17_isr(void);
void WEAK tim16_fdcan_it0_isr(void);
void WEAK tim17_fdcan_it1_isr(void);
void WEAK i2c1_isr(void);
void WEAK i2c2_3_isr(void);
void WEAK spi1_isr(void);
void WEAK spi2_3_isr(void);
void WEAK usart1_isr(void);
void WEAK usart2_isr(void);
void WEAK usart3_4_isr(void);
void WEAK cec_can_isr(void);
void WEAK usb_isr(void);
void WEAK usart2_lpuart2_isr(void);
void WEAK usart3_6_lpuart1_isr(void);
void WEAK cec_isr(void);
#else
#error "Not supported platform"
#endif

12
G0:G070/inc/ld/stm32g0b1xb.ld Normal file
View File

@@ -0,0 +1,12 @@
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
}
PROVIDE(_BLOCKSIZE = 2048);
/* Include the common ld script. */
INCLUDE stm32.ld

103
G0:G070/inc/startup/vector.c
View File

@@ -38,8 +38,7 @@ void null_handler(void);
#define NVIC_IRQ_COUNT 32
#if defined STM32G070xx
#define IRQ_HANDLERS \
#if defined(STM32G070xx)
[WWDG_IRQn] = wwdg_isr, \
[RTC_TAMP_IRQn] = rtc_isr, \
[FLASH_IRQn] = flash_isr, \
@@ -49,30 +48,61 @@ void null_handler(void);
[EXTI4_15_IRQn] = exti4_15_isr, \
[DMA1_Channel1_IRQn] = dma1_channel1_isr, \
[DMA1_Channel2_3_IRQn] = dma1_channel2_3_isr, \
[DMA1_Ch4_7_DMAMUX1_OVR_IRQn] = dmamux_isr, \
[DMA1_Ch4_7_DMAMUX1_OVR_IRQn] = dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr, \
[ADC1_IRQn] = adc_comp_isr, \
[TIM1_BRK_UP_TRG_COM_IRQn] = tim1_brk_up_trg_com_isr, \
[TIM1_CC_IRQn] = tim1_cc_isr, \
[TIM3_IRQn] = tim3_4_isr, \
[TIM6_IRQn] = tim6_dac_isr, \
[TIM7_IRQn] = tim7_isr, \
[TIM6_IRQn] = tim6_dac_lptim1_isr, \
[TIM7_IRQn] = tim7_lptim2_isr, \
[TIM14_IRQn] = tim14_isr, \
[TIM15_IRQn] = tim15_isr, \
[TIM16_IRQn] = tim16_isr, \
[TIM17_IRQn] = tim17_isr, \
[TIM16_IRQn] = tim16_fdcan_it0_isr, \
[TIM17_IRQn] = tim17_fdcan_it1_isr, \
[I2C1_IRQn] = i2c1_isr, \
[I2C2_IRQn] = i2c2_3_isr, \
[SPI1_IRQn] = spi1_isr, \
[SPI2_IRQn] = spi2_3_isr, \
[USART1_IRQn] = usart1_isr, \
[USART2_IRQn] = usart2_isr, \
[USART3_4_IRQn] = usart3_4_isr
[USART2_IRQn] = usart2_lpuart2_isr, \
[USART3_4_IRQn] = usart3_6_lpuart1_isr
#elif defined(STM32G0B1xx)
#define IRQ_HANDLERS \
[WWDG_IRQn] = wwdg_isr, \
[PVD_VDDIO2_IRQn] = pvd_vddio2_isr, \
[RTC_TAMP_IRQn] = rtc_isr, \
[FLASH_IRQn] = flash_isr, \
[RCC_CRS_IRQn] = rcc_isr, \
[EXTI0_1_IRQn] = exti0_1_isr, \
[EXTI2_3_IRQn] = exti2_3_isr, \
[EXTI4_15_IRQn] = exti4_15_isr, \
[USB_UCPD1_2_IRQn] = usb_ucpd1_2_isr, \
[DMA1_Channel1_IRQn] = dma1_channel1_isr, \
[DMA1_Channel2_3_IRQn] = dma1_channel2_3_isr, \
[DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn] = dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr, \
[ADC1_COMP_IRQn] = adc_comp_isr, \
[TIM1_BRK_UP_TRG_COM_IRQn] = tim1_brk_up_trg_com_isr, \
[TIM1_CC_IRQn] = tim1_cc_isr, \
[TIM2_IRQn] = tim2_isr, \
[TIM3_TIM4_IRQn] = tim3_4_isr, \
[TIM6_DAC_LPTIM1_IRQn] = tim6_dac_lptim1_isr, \
[TIM7_LPTIM2_IRQn] = tim7_lptim2_isr, \
[TIM14_IRQn] = tim14_isr, \
[TIM15_IRQn] = tim15_isr, \
[TIM16_FDCAN_IT0_IRQn] = tim16_fdcan_it0_isr, \
[TIM17_FDCAN_IT1_IRQn] = tim17_fdcan_it1_isr, \
[I2C1_IRQn] = i2c1_isr, \
[I2C2_3_IRQn] = i2c2_3_isr, \
[SPI1_IRQn] = spi1_isr, \
[SPI2_3_IRQn] = spi2_3_isr, \
[USART1_IRQn] = usart1_isr, \
[USART2_LPUART2_IRQn] = usart2_lpuart2_isr, \
[USART3_4_5_6_LPUART1_IRQn] = usart3_6_lpuart1_isr, \
[CEC_IRQn] = cec_isr
#else
#error "Not supported STM32G0 MCU"
#endif
typedef struct {
unsigned int *initial_sp_value; /**< Initial stack pointer value. */
vector_table_entry_t reset;
@@ -140,7 +170,7 @@ void null_handler(void)
#pragma weak pend_sv_handler = null_handler
#pragma weak sys_tick_handler = null_handler
#if defined STM32G0
#if defined STM32G070xx
#pragma weak wwdg_isr = blocking_handler
#pragma weak rtc_isr = blocking_handler
#pragma weak flash_isr = blocking_handler
@@ -150,25 +180,54 @@ void null_handler(void)
#pragma weak exti4_15_isr = blocking_handler
#pragma weak dma1_channel1_isr = blocking_handler
#pragma weak dma1_channel2_3_isr = blocking_handler
#pragma weak dmamux_isr = blocking_handler
#pragma weak dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr = blocking_handler
#pragma weak adc_comp_isr = blocking_handler
#pragma weak tim1_brk_up_trg_com_isr = blocking_handler
#pragma weak tim1_cc_isr = blocking_handler
#pragma weak tim3_4_isr = blocking_handler
#pragma weak tim6_dac_isr = blocking_handler
#pragma weak tim7_isr = blocking_handler
#pragma weak tim6_dac_lptim1_isr = blocking_handler
#pragma weak tim7_lptim2_isr = blocking_handler
#pragma weak tim14_isr = blocking_handler
#pragma weak tim15_isr = blocking_handler
#pragma weak tim16_isr = blocking_handler
#pragma weak tim17_isr = blocking_handler
#pragma weak tim16_fdcan_it0_isr = blocking_handler
#pragma weak tim17_fdcan_it1_isr = blocking_handler
#pragma weak i2c1_isr = blocking_handler
#pragma weak i2c2_3_isr = blocking_handler
#pragma weak spi1_isr = blocking_handler
#pragma weak spi2_3_isr = blocking_handler
#pragma weak usart1_isr = blocking_handler
#pragma weak usart2_isr = blocking_handler
#pragma weak usart3_4_isr = blocking_handler
#pragma weak cec_can_isr = blocking_handler
#pragma weak usb_isr = blocking_handler
#pragma weak usart2_lpuart2_isr = blocking_handler
#pragma weak usart3_6_lpuart1_isr = blocking_handler
#pragma weak cec_isr = blocking_handler
#elif defined STM32G0B1xx
#pragma weak wwdg_isr = blocking_handler
#pragma weak pvd_vddio2_isr = blocking_handler
#pragma weak rtc_isr = blocking_handler
#pragma weak flash_isr = blocking_handler
#pragma weak rcc_isr = blocking_handler
#pragma weak exti0_1_isr = blocking_handler
#pragma weak exti2_3_isr = blocking_handler
#pragma weak exti4_15_isr = blocking_handler
#pragma weak usb_ucpd1_2_isr = blocking_handler
#pragma weak dma1_channel1_isr = blocking_handler
#pragma weak dma1_channel2_3_isr = blocking_handler
#pragma weak dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr = blocking_handler
#pragma weak adc_comp_isr = blocking_handler
#pragma weak tim1_brk_up_trg_com_isr = blocking_handler
#pragma weak tim1_cc_isr = blocking_handler
#pragma weak tim3_4_isr = blocking_handler
#pragma weak tim6_dac_lptim1_isr = blocking_handler
#pragma weak tim7_lptim2_isr = blocking_handler
#pragma weak tim14_isr = blocking_handler
#pragma weak tim15_isr = blocking_handler
#pragma weak tim16_fdcan_it0_isr = blocking_handler
#pragma weak tim17_fdcan_it1_isr = blocking_handler
#pragma weak i2c1_isr = blocking_handler
#pragma weak i2c2_3_isr = blocking_handler
#pragma weak spi1_isr = blocking_handler
#pragma weak spi2_3_isr = blocking_handler
#pragma weak usart1_isr = blocking_handler
#pragma weak usart2_lpuart2_isr = blocking_handler
#pragma weak usart3_6_lpuart1_isr = blocking_handler
#pragma weak cec_isr = blocking_handler
#endif