diff --git a/.gitignore b/.gitignore index c5777ce..e9340e8 100644 --- a/.gitignore +++ b/.gitignore @@ -13,3 +13,5 @@ *.sublime-workspace *.bk *-bak +.qtcreator +.clang-format diff --git a/G0:G070/g0b1/Makefile b/G0:G070/g0b1/Makefile new file mode 100644 index 0000000..c0c8284 --- /dev/null +++ b/G0:G070/g0b1/Makefile @@ -0,0 +1,9 @@ +BINARY := test +# MCU code +MCU := G0B1xx +# change this linking script depending on particular MCU model, +LDSCRIPT := stm32g0b1xb.ld + +include ../makefile.g0 +include ../../makefile.stm32 + diff --git a/G0:G070/g0b1/README b/G0:G070/g0b1/README new file mode 100644 index 0000000..9012542 --- /dev/null +++ b/G0:G070/g0b1/README @@ -0,0 +1,3 @@ +Toggle LED on STM32G0B1-pill depending on user button: +- pressed - 'SOS' in Morze +- not pressed - blink with period of 1 second diff --git a/G0:G070/g0b1/main.c b/G0:G070/g0b1/main.c new file mode 100644 index 0000000..ecc9038 --- /dev/null +++ b/G0:G070/g0b1/main.c @@ -0,0 +1,86 @@ +/* + * This file is part of the blink project. + * Copyright 2023 Edward V. Emelianov . + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "stm32g0.h" + +#define KEY_PORT GPIOC +#define KEY_PIN (1<<13) +#define LED_PORT GPIOC +#define LED_PIN (1<<6) +#define KEY_PRESSED() (pin_read(KEY_PORT, KEY_PIN) == 1) +#define LED_ON() do{pin_set(LED_PORT, LED_PIN);}while(0) +#define LED_OFF() do{pin_clear(LED_PORT, LED_PIN);}while(0) + +// KEY (intpullup->0) - PC13 +// LED - PC6 + +static volatile uint32_t blink_ctr = 0; + +/* Called when systick fires */ +void sys_tick_handler(void){ + ++blink_ctr; +} + +/* + * Set up timer to fire every x milliseconds + */ +static void systick_setup(uint32_t xms){ // xms < 2098!!! + blink_ctr = 0; + static uint32_t curms = 0; + if(curms == xms) return; + // 8MHz - HCLK/8 + // this function also clears counter so it starts right away + SysTick_Config(8000 * xms); // arg should be < 0xffffff, so ms should be < 2098 + curms = xms; +} + +static void gpio_setup(void){ + RCC->IOPENR = RCC_IOPENR_GPIOCEN; // enable PC + // set PC8 as opendrain output, PC0 is pullup input, other as default (AIN) + GPIOC->MODER = (0xffffffff & ~(GPIO_MODER_MODE6 | GPIO_MODER_MODE13)) | GPIO_MODER_MODER6_O; // GPIO_MODER_MODER13_I == 0 + GPIOC->PUPDR = GPIO_PUPDR13_PD; // pull down +} + +static const uint32_t L[] = {125,100,125,100,125,200, 350,100,350,100,350,200, 125,100,125,100,125, 1000}; + +int main(void){ + StartHSE(); + gpio_setup(); + systick_setup(500); + uint32_t M = 0; + int pressed = 0; + /* Do nothing in main loop */ + while (1){ + if(KEY_PRESSED()){ // key pressed - 'sos' + pressed = 1; + systick_setup(L[M]); + if(M & 1) LED_OFF(); + else LED_ON(); + if(++M == 18) M = 0; + while(blink_ctr == 0); + }else{ // key not pressed - blink with period of 1s + if(pressed){ + M = 0; + pressed = 0; + systick_setup(500); + } + if(blink_ctr & 1) LED_ON(); + else LED_OFF(); + } + } +} diff --git a/G0:G070/g0b1/openocd.cfg b/G0:G070/g0b1/openocd.cfg new file mode 100644 index 0000000..f391d6e --- /dev/null +++ b/G0:G070/g0b1/openocd.cfg @@ -0,0 +1,4 @@ +set FLASH_SIZE 0x20000 + +source [find interface/stlink-v2-1.cfg] +source [find target/stm32g0x.cfg] diff --git a/G0:G070/g0b1/test.bin b/G0:G070/g0b1/test.bin new file mode 100755 index 0000000..6ba82a5 Binary files /dev/null and b/G0:G070/g0b1/test.bin differ diff --git a/G0:G070/g0b1/test.cflags b/G0:G070/g0b1/test.cflags new file mode 100644 index 0000000..68d5165 --- /dev/null +++ b/G0:G070/g0b1/test.cflags @@ -0,0 +1 @@ +-std=c17 \ No newline at end of file diff --git a/G0:G070/g0b1/test.config b/G0:G070/g0b1/test.config new file mode 100644 index 0000000..fb9ecef --- /dev/null +++ b/G0:G070/g0b1/test.config @@ -0,0 +1,3 @@ +#define EBUG +#define STM32G0 +#define STM32G0B1xx diff --git a/G0:G070/g0b1/test.creator b/G0:G070/g0b1/test.creator new file mode 100644 index 0000000..e94cbbd --- /dev/null +++ b/G0:G070/g0b1/test.creator @@ -0,0 +1 @@ +[General] diff --git a/G0:G070/g0b1/test.creator.user b/G0:G070/g0b1/test.creator.user new file mode 100644 index 0000000..e56686e --- /dev/null +++ b/G0:G070/g0b1/test.creator.user @@ -0,0 +1,214 @@ + + + + + + EnvironmentId + {7bd84e39-ca37-46d3-be9d-99ebea85bc0d} + + + ProjectExplorer.Project.ActiveTarget + 0 + + + ProjectExplorer.Project.EditorSettings + + true + true + true + + Cpp + + CppGlobal + + + + QmlJS + + QmlJSGlobal + + + 2 + KOI8-R + false + 4 + false + 0 + 80 + true + true + 1 + 0 + false + true + false + 0 + true + true + 0 + 8 + true + false + 1 + true + false + true + *.md, *.MD, Makefile + false + true + true + + + + ProjectExplorer.Project.PluginSettings + + + true + false + true + true + true + true + + false + + + 0 + true + + true + true + Builtin.DefaultTidyAndClazy + 2 + false + + + + true + + 0 + + + + ProjectExplorer.Project.Target.0 + + Desktop + true + Desktop + Desktop + {65a14f9e-e008-4c1b-89df-4eaa4774b6e3} + 0 + 0 + 0 + + /Big/Data/00__Electronics/STM32/G0-nolib/blink + + + + all + + true + GenericProjectManager.GenericMakeStep + + 1 + Build + Build + ProjectExplorer.BuildSteps.Build + + + + + clean + + true + GenericProjectManager.GenericMakeStep + + 1 + Clean + Clean + ProjectExplorer.BuildSteps.Clean + + 2 + false + + false + + По умолчанию + GenericProjectManager.GenericBuildConfiguration + 0 + 0 + + + 0 + Deploy + Deploy + ProjectExplorer.BuildSteps.Deploy + + 1 + + false + ProjectExplorer.DefaultDeployConfiguration + + 1 + + true + true + true + + 2 + + false + -e cpu-cycles --call-graph dwarf,4096 -F 250 + + ProjectExplorer.CustomExecutableRunConfiguration + + false + + true + true + + 1 + + 1 + + + 0 + Deploy + Deploy + ProjectExplorer.BuildSteps.Deploy + + 1 + + false + ProjectExplorer.DefaultDeployConfiguration + + 1 + + true + true + true + + 2 + + false + -e cpu-cycles --call-graph dwarf,4096 -F 250 + + ProjectExplorer.CustomExecutableRunConfiguration + + false + + true + true + + 1 + + + + ProjectExplorer.Project.TargetCount + 1 + + + Version + 22 + + diff --git a/G0:G070/g0b1/test.cxxflags b/G0:G070/g0b1/test.cxxflags new file mode 100644 index 0000000..6435dfc --- /dev/null +++ b/G0:G070/g0b1/test.cxxflags @@ -0,0 +1 @@ +-std=c++17 \ No newline at end of file diff --git a/G0:G070/g0b1/test.files b/G0:G070/g0b1/test.files new file mode 100644 index 0000000..59ab707 --- /dev/null +++ b/G0:G070/g0b1/test.files @@ -0,0 +1,2 @@ +main.c +systick_blink.c diff --git a/G0:G070/g0b1/test.includes b/G0:G070/g0b1/test.includes new file mode 100644 index 0000000..641fd56 --- /dev/null +++ b/G0:G070/g0b1/test.includes @@ -0,0 +1,4 @@ +. +../inc +../inc/Fx +../inc/cm diff --git a/G0:G070/inc/Fx/stm32g0.h b/G0:G070/inc/Fx/stm32g0.h index 2f7e34f..5b05384 100644 --- a/G0:G070/inc/Fx/stm32g0.h +++ b/G0:G070/inc/Fx/stm32g0.h @@ -19,8 +19,6 @@ * MA 02110-1301, USA. */ #pragma once -#ifndef __STM32F0_H__ -#define __STM32F0_H__ #include "vector.h" #include "stm32g0xx.h" @@ -37,14 +35,14 @@ * R=2..8, Q=2..8, P=2..32; N=8..86, M=1..8 * fvco = 64..344MHz (after /M should be 2.66..16 -> for 8MHz HSE M=1..3!!!) * For 8MHZ: - * fvco = (8/M)*N -> N(144)=18, M(144)=1 - * fpllp = fvco/P (<=122MHz) -> P(72)=2 - * fpllq = fvco/Q (<=128MHz) -> Q(48)=3 - * fpllr = fvco/R (<=64MHz) -> R(48)=3 - * AHB prescaler (36MHz) = 72/36 = 2 - * APB prescaler (36MHz) = 36/36 = 1 + * fvco = (8/M)*N -> N(128)=16, M(128)=1 + * fpllp = fvco/P (<=122MHz) -> P(64)=2 + * fpllq = fvco/Q (<=128MHz) -> Q(64)=2 + * fpllr = fvco/R (<=64MHz) -> R(64)=2 + * AHB prescaler (64MHz) = 1 + * APB prescaler (64MHz) = 1 * - * fp=fq=fr=fsys=64MHz => M=1, N=8, P=1, Q=1, R=1 + * fp=fq=fr=fsys=64MHz => M=1, N=16, P=2, Q=2, R=2 */ #ifndef PLLN #define PLLN 16 @@ -61,6 +59,12 @@ #ifndef PLLR #define PLLR 2 #endif +#ifndef PPRE +#define PPRE 1 +#endif +#ifndef HPRE +#define HPRE 1 +#endif #define WAITWHILE(x) do{register uint32_t StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){nop();}}while(0) TRUE_INLINE void StartHSEHSI(int isHSE){ @@ -76,18 +80,19 @@ TRUE_INLINE void StartHSEHSI(int isHSE){ WAITWHILE(PWR->SR2 & PWR_SR2_VOSF); if(isHSE){ RCC->PLLCFGR = ((PLLR-1)<<29) | ((PLLQ-1)<<25) | ((PLLP-1)<<17) | (PLLN<<8) | ((PLLM-1)<<4) - | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLPEN /* | RCC_PLLCFGR_PLLQEN */ + | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN /* | RCC_PLLCFGR_PLLPEN */ | RCC_PLLCFGR_PLLSRC_HSE; }else{ // 64MHz from HSI16 RCC->PLLCFGR = (8<<8) | (1<<4) - // enable P and/or Q if need - | RCC_PLLCFGR_PLLREN /* | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN */ + // enable P if need + | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN /* | RCC_PLLCFGR_PLLPEN */ | RCC_PLLCFGR_PLLSRC_HSI; } RCC->CR |= RCC_CR_PLLON; WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY)); - FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_1; - RCC->CFGR = RCC_CFGR_SW_1; // set sysclk switch to pll + FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2; // FLASH_ACR_LATENCY_2 for 64MHz + // set sysclk switch to pll, setup AHB/APB + RCC->CFGR = RCC_CFGR_SW_1 | PPRE << 12 | HPRE << 8; } #define StartHSE() do{StartHSEHSI(1);}while(0) @@ -253,7 +258,3 @@ TRUE_INLINE void StartHSEHSI(int isHSE){ //#define do{}while(0) - - - -#endif // __STM32F0_H__ diff --git a/G0:G070/inc/Fx/stm32g0xx.h b/G0:G070/inc/Fx/stm32g0xx.h index 1749bdf..238a806 100644 --- a/G0:G070/inc/Fx/stm32g0xx.h +++ b/G0:G070/inc/Fx/stm32g0xx.h @@ -48,43 +48,9 @@ * @brief STM32 Family */ #if !defined (STM32G0) -#define STM32G0 +#error "DEFINE STM32G0 first!" #endif /* STM32G0 */ -/* Uncomment the line below according to the target STM32G0 device used in your - application - */ - -#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \ - && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \ - && !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \ - && !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx) - /* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */ - /* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */ - /* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */ - /* #define STM32G070xx */ /*!< STM32G070xx Devices */ - /* #define STM32G071xx */ /*!< STM32G071xx Devices */ - /* #define STM32G081xx */ /*!< STM32G081xx Devices */ - /* #define STM32G050xx */ /*!< STM32G050xx Devices */ - /* #define STM32G051xx */ /*!< STM32G051xx Devices */ - /* #define STM32G061xx */ /*!< STM32G061xx Devices */ - /* #define STM32G030xx */ /*!< STM32G030xx Devices */ - /* #define STM32G031xx */ /*!< STM32G031xx Devices */ - /* #define STM32G041xx */ /*!< STM32G041xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - /** * @brief CMSIS Device version number $VERSION$ */ @@ -226,10 +192,6 @@ typedef enum * @} */ -#if defined (USE_HAL_DRIVER) - #include "stm32g0xx_hal.h" -#endif /* USE_HAL_DRIVER */ - #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/G0:G070/inc/Fx/vector.h b/G0:G070/inc/Fx/vector.h index ce63eea..96e1cb6 100644 --- a/G0:G070/inc/Fx/vector.h +++ b/G0:G070/inc/Fx/vector.h @@ -35,34 +35,36 @@ void WEAK sys_tick_handler(void); #if defined STM32G0 void WEAK wwdg_isr(void); +void WEAK pvd_vddio2_isr(void); void WEAK rtc_isr(void); void WEAK flash_isr(void); void WEAK rcc_isr(void); void WEAK exti0_1_isr(void); void WEAK exti2_3_isr(void); void WEAK exti4_15_isr(void); +void WEAK usb_ucpd1_2_isr(void); void WEAK dma1_channel1_isr(void); void WEAK dma1_channel2_3_isr(void); -void WEAK dmamux_isr(void); +void WEAK dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr(void); void WEAK adc_comp_isr(void); void WEAK tim1_brk_up_trg_com_isr(void); void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); void WEAK tim3_4_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); +void WEAK tim6_dac_lptim1_isr(void); +void WEAK tim7_lptim2_isr(void); void WEAK tim14_isr(void); void WEAK tim15_isr(void); -void WEAK tim16_isr(void); -void WEAK tim17_isr(void); +void WEAK tim16_fdcan_it0_isr(void); +void WEAK tim17_fdcan_it1_isr(void); void WEAK i2c1_isr(void); void WEAK i2c2_3_isr(void); void WEAK spi1_isr(void); void WEAK spi2_3_isr(void); void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_4_isr(void); -void WEAK cec_can_isr(void); -void WEAK usb_isr(void); +void WEAK usart2_lpuart2_isr(void); +void WEAK usart3_6_lpuart1_isr(void); +void WEAK cec_isr(void); #else #error "Not supported platform" #endif diff --git a/G0:G070/inc/ld/stm32g0b1xb.ld b/G0:G070/inc/ld/stm32g0b1xb.ld new file mode 100644 index 0000000..bfa5ec2 --- /dev/null +++ b/G0:G070/inc/ld/stm32g0b1xb.ld @@ -0,0 +1,12 @@ +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +PROVIDE(_BLOCKSIZE = 2048); + +/* Include the common ld script. */ +INCLUDE stm32.ld + diff --git a/G0:G070/inc/startup/vector.c b/G0:G070/inc/startup/vector.c index 958c534..db9c9da 100644 --- a/G0:G070/inc/startup/vector.c +++ b/G0:G070/inc/startup/vector.c @@ -38,8 +38,7 @@ void null_handler(void); #define NVIC_IRQ_COUNT 32 -#if defined STM32G070xx -#define IRQ_HANDLERS \ +#if defined(STM32G070xx) [WWDG_IRQn] = wwdg_isr, \ [RTC_TAMP_IRQn] = rtc_isr, \ [FLASH_IRQn] = flash_isr, \ @@ -49,30 +48,61 @@ void null_handler(void); [EXTI4_15_IRQn] = exti4_15_isr, \ [DMA1_Channel1_IRQn] = dma1_channel1_isr, \ [DMA1_Channel2_3_IRQn] = dma1_channel2_3_isr, \ - [DMA1_Ch4_7_DMAMUX1_OVR_IRQn] = dmamux_isr, \ + [DMA1_Ch4_7_DMAMUX1_OVR_IRQn] = dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr, \ [ADC1_IRQn] = adc_comp_isr, \ [TIM1_BRK_UP_TRG_COM_IRQn] = tim1_brk_up_trg_com_isr, \ [TIM1_CC_IRQn] = tim1_cc_isr, \ [TIM3_IRQn] = tim3_4_isr, \ - [TIM6_IRQn] = tim6_dac_isr, \ - [TIM7_IRQn] = tim7_isr, \ + [TIM6_IRQn] = tim6_dac_lptim1_isr, \ + [TIM7_IRQn] = tim7_lptim2_isr, \ [TIM14_IRQn] = tim14_isr, \ [TIM15_IRQn] = tim15_isr, \ - [TIM16_IRQn] = tim16_isr, \ - [TIM17_IRQn] = tim17_isr, \ + [TIM16_IRQn] = tim16_fdcan_it0_isr, \ + [TIM17_IRQn] = tim17_fdcan_it1_isr, \ [I2C1_IRQn] = i2c1_isr, \ [I2C2_IRQn] = i2c2_3_isr, \ [SPI1_IRQn] = spi1_isr, \ [SPI2_IRQn] = spi2_3_isr, \ [USART1_IRQn] = usart1_isr, \ - [USART2_IRQn] = usart2_isr, \ - [USART3_4_IRQn] = usart3_4_isr + [USART2_IRQn] = usart2_lpuart2_isr, \ + [USART3_4_IRQn] = usart3_6_lpuart1_isr +#elif defined(STM32G0B1xx) +#define IRQ_HANDLERS \ + [WWDG_IRQn] = wwdg_isr, \ + [PVD_VDDIO2_IRQn] = pvd_vddio2_isr, \ + [RTC_TAMP_IRQn] = rtc_isr, \ + [FLASH_IRQn] = flash_isr, \ + [RCC_CRS_IRQn] = rcc_isr, \ + [EXTI0_1_IRQn] = exti0_1_isr, \ + [EXTI2_3_IRQn] = exti2_3_isr, \ + [EXTI4_15_IRQn] = exti4_15_isr, \ + [USB_UCPD1_2_IRQn] = usb_ucpd1_2_isr, \ + [DMA1_Channel1_IRQn] = dma1_channel1_isr, \ + [DMA1_Channel2_3_IRQn] = dma1_channel2_3_isr, \ + [DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn] = dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr, \ + [ADC1_COMP_IRQn] = adc_comp_isr, \ + [TIM1_BRK_UP_TRG_COM_IRQn] = tim1_brk_up_trg_com_isr, \ + [TIM1_CC_IRQn] = tim1_cc_isr, \ + [TIM2_IRQn] = tim2_isr, \ + [TIM3_TIM4_IRQn] = tim3_4_isr, \ + [TIM6_DAC_LPTIM1_IRQn] = tim6_dac_lptim1_isr, \ + [TIM7_LPTIM2_IRQn] = tim7_lptim2_isr, \ + [TIM14_IRQn] = tim14_isr, \ + [TIM15_IRQn] = tim15_isr, \ + [TIM16_FDCAN_IT0_IRQn] = tim16_fdcan_it0_isr, \ + [TIM17_FDCAN_IT1_IRQn] = tim17_fdcan_it1_isr, \ + [I2C1_IRQn] = i2c1_isr, \ + [I2C2_3_IRQn] = i2c2_3_isr, \ + [SPI1_IRQn] = spi1_isr, \ + [SPI2_3_IRQn] = spi2_3_isr, \ + [USART1_IRQn] = usart1_isr, \ + [USART2_LPUART2_IRQn] = usart2_lpuart2_isr, \ + [USART3_4_5_6_LPUART1_IRQn] = usart3_6_lpuart1_isr, \ + [CEC_IRQn] = cec_isr #else #error "Not supported STM32G0 MCU" #endif - - typedef struct { unsigned int *initial_sp_value; /**< Initial stack pointer value. */ vector_table_entry_t reset; @@ -140,7 +170,7 @@ void null_handler(void) #pragma weak pend_sv_handler = null_handler #pragma weak sys_tick_handler = null_handler -#if defined STM32G0 +#if defined STM32G070xx #pragma weak wwdg_isr = blocking_handler #pragma weak rtc_isr = blocking_handler #pragma weak flash_isr = blocking_handler @@ -150,25 +180,54 @@ void null_handler(void) #pragma weak exti4_15_isr = blocking_handler #pragma weak dma1_channel1_isr = blocking_handler #pragma weak dma1_channel2_3_isr = blocking_handler -#pragma weak dmamux_isr = blocking_handler +#pragma weak dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr = blocking_handler #pragma weak adc_comp_isr = blocking_handler #pragma weak tim1_brk_up_trg_com_isr = blocking_handler #pragma weak tim1_cc_isr = blocking_handler #pragma weak tim3_4_isr = blocking_handler -#pragma weak tim6_dac_isr = blocking_handler -#pragma weak tim7_isr = blocking_handler +#pragma weak tim6_dac_lptim1_isr = blocking_handler +#pragma weak tim7_lptim2_isr = blocking_handler #pragma weak tim14_isr = blocking_handler #pragma weak tim15_isr = blocking_handler -#pragma weak tim16_isr = blocking_handler -#pragma weak tim17_isr = blocking_handler +#pragma weak tim16_fdcan_it0_isr = blocking_handler +#pragma weak tim17_fdcan_it1_isr = blocking_handler #pragma weak i2c1_isr = blocking_handler #pragma weak i2c2_3_isr = blocking_handler #pragma weak spi1_isr = blocking_handler #pragma weak spi2_3_isr = blocking_handler #pragma weak usart1_isr = blocking_handler -#pragma weak usart2_isr = blocking_handler -#pragma weak usart3_4_isr = blocking_handler -#pragma weak cec_can_isr = blocking_handler -#pragma weak usb_isr = blocking_handler +#pragma weak usart2_lpuart2_isr = blocking_handler +#pragma weak usart3_6_lpuart1_isr = blocking_handler +#pragma weak cec_isr = blocking_handler +#elif defined STM32G0B1xx +#pragma weak wwdg_isr = blocking_handler +#pragma weak pvd_vddio2_isr = blocking_handler +#pragma weak rtc_isr = blocking_handler +#pragma weak flash_isr = blocking_handler +#pragma weak rcc_isr = blocking_handler +#pragma weak exti0_1_isr = blocking_handler +#pragma weak exti2_3_isr = blocking_handler +#pragma weak exti4_15_isr = blocking_handler +#pragma weak usb_ucpd1_2_isr = blocking_handler +#pragma weak dma1_channel1_isr = blocking_handler +#pragma weak dma1_channel2_3_isr = blocking_handler +#pragma weak dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr = blocking_handler +#pragma weak adc_comp_isr = blocking_handler +#pragma weak tim1_brk_up_trg_com_isr = blocking_handler +#pragma weak tim1_cc_isr = blocking_handler +#pragma weak tim3_4_isr = blocking_handler +#pragma weak tim6_dac_lptim1_isr = blocking_handler +#pragma weak tim7_lptim2_isr = blocking_handler +#pragma weak tim14_isr = blocking_handler +#pragma weak tim15_isr = blocking_handler +#pragma weak tim16_fdcan_it0_isr = blocking_handler +#pragma weak tim17_fdcan_it1_isr = blocking_handler +#pragma weak i2c1_isr = blocking_handler +#pragma weak i2c2_3_isr = blocking_handler +#pragma weak spi1_isr = blocking_handler +#pragma weak spi2_3_isr = blocking_handler +#pragma weak usart1_isr = blocking_handler +#pragma weak usart2_lpuart2_isr = blocking_handler +#pragma weak usart3_6_lpuart1_isr = blocking_handler +#pragma weak cec_isr = blocking_handler #endif -