mirror of
https://github.com/eddyem/stm32samples.git
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207 lines
6.1 KiB
C
207 lines
6.1 KiB
C
/**
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******************************************************************************
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* @file stm32g0xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32G0xx device used in the target application
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* - To use or not the peripherals drivers in application code(i.e.
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* code will be based on direct access to peripherals registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018-2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32g0xx
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* @{
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*/
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#ifndef STM32G0xx_H
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#define STM32G0xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32G0)
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#error "DEFINE STM32G0 first!"
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#endif /* STM32G0 */
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/**
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* @brief CMSIS Device version number $VERSION$
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*/
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#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
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#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
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#define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
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#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
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|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
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|(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
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|(__STM32G0_CMSIS_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32G0B1xx)
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#include "stm32g0b1xx.h"
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#elif defined(STM32G0C1xx)
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#include "stm32g0c1xx.h"
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#elif defined(STM32G0B0xx)
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#include "stm32g0b0xx.h"
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#elif defined(STM32G071xx)
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#include "stm32g071xx.h"
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#elif defined(STM32G081xx)
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#include "stm32g081xx.h"
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#elif defined(STM32G070xx)
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#include "stm32g070xx.h"
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#elif defined(STM32G031xx)
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#include "stm32g031xx.h"
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#elif defined(STM32G041xx)
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#include "stm32g041xx.h"
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#elif defined(STM32G030xx)
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#include "stm32g030xx.h"
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#elif defined(STM32G051xx)
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#include "stm32g051xx.h"
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#elif defined(STM32G061xx)
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#include "stm32g061xx.h"
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#elif defined(STM32G050xx)
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#include "stm32g050xx.h"
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#else
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#error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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SUCCESS = 0,
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ERROR = !SUCCESS
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macros
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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/* Use of interrupt control for register exclusive access */
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/* Atomic 32-bit register access macro to set one or several bits */
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#define ATOMIC_SET_BIT(REG, BIT) \
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do { \
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uint32_t primask; \
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primask = __get_PRIMASK(); \
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__set_PRIMASK(1); \
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SET_BIT((REG), (BIT)); \
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__set_PRIMASK(primask); \
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} while(0)
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/* Atomic 32-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEAR_BIT(REG, BIT) \
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do { \
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uint32_t primask; \
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primask = __get_PRIMASK(); \
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__set_PRIMASK(1); \
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CLEAR_BIT((REG), (BIT)); \
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__set_PRIMASK(primask); \
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} while(0)
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/* Atomic 32-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint32_t primask; \
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primask = __get_PRIMASK(); \
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__set_PRIMASK(1); \
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MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
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__set_PRIMASK(primask); \
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} while(0)
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/* Atomic 16-bit register access macro to set one or several bits */
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#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
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/* Atomic 16-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
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/* Atomic 16-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
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/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* STM32G0xx_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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