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This commit is contained in:
Timur A. Fatkhullin 2024-12-13 14:41:32 +03:00
parent 6d7e7f14b5
commit eb09de7a21
1 changed files with 52 additions and 27 deletions
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79
raptor_eagle_ccd.cpp
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@ -107,6 +107,24 @@ R convertUIntTo12Bit(uint16_t counts)
return res;
}
std::string formatByteArr(const std::ranges::range auto& bytes, std::string_view delim = ", ")
requires std::integral<std::ranges::range_value_t<decltype(bytes)>>
{
std::string res;
auto sz = std::ranges::size(bytes);
if (!sz) {
return res;
}
for (auto const& el : bytes | std::views::take(sz - 1)) {
res += std::format("0x{:02X}{}", el, delim);
}
res += std::format("0x{:02X}", *(bytes.end() - 1));
return res;
}
} // namespace details
@ -392,21 +410,20 @@ size_t RaptorEagleCCD::clRead(byte_seq_t& bytes)
xclibApiCall(nbytes = pxd_serialRead(_cameraUnitmap, 0, nullptr, 0),
std::format("pxd_serialRead({}, 0, NULL, 0)", _cameraUnitmap));
logWarn("There are no bytes in Rx-buffer! Waiting for {} as timeout ...", CL_DEFAULT_TIMEOUT);
// if (!nbytes) {
// logWarn("There are no bytes in Rx-buffer! Nothing to do!");
// return 0;
// }
while ((std::chrono::steady_clock::now() - start_tp) <= CL_DEFAULT_TIMEOUT) {
std::this_thread::sleep_for(std::chrono::milliseconds(5));
nbytes = pxd_serialRead(_cameraUnitmap, 0, nullptr, 0);
}
if (!nbytes) {
logWarn("Cameralink reading operation timeout!");
return 0;
logWarn("There are no bytes in Rx-buffer! Waiting for {} as timeout ...", CL_DEFAULT_TIMEOUT);
while ((std::chrono::steady_clock::now() - start_tp) <= CL_DEFAULT_TIMEOUT) {
std::this_thread::sleep_for(std::chrono::milliseconds(5));
nbytes = pxd_serialRead(_cameraUnitmap, 0, nullptr, 0);
if (nbytes) {
break;
}
}
if (!nbytes) {
logWarn("Cameralink reading operation timeout!");
return 0;
}
}
nbytes += _clCommandAckBit + _clChecksumBit;
@ -416,15 +433,16 @@ size_t RaptorEagleCCD::clRead(byte_seq_t& bytes)
}
xclibApiCall(pxd_serialRead(_cameraUnitmap, 0, (char*)bytes.data(), nbytes),
std::format("pxd_serialRead({}, 0, {}, {})", _cameraUnitmap, (void*)bytes.data(), nbytes));
std::format("pxd_serialRead({}, 0, {}, {}) -> [{}]", _cameraUnitmap, (void*)bytes.data(), nbytes,
details::formatByteArr(bytes)));
if (_loggerSPtr->level() == spdlog::level::trace) {
std::string s;
adc::utils::AdcCharRangeFromValueRange(s, bytes, std::string_view(", "));
// if (_loggerSPtr->level() == spdlog::level::trace) {
// std::string s;
// adc::utils::AdcCharRangeFromValueRange(s, bytes, std::string_view(", "));
logTrace("Received from controller: [{}]", s);
}
// logTrace("Received from controller: [{}]", s);
// }
return nbytes;
}
@ -503,9 +521,14 @@ size_t RaptorEagleCCD::clWrite(const byte_seq_t& bytes)
logDebug("Write trailing ETX byte");
}
xclibApiCall(
pxd_serialWrite(_cameraUnitmap, 0, (char*)etx_checksum_bytes, tr_nbytes),
std::format("pxd_serialWrite({}, 0, {}, {})", _cameraUnitmap, (void*)etx_checksum_bytes, tr_nbytes));
xclibApiCall(pxd_serialWrite(_cameraUnitmap, 0, (char*)etx_checksum_bytes, tr_nbytes),
std::format("pxd_serialWrite({}, 0, {}, {})", _cameraUnitmap,
details::formatByteArr(std::string_view((const char*)etx_checksum_bytes, 2) |
std::views::take(tr_nbytes)),
tr_nbytes));
// xclibApiCall(
// pxd_serialWrite(_cameraUnitmap, 0, (char*)etx_checksum_bytes, tr_nbytes),
// std::format("pxd_serialWrite({}, 0, {}, {})", _cameraUnitmap, (void*)etx_checksum_bytes, tr_nbytes));
}
} else {
logWarn("No available space in the internal Tx-buffer! Nothing to do!");
@ -612,7 +635,7 @@ bool RaptorEagleCCD::resetMicro(const std::chrono::milliseconds& timeout)
do {
// poll camera with 'set-system-status'
clWrite({0x4F, 0x51});
//clWrite({0x4F, 0x50});
// clWrite({0x4F, 0x50});
std::this_thread::sleep_for(sleep_dur);
clRead(ack);
@ -644,9 +667,11 @@ bool RaptorEagleCCD::resetFPGA(const std::chrono::milliseconds& timeout)
std::chrono::milliseconds sleep_dur =
cnt > 10 ? std::chrono::milliseconds(cnt / 10) : std::chrono::milliseconds(10);
clearSystemStateBit(CL_SYSTEM_STATUS_FPGA_RST_HOLD_BIT); // set bit to 0 to hold FPGA in reset state
std::this_thread::sleep_for(std::chrono::milliseconds(100));
setSystemStateBit(CL_SYSTEM_STATUS_FPGA_RST_HOLD_BIT); // set bit to 1 to boot FPGA
// clearSystemStateBit(CL_SYSTEM_STATUS_FPGA_RST_HOLD_BIT); // set bit to 0 to hold FPGA in reset state
setSystemState(0x52);
std::this_thread::sleep_for(std::chrono::milliseconds(200));
setSystemState(0x50);
// setSystemStateBit(CL_SYSTEM_STATUS_FPGA_RST_HOLD_BIT); // set bit to 1 to boot FPGA
// according to instruction manual rev 1.1 FPGA will take approximately 500msecs to reset
std::this_thread::sleep_for(std::chrono::milliseconds(500));