mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 10:45:11 +03:00
231 lines
7.2 KiB
C
231 lines
7.2 KiB
C
/*
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* This file is part of the multistepper project.
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* Copyright 2023 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stm32f3.h>
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#include "hardware.h"
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#include "proto.h"
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extern volatile uint32_t Tms;
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#define MAXBUFLEN (8)
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// Rx timeout, ms
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#define PDNUART_TIMEOUT (20)
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// buffers format: 0 - sync+reserved, 1 - address (0..3 - slave, 0xff - master)
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// 2 - register<<1 | RW, 3 - CRC (r) or [ 3..6 - MSB data, 7 - CRC ]
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// buf[0] - USART2, buf[1] - USART3
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static uint8_t inbuf[2][MAXBUFLEN], outbuf[2][MAXBUFLEN];
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static uint8_t Taccess[2] = {0}; // last access time
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static int curslaveaddr[2] = {-1, -1}; // current slave address for each USART (0..3)
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static uint8_t notfound = 0; // not found mask (LSB - 0, MSB - 7)
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static uint8_t readrq[2] = {0}; // ==1 for read request (after send wait to read)
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// UART states
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typedef enum{
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PDU_IDLE,
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PDU_TX,
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PDU_TXREADY,
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PDU_RX,
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PDU_RXREADY
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} pdnuart_state;
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static pdnuart_state state[2] = {PDU_IDLE, PDU_IDLE};
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// datalen == 3 for read request or 7 for writing
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static void calcCRC(int no, int datalen){
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uint8_t crc = 0;
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for(int i = 0; i < datalen; ++i){
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uint8_t currentByte = outbuf[no][i];
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for(int j = 0; j < 8; ++j){
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if((crc >> 7) ^ (currentByte & 0x01)) crc = (crc << 1) ^ 0x07;
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else crc <<= 1;
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currentByte = currentByte >> 1;
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}
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}
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outbuf[no][datalen] = crc;
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}
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static volatile DMA_Channel_TypeDef *TxDMA[2] = {DMA1_Channel7, DMA1_Channel2};
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static volatile DMA_Channel_TypeDef *RxDMA[2] = {DMA1_Channel6, DMA1_Channel3};
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static volatile USART_TypeDef *USART[2] = {USART2, USART3};
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static void setup_usart(int no){
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USART[no]->ICR = 0xffffffff; // clear all flags
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TxDMA[no]->CCR = 0;
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TxDMA[no]->CPAR = (uint32_t) &USART[no]->TDR; // periph
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TxDMA[no]->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
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RxDMA[no]->CCR = 0;
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RxDMA[no]->CPAR = (uint32_t) &USART[no]->RDR; // periph
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RxDMA[no]->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE; // 8bit, mem++, per->mem, transcompl irq
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USART[no]->BRR = 72000000 / 256000; // 256 kbaud
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USART[no]->CR3 = USART_CR3_DMAT | USART_CR3_DMAR; // enable DMA Tx/Rx
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USART[no]->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART
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uint32_t tmout = 16000000;
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while(!(USART[no]->ISR & USART_ISR_TC)){if(--tmout == 0) break;} // polling idle frame Transmission
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USART[no]->ICR = 0xffffffff; // clear all flags again
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}
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// USART2 (ch0..3): DMA1ch6 (Rx), DMA1_ch7 (Tx)
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// USART3 (ch4..7): DMA1ch3 (Rx), DMA1_ch2 (Tx)
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// pins are setting up in `hardware.c`
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void pdnuart_setup(){
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RCC->APB1ENR |= RCC_APB1ENR_USART2EN | RCC_APB1ENR_USART3EN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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setup_usart(0);
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setup_usart(1);
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NVIC_EnableIRQ(DMA1_Channel2_IRQn);
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NVIC_EnableIRQ(DMA1_Channel3_IRQn);
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NVIC_EnableIRQ(DMA1_Channel6_IRQn);
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NVIC_EnableIRQ(DMA1_Channel7_IRQn);
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}
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static int rwreg(uint8_t motorno, uint8_t reg, uint32_t data, int w){
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if(motorno >= MOTORSNO || reg & 0x80) return FALSE;
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int no = motorno >> 2;
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if(state[no] != PDU_IDLE) return FALSE;
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outbuf[no][0] = 0xa0;
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outbuf[no][1] = curslaveaddr[no] = motorno - (no << 2);
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outbuf[no][2] = reg << 1;
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int nbytes = 3;
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if(w){
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outbuf[no][2] |= 1;
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for(int i = 6; i > 2; --i){
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outbuf[no][i] = data & 0xff;
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data >>= 8;
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}
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nbytes = 7;
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readrq[no] = 0;
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}else{
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readrq[no] = 1;
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}
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calcCRC(no, nbytes);
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TxDMA[no]->CMAR = (uint32_t) outbuf[no];
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TxDMA[no]->CNDTR = nbytes + 1;
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TxDMA[no]->CCR |= DMA_CCR_EN; // start transmission
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state[no] = PDU_TX;
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Taccess[no] = Tms;
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return TRUE;
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}
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// return FALSE if failed
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int pdnuart_writereg(uint8_t motorno, uint8_t reg, uint32_t data){
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return rwreg(motorno, reg, data, 1);
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}
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// return FALSE if failed
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int pdnuart_readreg(uint8_t motorno, uint8_t reg){
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return rwreg(motorno, reg, 0, 0);
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}
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static void disableDMA(int no){
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TxDMA[no]->CCR &= ~DMA_CCR_EN;
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RxDMA[no]->CCR &= ~DMA_CCR_EN;
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readrq[no] = 0;
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state[no] = PDU_IDLE;
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}
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static void parseRx(int no){
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USB_sendstr("Got from ");
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USB_putbyte('#'); printu(curslaveaddr[no] + no*4); USB_sendstr(": ");
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for(int i = 0; i < 8; ++i){
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printuhex(inbuf[no][i]); USB_putbyte(' ');
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}
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newline();
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}
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void pdnuart_poll(){
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for(int i = 0; i < 2; ++i){
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int showno = 0;
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uint32_t time = Tms - Taccess[i];
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switch(state[i]){
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case PDU_TX:
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if(time > PDNUART_TIMEOUT){
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USB_sendstr("PDN/UART timeout: Tx problem ");
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showno = 1;
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disableDMA(i);
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}
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break;
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case PDU_TXREADY:
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USB_sendstr("Tx ready ");
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showno = 1;
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break;
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case PDU_RX:
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if(time > PDNUART_TIMEOUT){
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USB_sendstr("PDN/UART timeout: no answer ");
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notfound |= 1 << (curslaveaddr[i] + 4*i);
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showno = 1;
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disableDMA(i);
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}
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break;
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case PDU_RXREADY:
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parseRx(i);
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state[i] = PDU_IDLE; // DMA already turned off
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break;
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default: // IDLE
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return;
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}
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if(showno){
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USB_putbyte('#'); printu(curslaveaddr[i] + 4*i); newline();
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}
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}
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}
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// USART2 Tx complete -> prepare Rx
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void dma1_channel7_isr(){
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DMA1_Channel7->CCR &= ~DMA_CCR_EN;
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DMA1->IFCR |= DMA_IFCR_CTCIF7;
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if(!readrq[0]){ // there was a setter
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state[0] = PDU_TXREADY;
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return;
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}
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DMA1_Channel6->CMAR = (uint32_t) inbuf[0];
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DMA1_Channel6->CCR |= DMA_CCR_EN;
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DMA1_Channel6->CNDTR = MAXBUFLEN;
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state[0] = PDU_RX;
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Taccess[0] = Tms;
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}
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// USART3 Tx complete -> prepare Rx
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void dma1_channel2_isr(){
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DMA1_Channel2->CCR &= ~DMA_CCR_EN;
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DMA1->IFCR |= DMA_IFCR_CTCIF2;
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if(!readrq[1]){ // there was a setter
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state[1] = PDU_TXREADY;
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return;
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}
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DMA1_Channel3->CMAR = (uint32_t) inbuf[1];
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DMA1_Channel3->CCR |= DMA_CCR_EN;
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DMA1_Channel3->CNDTR = MAXBUFLEN;
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state[1] = PDU_RX;
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Taccess[1] = Tms;
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}
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// USART2 Rx complete -> set flag
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void dma1_channel6_isr(){
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DMA1_Channel6->CCR &= ~DMA_CCR_EN;
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DMA1->IFCR |= DMA_IFCR_CTCIF6;
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state[0] = PDU_RXREADY;
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}
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// USART3 Rx complete -> set flag
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void dma1_channel3_isr(){
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DMA1_Channel3->CCR &= ~DMA_CCR_EN;
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DMA1->IFCR |= DMA_IFCR_CTCIF3;
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state[1] = PDU_RXREADY;
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}
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