mirror of
https://github.com/eddyem/stm32samples.git
synced 2026-03-20 08:40:57 +03:00
215 lines
6.4 KiB
C
215 lines
6.4 KiB
C
/*
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* This file is part of the usbcangpio project.
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* Copyright 2026 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "gpio.h"
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#include "i2c.h"
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// fields position in I2C1->TIMINGR
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#define I2C_TIMINGR_PRESC_Pos 28
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#define I2C_TIMINGR_SCLDEL_Pos 20
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#define I2C_TIMINGR_SDADEL_Pos 16
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#define I2C_TIMINGR_SCLH_Pos 8
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#define I2C_TIMINGR_SCLL_Pos 0
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i2c_speed_t curI2Cspeed = I2C_SPEED_10K;
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extern volatile uint32_t Tms;
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static uint32_t cntr;
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volatile uint8_t I2C_scan_mode = 0; // == 1 when I2C is in scan mode
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static uint8_t i2caddr = I2C_ADDREND; // address for `scan`, not active
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void i2c_setup(i2c_speed_t speed){
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if(speed >= I2C_SPEED_1M) speed = curI2Cspeed;
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else curI2Cspeed = speed;
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uint8_t PRESC, SCLDEL = 4, SDADEL = 2, SCLH, SCLL;
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I2C1->CR1 = 0;
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// I2C
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RCC->CFGR3 |= RCC_CFGR3_I2C1SW; // use sysclock for timing
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switch(curI2Cspeed){
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case I2C_SPEED_10K:
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PRESC = 0x0B;
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SCLH = 0xC3;
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SCLL = 0xC7;
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break;
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case I2C_SPEED_100K:
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PRESC = 0x0B;
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SCLH = 0x0F;
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SCLL = 0x13;
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break;
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case I2C_SPEED_400K:
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SDADEL = 3;
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SCLDEL = 3;
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PRESC = 5;
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SCLH = 3;
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SCLL = 9;
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break;
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case I2C_SPEED_1M:
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default:
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SDADEL = 0;
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SCLDEL = 1;
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PRESC = 5;
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SCLH = 1;
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SCLL = 3;
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break;
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}
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I2C1->TIMINGR = (PRESC<<I2C_TIMINGR_PRESC_Pos) | (SCLDEL<<I2C_TIMINGR_SCLDEL_Pos) |
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(SDADEL<<I2C_TIMINGR_SDADEL_Pos) | (SCLH<<I2C_TIMINGR_SCLH_Pos) | (SCLL<< I2C_TIMINGR_SCLL_Pos);
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if(speed < I2C_SPEED_400K){
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SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_I2C_FMP_I2C1;
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}else{ // activate FM+
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SYSCFG->CFGR1 |= SYSCFG_CFGR1_I2C_FMP_I2C1;
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}
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I2C1->ICR = 0xffff; // clear all errors
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I2C1->CR1 = I2C_CR1_PE;
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}
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void i2c_stop(){
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I2C1->CR1 = 0;
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}
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/**
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* write command byte to I2C
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* @param addr - device address (TSYS01_ADDR0 or TSYS01_ADDR1)
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* @param data - bytes to write
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* @param nbytes - amount of bytes to write
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* @param stop - to set STOP
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* @return 0 if error
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*/
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static uint8_t i2c_writes(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t stop){
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cntr = Tms;
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I2C1->CR1 = 0; // clear busy flag
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I2C1->ICR = 0x3f38; // clear all errors
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I2C1->CR1 = I2C_CR1_PE;
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while(I2C1->ISR & I2C_ISR_BUSY){
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IWDG->KR = IWDG_REFRESH;
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if(Tms - cntr > I2C_TIMEOUT){
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DBG("Line busy\n");
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return 0; // check busy
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}}
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cntr = Tms;
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while(I2C1->CR2 & I2C_CR2_START){
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IWDG->KR = IWDG_REFRESH;
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if(Tms - cntr > I2C_TIMEOUT){
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return 0; // check start
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}}
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//I2C1->ICR = 0x3f38; // clear all errors
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I2C1->CR2 = nbytes << 16 | addr;
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if(stop) I2C1->CR2 |= I2C_CR2_AUTOEND; // autoend
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// now start transfer
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I2C1->CR2 |= I2C_CR2_START;
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for(int i = 0; i < nbytes; ++i){
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cntr = Tms;
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while(!(I2C1->ISR & I2C_ISR_TXIS)){ // ready to transmit
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IWDG->KR = IWDG_REFRESH;
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if(I2C1->ISR & I2C_ISR_NACKF){
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I2C1->ICR |= I2C_ICR_NACKCF;
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DBG("NAK\n");
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return 0;
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}
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if(Tms - cntr > I2C_TIMEOUT){
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DBG("Timeout\n");
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return 0;
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}
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}
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I2C1->TXDR = data[i]; // send data
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}
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// wait for data gone
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while(I2C1->ISR & I2C_ISR_BUSY){
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IWDG->KR = IWDG_REFRESH;
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if(Tms - cntr > I2C_TIMEOUT){break;}
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}
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return 1;
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}
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uint8_t i2c_write(uint8_t addr, uint8_t *data, uint8_t nbytes){
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return i2c_writes(addr, data, nbytes, 1);
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}
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/**
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* read nbytes of data from I2C line
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* `data` should be an array with at least `nbytes` length
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* @return 1 if all OK, 0 if NACK or no device found
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*/
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static uint8_t i2c_readb(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t busychk){
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if(busychk){
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cntr = Tms;
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while(I2C1->ISR & I2C_ISR_BUSY){
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IWDG->KR = IWDG_REFRESH;
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if(Tms - cntr > I2C_TIMEOUT){
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DBG("Line busy\n");
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return 0; // check busy
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}}
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}
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cntr = Tms;
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while(I2C1->CR2 & I2C_CR2_START){
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IWDG->KR = IWDG_REFRESH;
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if(Tms - cntr > I2C_TIMEOUT){
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DBG("No start\n");
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return 0; // check start
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}}
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// read N bytes
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I2C1->CR2 = (nbytes<<16) | addr | 1 | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN;
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I2C1->CR2 |= I2C_CR2_START;
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uint8_t i;
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for(i = 0; i < nbytes; ++i){
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cntr = Tms;
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while(!(I2C1->ISR & I2C_ISR_RXNE)){ // wait for data
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IWDG->KR = IWDG_REFRESH;
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if(I2C1->ISR & I2C_ISR_NACKF){
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I2C1->ICR |= I2C_ICR_NACKCF;
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DBG("NAK\n");
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return 0;
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}
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if(Tms - cntr > I2C_TIMEOUT){
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DBG("Timeout\n");
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return 0;
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}
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}
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*data++ = I2C1->RXDR;
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}
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return 1;
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}
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uint8_t i2c_read(uint8_t addr, uint8_t *data, uint8_t nbytes){
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return i2c_readb(addr, data, nbytes, 1);
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}
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// read register reg
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uint8_t i2c_read_reg(uint8_t addr, uint8_t reg, uint8_t *data, uint8_t nbytes){
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if(!i2c_writes(addr, ®, 1, 0)) return 0;
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return i2c_readb(addr, data, nbytes, 0);
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}
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void i2c_init_scan_mode(){
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i2caddr = 1;
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I2C_scan_mode = 1;
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}
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// return 1 if next addr is active & return in as `addr`
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// if addresses are over, return 1 and set addr to I2C_NOADDR
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// if scan mode inactive, return 0 and set addr to I2C_NOADDR
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int i2c_scan_next_addr(uint8_t *addr){
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*addr = i2caddr;
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if(i2caddr == I2C_ADDREND){
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*addr = I2C_ADDREND;
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I2C_scan_mode = 0;
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return 0;
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}
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if(!i2c_read_reg((i2caddr++)<<1, 0, NULL, 0)) return 0;
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return 1;
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}
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