add CDC ACM

F0-nolib/pl2303/usb_lib.c

@@ -347,10 +347,11 @@ static uint16_t EP0_Handler(ep_t ep){
         epstatus = SET_STALL_TX(epstatus);
     } else if (ep.tx_flag){ // package transmitted
         // now we can change address after enumeration
-        if ((USB->DADDR & USB_DADDR_ADD) != USB_Dev.USB_Addr){
+        if(USB_Dev.USB_Addr){
             USB->DADDR = USB_DADDR_EF | USB_Dev.USB_Addr;
             // change state to ADRESSED
             USB_Dev.USB_Status = USB_ADRESSED_STATE;
+            USB_Dev.USB_Addr = 0; // clear address for re-enumeration
         }
         // end of transaction
         epstatus = CLEAR_DTOG_RX(epstatus);

F1-nolib/CDC_ACM/Makefile

@@ -0,0 +1,139 @@
+BINARY		= cdcacm
+BOOTPORT	?= /dev/ttyUSB0
+BOOTSPEED	?= 115200
+# MCU FAMILY
+FAMILY		?= F1
+# MCU code
+MCU			?= F103x8
+# density (stm32f10x.h, lines 70-84)
+DENSITY 	?= MD
+# change this linking script depending on particular MCU model,
+LDSCRIPT	?= stm32f103x8.ld
+# debug
+#DEFS		= -DEBUG
+
+INDEPENDENT_HEADERS=
+
+FP_FLAGS	?= -msoft-float -mfloat-abi=soft
+ASM_FLAGS	?= -mthumb -mcpu=cortex-m3 -mfix-cortex-m3-ldrd
+ARCH_FLAGS	= $(ASM_FLAGS) $(FP_FLAGS)
+
+###############################################################################
+# Executables
+#PREFIX		?= arm-none-eabi
+# gcc from arm web site 
+PREFIX		?= /opt/bin/arm-none-eabi
+TOOLCHLIB	?= /opt/arm-none-eabi/lib
+RM			:= rm -f
+RMDIR		:= rmdir
+CC			:= $(PREFIX)-gcc
+# don't replace ld with gcc: the binary size would be much greater!!
+LD			:= $(PREFIX)-ld
+AR			:= $(PREFIX)-ar
+AS			:= $(PREFIX)-as
+SIZE 		:= $(PREFIX)-size
+OBJCOPY		:= $(PREFIX)-objcopy
+OBJDUMP		:= $(PREFIX)-objdump
+GDB			:= $(PREFIX)-gdb
+STFLASH		:= $(shell which st-flash)
+STBOOT		:= $(shell which stm32flash)
+DFUUTIL		:= $(shell which dfu-util)
+
+###############################################################################
+# Source files
+OBJDIR 		= mk
+SRC			:= $(wildcard *.c)
+OBJS		:= $(addprefix $(OBJDIR)/, $(SRC:%.c=%.o))
+STARTUP		= $(OBJDIR)/startup.o
+OBJS 		+= $(STARTUP)
+# dependencies: we need them to recompile files if their headers-dependencies changed
+DEPS		:= $(OBJS:.o=.d)
+
+INC_DIR ?= ../inc
+
+INCLUDE 	:= -I$(INC_DIR)/Fx -I$(INC_DIR)/cm
+LIB_DIR		:= $(INC_DIR)/ld
+
+###############################################################################
+# C flags
+CFLAGS		+= -O2 -g -D__thumb2__=1 -MD
+CFLAGS		+= -Wall -Werror -Wextra -Wshadow 
+CFLAGS		+= -fno-common -ffunction-sections -fdata-sections -fno-stack-protector
+CFLAGS		+=  $(ARCH_FLAGS)
+
+###############################################################################
+# Linker flags
+LDFLAGS		+= -nostartfiles --static -nostdlibs 
+LDFLAGS		+= -L$(LIB_DIR) -L$(TOOLCHLIB)
+LDFLAGS		+= -T$(LDSCRIPT)
+
+###############################################################################
+# Used libraries
+LDLIBS		+=  -lc $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+
+PLATFRM		?= -DSTM32$(FAMILY) -DSTM32$(MCU) -DSTM32F10X_$(DENSITY)
+
+ELF		:= $(OBJDIR)/$(BINARY).elf
+LIST	:= $(OBJDIR)/$(BINARY).list
+BIN		:= $(BINARY).bin
+HEX		:= $(BINARY).hex
+
+all: bin list size
+
+elf: $(ELF)
+bin: $(BIN)
+hex: $(HEX)
+list: $(LIST)
+
+ifneq ($(MAKECMDGOALS),clean)
+-include $(DEPS)
+endif
+
+$(OBJDIR):
+	mkdir $(OBJDIR)
+
+$(STARTUP): $(INC_DIR)/startup/vector.c
+	$(CC) $(CFLAGS) $(DEFS) $(PLATFRM) $(INCLUDE) -o $@ -c $<
+
+$(OBJDIR)/%.o: %.c
+	@echo "  CC      $<"
+	$(CC) $(CFLAGS) $(DEFS) $(PLATFRM) $(INCLUDE) -o $@ -c $<
+
+$(BIN): $(ELF)
+	@echo "  OBJCOPY $(BIN)"
+	$(OBJCOPY) -Obinary $(ELF) $(BIN)
+
+$(HEX): $(ELF)
+	@echo "  OBJCOPY $(HEX)"
+	$(OBJCOPY) -Oihex $(ELF) $(HEX)
+
+$(LIST): $(ELF)
+	@echo "  OBJDUMP $(LIST)"
+	$(OBJDUMP) -S $(ELF) > $(LIST)
+
+$(ELF): $(OBJDIR) $(OBJS)
+	@echo "  LD      $(ELF)"
+	$(LD) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $(ELF)
+
+size: $(ELF)
+	$(SIZE) $(ELF)    
+
+clean:
+	@echo "  CLEAN"
+	$(RM) $(OBJS) $(DEPS) $(ELF) $(HEX) $(LIST)
+	@rmdir $(OBJDIR) 2>/dev/null || true
+
+
+flash: $(BIN)
+	@echo "  FLASH  $(BIN)"
+	$(STFLASH) write $(BIN) 0x8000000
+
+boot: $(BIN)
+	@echo "  LOAD $(BIN) through bootloader"
+	$(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN)
+
+dfuboot: $(BIN)
+	@echo "  LOAD  $(BIN) THROUGH DFU"
+	$(DFUUTIL) -a0 -D $(BIN) -s 0x08000000
+
+.PHONY: clean flash boot

F1-nolib/CDC_ACM/hardware.c

@@ -0,0 +1,41 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * hardware.c - hardware-dependent macros & functions
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#include "hardware.h"
+
+static inline void gpio_setup(){
+    // Enable clocks to the GPIO subsystems (PB for ADC), turn on AFIO clocking to disable SWD/JTAG
+    RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
+    // turn off SWJ/JTAG
+//    AFIO->MAPR = AFIO_MAPR_SWJ_CFG_DISABLE;
+    // turn off USB pullup
+    GPIOA->ODR = (1<<13); // turn off usb pullup & turn on pullups for buttons
+    // Set led as opendrain output
+    GPIOC->CRH |= CRH(13, CNF_ODOUTPUT|MODE_SLOW);
+    // USB pullup (PA13) - opendrain output
+    GPIOA->CRH = CRH(13, CNF_ODOUTPUT|MODE_SLOW);
+}
+
+void hw_setup(){
+    gpio_setup();
+}

F1-nolib/CDC_ACM/hardware.h

@@ -0,0 +1,45 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * hardware.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+#pragma once
+#ifndef __HARDWARE_H__
+#define __HARDWARE_H__
+
+#include "stm32f1.h"
+
+// LED0 - PC13 (bluepill), blinking each second
+#define LED0_port   GPIOC
+#define LED0_pin    (1<<13)
+
+// USB pullup (not present in bluepill) - PA13
+#define USBPU_port  GPIOA
+#define USBPU_pin   (1<<13)
+#define USBPU_ON()  pin_clear(USBPU_port, USBPU_pin)
+#define USBPU_OFF() pin_set(USBPU_port, USBPU_pin)
+
+#define LED_blink(x)    pin_toggle(x ## _port, x ## _pin)
+#define LED_on(x)       pin_clear(x ## _port, x ## _pin)
+#define LED_off(x)      pin_set(x ## _port, x ## _pin)
+
+void hw_setup();
+
+#endif // __HARDWARE_H__

F1-nolib/CDC_ACM/main.c

@@ -0,0 +1,175 @@
+/*
+ * main.c
+ *
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include "hardware.h"
+#include "usart.h"
+#include "usb.h"
+#include "usb_lib.h"
+
+volatile uint32_t Tms = 0;
+
+/* Called when systick fires */
+void sys_tick_handler(void){
+    ++Tms;
+}
+
+void iwdg_setup(){
+    uint32_t tmout = 16000000;
+    /* Enable the peripheral clock RTC */
+    /* (1) Enable the LSI (40kHz) */
+    /* (2) Wait while it is not ready */
+    RCC->CSR |= RCC_CSR_LSION; /* (1) */
+    while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
+    /* Configure IWDG */
+    /* (1) Activate IWDG (not needed if done in option bytes) */
+    /* (2) Enable write access to IWDG registers */
+    /* (3) Set prescaler by 64 (1.6ms for each tick) */
+    /* (4) Set reload value to have a rollover each 2s */
+    /* (5) Check if flags are reset */
+    /* (6) Refresh counter */
+    IWDG->KR = IWDG_START; /* (1) */
+    IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
+    IWDG->PR = IWDG_PR_PR_1; /* (3) */
+    IWDG->RLR = 1250; /* (4) */
+    tmout = 16000000;
+    while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
+    IWDG->KR = IWDG_REFRESH; /* (6) */
+}
+
+char *parse_cmd(char *buf){
+    if(buf[1] != '\n') return buf;
+    switch(*buf){
+        case 'p':
+            pin_toggle(USBPU_port, USBPU_pin);
+            USB_send("USB pullup is ");
+            if(pin_read(USBPU_port, USBPU_pin)) USB_send("off\n");
+            else USB_send("on\n");
+            return NULL;
+        break;
+        case 'L':
+            USB_send("Very long test string for USB (it's length is more than 64 bytes).\n"
+                     "This is another part of the string! Can you see all of this?\n");
+            return "OK\n";
+        break;
+        case 'R':
+            USB_send("Soft reset\n");
+            NVIC_SystemReset();
+        break;
+        case 'S':
+            USB_send("Test string for USB\n");
+            return "OK\n";
+        break;
+        case 'W':
+            USB_send("Wait for reboot\n");
+            while(1){nop();};
+        break;
+        default: // help
+            return
+            "'p' - toggle USB pullup\n"
+            "'L' - send long string over USB\n"
+            "'R' - software reset\n"
+            "'S' - send short string over USB\n"
+            "'W' - test watchdog\n"
+            ;
+        break;
+    }
+    return NULL;
+}
+
+// usb getline
+char *get_USB(){
+    static char tmpbuf[512], *curptr = tmpbuf;
+    static int rest = 511;
+    int x = USB_receive(curptr, rest);
+    curptr[x] = 0;
+    if(!x) return NULL;
+    if(curptr[x-1] == '\n'){
+        curptr = tmpbuf;
+        rest = 511;
+        return tmpbuf;
+    }
+    curptr += x; rest -= x;
+    if(rest <= 0){ // buffer overflow
+        curptr = tmpbuf;
+        rest = 511;
+    }
+    return NULL;
+}
+
+
+uint32_t newrate = 0;
+void linecoding_handler(usb_LineCoding *lcd){
+    newrate = lcd->dwDTERate;
+}
+uint16_t cl = 0xffff;
+void clstate_handler(uint16_t val){
+    cl = val;
+}
+int8_t br = 0;
+void break_handler(){
+    br = 1;
+}
+
+int main(void){
+    uint32_t lastT = 0, Tp = 499;
+    sysreset();
+    StartHSE();
+    SysTick_Config(72000);
+
+    hw_setup();
+    USBPU_OFF();
+    usart_setup();
+    if(RCC->CSR & RCC_CSR_IWDGRSTF){ // watchdog reset occured
+        SEND("WDGRESET=1"); newline();
+    }
+    if(RCC->CSR & RCC_CSR_SFTRSTF){ // software reset occured
+        SEND("SOFTRESET=1"); newline();
+    }
+    RCC->CSR |= RCC_CSR_RMVF; // remove reset flags
+
+    USB_setup();
+    iwdg_setup();
+    USBPU_ON();
+
+    while (1){
+        IWDG->KR = IWDG_REFRESH; // refresh watchdog
+        if(lastT > Tms || Tms - lastT > Tp){
+            LED_blink(LED0);
+            lastT = Tms;
+            USB_send("Hello!\n");
+        }
+        usb_proc();
+        if(USB_connected()) Tp = 999;
+        else Tp = 499;
+        char *txt, *ans;
+        if((txt = get_USB())){
+            ans = parse_cmd(txt);
+            if(ans) USB_send(ans);
+        }
+        int n = 0;
+        if(newrate){SEND("new speed: "); printu(newrate); n = 1; newrate = 0;}
+        if(cl!=0xffff){SEND("controls: "); printuhex(cl); n = 1; cl = 0xffff;}
+        if(br){SEND("break"); n = 1; br = 0;}
+        if(n) newline();
+    }
+    return 0;
+}
+

F1-nolib/CDC_ACM/usart.c

@@ -0,0 +1,233 @@
+/*
+ * usart.c
+ *
+ * Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include "stm32f1.h"
+#include "usart.h"
+
+extern volatile uint32_t Tms;
+static volatile int idatalen[2] = {0,0}; // received data line length (including '\n')
+static volatile int odatalen[2] = {0,0};
+
+volatile int linerdy = 0,        // received data ready
+    dlen = 0,           // length of data (including '\n') in current buffer
+    bufovr = 0,         // input buffer overfull
+    txrdy = 1           // transmission done
+;
+
+
+int rbufno = 0, tbufno = 0; // current rbuf/tbuf numbers
+static char rbuf[2][UARTBUFSZI], tbuf[2][UARTBUFSZO]; // receive & transmit buffers
+static char *recvdata = NULL;
+
+/**
+ * return length of received data (without trailing zero)
+ */
+int usart_getline(char **line){
+    if(bufovr){
+        bufovr = 0;
+        linerdy = 0;
+        return 0;
+    }
+    *line = recvdata;
+    linerdy = 0;
+    return dlen;
+}
+
+// transmit current tbuf and swap buffers
+void transmit_tbuf(){
+    uint32_t tmout = 16000000;
+    while(!txrdy){if(--tmout == 0) return;}; // wait for previos buffer transmission
+    register int l = odatalen[tbufno];
+    if(!l) return;
+    txrdy = 0;
+    odatalen[tbufno] = 0;
+    DMA1_Channel4->CCR &= ~DMA_CCR_EN;
+    DMA1_Channel4->CMAR = (uint32_t) tbuf[tbufno]; // mem
+    DMA1_Channel4->CNDTR = l;
+    DMA1_Channel4->CCR |= DMA_CCR_EN;
+    tbufno = !tbufno;
+}
+
+void usart_putchar(const char ch){
+    if(odatalen[tbufno] == UARTBUFSZO) transmit_tbuf();
+    tbuf[tbufno][odatalen[tbufno]++] = ch;
+}
+
+void usart_send(const char *str){
+    uint32_t x = 512;
+    while(*str && --x){
+        if(odatalen[tbufno] == UARTBUFSZO) transmit_tbuf();
+        tbuf[tbufno][odatalen[tbufno]++] = *str++;
+    }
+}
+
+void newline(){
+    usart_putchar('\n');
+    transmit_tbuf();
+}
+
+
+/*
+ * USART speed: baudrate = Fck/(USARTDIV)
+ * USARTDIV stored in USART->BRR
+ *
+ * for 72MHz USARTDIV=72000/f(kboud); so for 115200 USARTDIV=72000/115.2=625 -> BRR=0x271
+ *         9600: BRR = 7500 (0x1D4C)
+ */
+
+void usart_setup(){
+    uint32_t tmout = 16000000;
+    // PA9 - Tx, PA10 - Rx 
+    RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_AFIOEN;
+    RCC->AHBENR |= RCC_AHBENR_DMA1EN;
+    GPIOA->CRH = CRH(9, CNF_AFPP|MODE_NORMAL) | CRH(10, CNF_FLINPUT|MODE_INPUT); 
+
+    // USART1 Tx DMA - Channel4 (Rx - channel 5)
+    DMA1_Channel4->CPAR = (uint32_t) &USART1->DR; // periph
+    DMA1_Channel4->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
+    // Tx CNDTR set @ each transmission due to data size
+    NVIC_SetPriority(DMA1_Channel4_IRQn, 3);
+    NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+    NVIC_SetPriority(USART1_IRQn, 0);
+    // setup usart1
+    USART1->BRR = 72000000 / 115200;
+    USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART
+    while(!(USART1->SR & USART_SR_TC)){if(--tmout == 0) break;} // polling idle frame Transmission
+    USART1->SR = 0; // clear flags
+    USART1->CR1 |= USART_CR1_RXNEIE; // allow Rx IRQ
+    USART1->CR3 = USART_CR3_DMAT; // enable DMA Tx
+    NVIC_EnableIRQ(USART1_IRQn);
+}
+
+
+void usart1_isr(){
+    #ifdef CHECK_TMOUT
+    static uint32_t tmout = 0;
+    #endif
+    if(USART1->SR & USART_SR_RXNE){ // RX not emty - receive next char
+        #ifdef CHECK_TMOUT
+        if(tmout && Tms >= tmout){ // set overflow flag
+            bufovr = 1;
+            idatalen[rbufno] = 0;
+        }
+        tmout = Tms + TIMEOUT_MS;
+        if(!tmout) tmout = 1; // prevent 0
+        #endif
+        uint8_t rb = USART1->DR;
+        if(idatalen[rbufno] < UARTBUFSZI){ // put next char into buf
+            rbuf[rbufno][idatalen[rbufno]++] = rb;
+            if(rb == '\n'){ // got newline - line ready
+                linerdy = 1;
+                dlen = idatalen[rbufno];
+                recvdata = rbuf[rbufno];
+                // prepare other buffer
+                rbufno = !rbufno;
+                idatalen[rbufno] = 0;
+                #ifdef CHECK_TMOUT
+                // clear timeout at line end
+                tmout = 0;
+                #endif
+            }
+        }else{ // buffer overrun
+            bufovr = 1;
+            idatalen[rbufno] = 0;
+            #ifdef CHECK_TMOUT
+            tmout = 0;
+            #endif
+        }
+    }
+}
+
+// print 32bit unsigned int
+void printu(uint32_t val){
+    char bufa[11], bufb[10];
+    int l = 0, bpos = 0;
+    if(!val){
+        bufa[0] = '0';
+        l = 1;
+    }else{
+        while(val){
+            bufb[l++] = val % 10 + '0';
+            val /= 10;
+        }
+        int i;
+        bpos += l;
+        for(i = 0; i < l; ++i){
+            bufa[--bpos] = bufb[i];
+        }
+    }
+    bufa[l + bpos] = 0;
+    usart_send(bufa);
+}
+
+// print 32bit unsigned int as hex
+void printuhex(uint32_t val){
+    usart_send("0x");
+    uint8_t *ptr = (uint8_t*)&val + 3;
+    int i, j;
+    for(i = 0; i < 4; ++i, --ptr){
+        for(j = 1; j > -1; --j){
+            register uint8_t half = (*ptr >> (4*j)) & 0x0f;
+            if(half < 10) usart_putchar(half + '0');
+            else usart_putchar(half - 10 + 'a');
+        }
+    }
+}
+
+// dump memory buffer
+void hexdump(uint8_t *arr, uint16_t len){
+    for(uint16_t l = 0; l < len; ++l, ++arr){
+        for(int16_t j = 1; j > -1; --j){
+            register uint8_t half = (*arr >> (4*j)) & 0x0f;
+            if(half < 10) usart_putchar(half + '0');
+            else usart_putchar(half - 10 + 'a');
+        }
+        if(l % 16 == 15) usart_putchar('\n');
+        else if(l & 1) usart_putchar(' ');
+    }
+}
+
+void dma1_channel4_isr(){
+    if(DMA1->ISR & DMA_ISR_TCIF4){ // Tx
+        DMA1->IFCR = DMA_IFCR_CTCIF4; // clear TC flag
+        txrdy = 1;
+    }
+}
+
+/*
+#if USARTNUM == 2
+void dma1_channel4_5_isr(){
+    if(DMA1->ISR & DMA_ISR_TCIF4){ // Tx
+        DMA1->IFCR |= DMA_IFCR_CTCIF4; // clear TC flag
+        txrdy = 1;
+    }
+}
+// USART1
+#elif USARTNUM == 1
+void dma1_channel2_3_isr(){
+    if(DMA1->ISR & DMA_ISR_TCIF2){ // Tx
+        DMA1->IFCR |= DMA_IFCR_CTCIF2; // clear TC flag
+        txrdy = 1;
+    }
+}
+#else
+#error "Not implemented"
+#endif
+*/

F1-nolib/CDC_ACM/usart.h

@@ -0,0 +1,59 @@
+/*
+ * usart.h
+ *
+ * Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#pragma once
+#ifndef __USART_H__
+#define __USART_H__
+
+// input and output buffers size
+#define UARTBUFSZI  (16)
+#define UARTBUFSZO  (32)
+// timeout between data bytes
+#ifndef TIMEOUT_MS
+#define TIMEOUT_MS (1500)
+#endif
+
+// macro for static strings
+#define SEND(str) usart_send(str)
+
+#ifdef EBUG
+#define DBG(str)  do{SEND(__func__); SEND(": " str); newline();}while(0)
+#else
+#define MSG(str)
+#define DBG(str)
+#endif
+
+#define usartrx()  (linerdy)
+#define usartovr() (bufovr)
+
+extern volatile int linerdy, bufovr, txrdy;
+
+void transmit_tbuf();
+void usart_setup();
+int usart_getline(char **line);
+void usart_send(const char *str);
+void newline();
+void usart_putchar(const char ch);
+void printu(uint32_t val);
+void printuhex(uint32_t val);
+void hexdump(uint8_t *arr, uint16_t len);
+
+#endif // __USART_H__

F1-nolib/CDC_ACM/usb.c

@@ -0,0 +1,156 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb.c - base functions for different USB types
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+#include "usb.h"
+#include "usb_lib.h"
+#include "usart.h"
+
+// incoming buffer size
+#define IDATASZ     (256)
+static uint8_t incoming_data[IDATASZ];
+static uint8_t ovfl = 0;
+static uint16_t idatalen = 0;
+static volatile uint8_t tx_succesfull = 0;
+
+// interrupt IN handler (never used?)
+static uint16_t EP1_Handler(ep_t ep){
+    if (ep.rx_flag){
+        ep.status = SET_VALID_TX(ep.status);
+        ep.status = KEEP_STAT_RX(ep.status);
+    }else if (ep.tx_flag){
+        ep.status = SET_VALID_RX(ep.status);
+        ep.status = SET_STALL_TX(ep.status);
+    }
+    return ep.status;
+}
+
+// data IN/OUT handler
+static uint16_t EP23_Handler(ep_t ep){
+    if(ep.rx_flag){
+        int rd = ep.rx_cnt, rest = IDATASZ - idatalen;
+        if(rd){
+            if(rd <= rest){
+                idatalen += EP_Read(2, (uint16_t*)&incoming_data[idatalen]);
+                ovfl = 0;
+            }else{
+                ep.status = SET_NAK_RX(ep.status);
+                ovfl = 1;
+                return ep.status;
+            }
+        }
+        // end of transaction: clear DTOGs
+        ep.status = CLEAR_DTOG_RX(ep.status);
+        ep.status = CLEAR_DTOG_TX(ep.status);
+        ep.status = SET_STALL_TX(ep.status);
+    }else if (ep.tx_flag){
+        ep.status = KEEP_STAT_TX(ep.status);
+        tx_succesfull = 1;
+    }
+    ep.status = SET_VALID_RX(ep.status);
+    return ep.status;
+}
+
+void USB_setup(){
+    NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
+    NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);
+    RCC->APB1ENR |= RCC_APB1ENR_USBEN;
+    USB->CNTR   = USB_CNTR_FRES; // Force USB Reset
+    for(uint32_t ctr = 0; ctr < 72000; ++ctr) nop(); // wait >1ms
+    USB->CNTR   = 0;
+    USB->BTABLE = 0;
+    USB->DADDR  = 0;
+    USB->ISTR   = 0;
+    USB->CNTR   = USB_CNTR_RESETM | USB_CNTR_WKUPM; // allow only wakeup & reset interrupts
+    NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
+    NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn );
+}
+
+void usb_proc(){
+    switch(USB_Dev.USB_Status){
+        case USB_CONFIGURE_STATE:
+            // make new BULK endpoint
+            // Buffer have 1024 bytes, but last 256 we use for CAN bus (30.2 of RM: USB main features)
+            EP_Init(1, EP_TYPE_INTERRUPT, USB_EP1BUFSZ, 0, EP1_Handler); // IN1 - transmit
+            EP_Init(2, EP_TYPE_BULK, 0, USB_RXBUFSZ, EP23_Handler); // OUT2 - receive data
+            EP_Init(3, EP_TYPE_BULK, USB_TXBUFSZ, 0, EP23_Handler); // IN3 - transmit data
+            USB_Dev.USB_Status = USB_CONNECTED_STATE;
+        break;
+        case USB_DEFAULT_STATE:
+        case USB_ADRESSED_STATE:
+            usbON = 0;
+        default:
+            return;
+    }
+}
+
+void USB_send(const char *buf){
+    if(!usbON) return;
+    uint16_t l = 0, ctr = 0;
+    const char *p = buf;
+    while(*p++) ++l;
+    while(l){
+        uint16_t s = (l > USB_TXBUFSZ) ? USB_TXBUFSZ : l;
+        tx_succesfull = 0;
+        EP_Write(3, (uint8_t*)&buf[ctr], s);
+        uint32_t ctra = 1000000;
+        while(--ctra && tx_succesfull == 0);
+        if(tx_succesfull == 0){usbON = 0; DBG("USB disconnected"); return;} // usb is OFF?
+        l -= s;
+        ctr += s;
+    }
+}
+
+/**
+ * @brief USB_receive
+ * @param buf (i) - buffer for received data
+ * @param bufsize - its size
+ * @return amount of received bytes
+ */
+int USB_receive(char *buf, int bufsize){
+    if(!bufsize || !idatalen) return 0;
+    uint32_t oldcntr = USB->CNTR;
+    USB->CNTR = 0;
+    int sz = (idatalen > bufsize) ? bufsize : idatalen, rest = idatalen - sz;
+    for(int i = 0; i < sz; ++i) buf[i] = incoming_data[i];
+    if(rest > 0){
+        uint8_t *ptr = &incoming_data[sz];
+        for(int i = 0; i < rest; ++i) incoming_data[i] = *ptr++;
+        idatalen = rest;
+    }else idatalen = 0;
+    if(ovfl){
+        EP23_Handler(endpoints[2]);
+        uint16_t epstatus = USB->EPnR[2];
+        epstatus = CLEAR_DTOG_RX(epstatus);
+        epstatus = SET_VALID_RX(epstatus);
+        USB->EPnR[2] = epstatus;
+    }
+    USB->CNTR = oldcntr;
+    return sz;
+}
+
+/**
+ * @brief USB_configured
+ * @return 1 if USB is in configured state
+ */
+int USB_connected(){
+    return usbON;
+}

F1-nolib/CDC_ACM/usb.h

@@ -0,0 +1,37 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+#pragma once
+#ifndef __USB_H__
+#define __USB_H__
+
+#include "hardware.h"
+
+#define BUFFSIZE   (64)
+
+void USB_setup();
+void usb_proc();
+void USB_send(const char *buf);
+int USB_receive(char *buf, int bufsize);
+int USB_connected();
+
+#endif // __USB_H__

F1-nolib/CDC_ACM/usb_defs.h

@@ -0,0 +1,119 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb_defs.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#pragma once
+#ifndef __USB_DEFS_H__
+#define __USB_DEFS_H__
+
+#include <stm32f1.h>
+
+// max endpoints number
+#define STM32ENDPOINTS          8
+/**
+ *                 Buffers size definition
+ **/
+#define USB_BTABLE_SIZE         512
+// first 64 bytes of USB_BTABLE are registers!
+//#define USB_EP0_BASEADDR        64
+// for USB FS EP0 buffers are from 8 to 64 bytes long (64 for PL2303)
+#define USB_EP0_BUFSZ           64
+// USB transmit buffer size (64 for PL2303)
+#define USB_TXBUFSZ             64
+// USB receive buffer size (64 for PL2303)
+#define USB_RXBUFSZ             64
+// EP1 - interrupt - buffer size
+#define USB_EP1BUFSZ            8
+
+#define USB_BTABLE_BASE         0x40006000
+#define USB_BASE                ((uint32_t)0x40005C00)
+#define USB                     ((USB_TypeDef *) USB_BASE)
+
+#ifdef USB_BTABLE
+#undef USB_BTABLE
+#endif
+#define USB_BTABLE              ((USB_BtableDef *)(USB_BTABLE_BASE))
+#define USB_ISTR_EPID           0x0000000F
+#define USB_FNR_LSOF_0          0x00000800
+#define USB_FNR_lSOF_1          0x00001000
+#define USB_LPMCSR_BESL_0       0x00000010
+#define USB_LPMCSR_BESL_1       0x00000020
+#define USB_LPMCSR_BESL_2       0x00000040
+#define USB_LPMCSR_BESL_3       0x00000080
+#define USB_EPnR_CTR_RX         0x00008000
+#define USB_EPnR_DTOG_RX        0x00004000
+#define USB_EPnR_STAT_RX        0x00003000
+#define USB_EPnR_STAT_RX_0      0x00001000
+#define USB_EPnR_STAT_RX_1      0x00002000
+#define USB_EPnR_SETUP          0x00000800
+#define USB_EPnR_EP_TYPE        0x00000600
+#define USB_EPnR_EP_TYPE_0      0x00000200
+#define USB_EPnR_EP_TYPE_1      0x00000400
+#define USB_EPnR_EP_KIND        0x00000100
+#define USB_EPnR_CTR_TX         0x00000080
+#define USB_EPnR_DTOG_TX        0x00000040
+#define USB_EPnR_STAT_TX        0x00000030
+#define USB_EPnR_STAT_TX_0      0x00000010
+#define USB_EPnR_STAT_TX_1      0x00000020
+#define USB_EPnR_EA             0x0000000F
+#define USB_COUNTn_RX_BLSIZE    0x00008000
+#define USB_COUNTn_NUM_BLOCK    0x00007C00
+#define USB_COUNTn_RX           0x0000003F
+
+#ifdef USB_TypeDef
+#define USB_TypeDef USB_TypeDef_custom
+#endif
+
+typedef struct {
+    __IO uint32_t EPnR[STM32ENDPOINTS];
+    __IO uint32_t RESERVED[STM32ENDPOINTS];
+    __IO uint32_t CNTR;
+    __IO uint32_t ISTR;
+    __IO uint32_t FNR;
+    __IO uint32_t DADDR;
+    __IO uint32_t BTABLE;
+} USB_TypeDef;
+
+/*
+typedef struct{
+    __IO uint16_t USB_ADDR_TX;
+    __IO uint16_t res1;
+    __IO uint16_t USB_COUNT_TX;
+    __IO uint16_t res2;
+    __IO uint16_t USB_ADDR_RX;
+    __IO uint16_t res3;
+    __IO uint16_t USB_COUNT_RX;
+    __IO uint16_t res4;
+} USB_EPDATA_TypeDef;*/
+
+typedef struct{
+    __IO uint32_t USB_ADDR_TX;
+    __IO uint32_t USB_COUNT_TX;
+    __IO uint32_t USB_ADDR_RX;
+    __IO uint32_t USB_COUNT_RX;
+} USB_EPDATA_TypeDef;
+
+typedef struct{
+    __IO USB_EPDATA_TypeDef EP[STM32ENDPOINTS];
+} USB_BtableDef;
+
+#endif // __USB_DEFS_H__

F1-nolib/CDC_ACM/usb_lib.c

@@ -0,0 +1,542 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb_lib.c
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#include <stdint.h>
+#include "usart.h"
+#include "usb_lib.h"
+
+ep_t endpoints[STM32ENDPOINTS];
+
+usb_dev_t USB_Dev;
+static usb_LineCoding lineCoding = {115200, 0, 0, 8};
+config_pack_t setup_packet;
+static uint8_t ep0databuf[EP0DATABUF_SIZE];
+static uint8_t ep0dbuflen = 0;
+
+usb_LineCoding getLineCoding(){return lineCoding;}
+
+uint8_t usbON = 0; // device disconnected from terminal
+
+// definition of parts common for USB_DeviceDescriptor & USB_DeviceQualifierDescriptor
+#define bcdUSB_L        0x00
+#define bcdUSB_H        0x02
+#define bDeviceClass    0
+#define bDeviceSubClass 0
+#define bDeviceProtocol 0
+#define bNumConfigurations 1
+
+static const uint8_t USB_DeviceDescriptor[] = {
+        18,     // bLength
+        0x01,   // bDescriptorType - Device descriptor
+        bcdUSB_L,   // bcdUSB_L - 1.10
+        bcdUSB_H,   // bcdUSB_H
+        bDeviceClass,   // bDeviceClass - USB_COMM
+        bDeviceSubClass,   // bDeviceSubClass
+        bDeviceProtocol,   // bDeviceProtocol
+        USB_EP0_BUFSZ,   // bMaxPacketSize
+  /*  0x1915, 0x520f
+    0x15, 0x19, 0x0f, 0x52,*/
+        0xae,   // idVendor_L VID=0x25AE, PID=0x24AB
+        0x25,   // idVendor_H
+        0xab,   // idProduct_L
+        0x24,   // idProduct_H
+
+        0x00,   // bcdDevice_Ver_L
+        0x01,   // bcdDevice_Ver_H
+        0x01,   // iManufacturer
+        0x02,   // iProduct
+        0x03,   // iSerialNumber
+        bNumConfigurations    // bNumConfigurations
+};
+
+static const uint8_t USB_DeviceQualifierDescriptor[] = {
+        10,     //bLength
+        0x06,   // bDescriptorType - Device qualifier
+        bcdUSB_L,   // bcdUSB_L
+        bcdUSB_H,   // bcdUSB_H
+        bDeviceClass,   // bDeviceClass
+        bDeviceSubClass,   // bDeviceSubClass
+        bDeviceProtocol,   // bDeviceProtocol
+        USB_EP0_BUFSZ,   // bMaxPacketSize0
+        bNumConfigurations,   // bNumConfigurations
+        0x00    // Reserved
+};
+
+static const uint8_t USB_ConfigDescriptor[] = {
+    /*Configuration Descriptor*/
+    0x09, /* bLength: Configuration Descriptor size */
+    0x02, /* bDescriptorType: Configuration */
+    67,   /* wTotalLength:no of returned bytes */
+    0x00,
+    0x02, /* bNumInterfaces: 2 interface */
+    0x01, /* bConfigurationValue: Configuration value */
+    0x00, /* iConfiguration: Index of string descriptor describing the configuration */
+    0x80, /* bmAttributes - Bus powered */
+    0x32, /* MaxPower 100 mA */
+
+    /*---------------------------------------------------------------------------*/
+
+    /*Interface Descriptor */
+    0x09, /* bLength: Interface Descriptor size */
+    0x04, /* bDescriptorType: Interface */
+    0x00, /* bInterfaceNumber: Number of Interface */
+    0x00, /* bAlternateSetting: Alternate setting */
+    0x01, /* bNumEndpoints: One endpoints used */
+    0x02, /* bInterfaceClass: Communication Interface Class */
+    0x02, /* bInterfaceSubClass: Abstract Control Model */
+    0x01, /* bInterfaceProtocol: Common AT commands */
+    0x00, /* iInterface: */
+
+    /*Header Functional Descriptor*/
+    0x05, /* bLength: Endpoint Descriptor size */
+    0x24, /* bDescriptorType: CS_INTERFACE */
+    0x00, /* bDescriptorSubtype: Header Func Desc */
+    0x10, /* bcdCDC: spec release number */
+    0x01,
+
+    /*Call Management Functional Descriptor*/
+    0x05, /* bFunctionLength */
+    0x24, /* bDescriptorType: CS_INTERFACE */
+    0x01, /* bDescriptorSubtype: Call Management Func Desc */
+    0x00, /* bmCapabilities: D0+D1 */
+    0x01, /* bDataInterface: 1 */
+
+    /*ACM Functional Descriptor*/
+    0x04, /* bFunctionLength */
+    0x24, /* bDescriptorType: CS_INTERFACE */
+    0x02, /* bDescriptorSubtype: Abstract Control Management desc */
+    0x02, /* bmCapabilities */
+
+    /*Union Functional Descriptor*/
+    0x05, /* bFunctionLength */
+    0x24, /* bDescriptorType: CS_INTERFACE */
+    0x06, /* bDescriptorSubtype: Union func desc */
+    0x00, /* bMasterInterface: Communication class interface */
+    0x01, /* bSlaveInterface0: Data Class Interface */
+
+    /*Endpoint 1 Descriptor*/
+    0x07, /* bLength: Endpoint Descriptor size */
+    0x05, /* bDescriptorType: Endpoint */
+    0x81, /* bEndpointAddress IN1 */
+    0x03, /* bmAttributes: Interrupt */
+    (USB_EP1BUFSZ & 0xff), /* wMaxPacketSize LO: */
+    (USB_EP1BUFSZ >> 8), /* wMaxPacketSize HI: */
+    0x10, /* bInterval: */
+    /*---------------------------------------------------------------------------*/
+
+    /*Data class interface descriptor*/
+    0x09, /* bLength: Endpoint Descriptor size */
+    0x04, /* bDescriptorType: */
+    0x01, /* bInterfaceNumber: Number of Interface */
+    0x00, /* bAlternateSetting: Alternate setting */
+    0x02, /* bNumEndpoints: Two endpoints used */
+    0x0A, /* bInterfaceClass: CDC */
+    0x02, /* bInterfaceSubClass: */
+    0x00, /* bInterfaceProtocol: */
+    0x00, /* iInterface: */
+
+    /*Endpoint IN3 Descriptor*/
+    0x07, /* bLength: Endpoint Descriptor size */
+    0x05, /* bDescriptorType: Endpoint */
+    0x83, /* bEndpointAddress IN3 */
+    0x02, /* bmAttributes: Bulk */
+    (USB_TXBUFSZ & 0xff), /* wMaxPacketSize: 64 */
+    (USB_TXBUFSZ >> 8),
+    0x00, /* bInterval: ignore for Bulk transfer */
+
+    /*Endpoint OUT2 Descriptor*/
+    0x07, /* bLength: Endpoint Descriptor size */
+    0x05, /* bDescriptorType: Endpoint */
+    0x02, /* bEndpointAddress */
+    0x02, /* bmAttributes: Bulk */
+    (USB_TXBUFSZ & 0xff), /* wMaxPacketSize: 64 */
+    (USB_TXBUFSZ >> 8),
+    0x00 /* bInterval: ignore for Bulk transfer */
+};
+
+
+_USB_LANG_ID_(USB_StringLangDescriptor, LANG_US);
+_USB_STRING_(USB_StringSerialDescriptor, u"000001");
+_USB_STRING_(USB_StringManufacturingDescriptor, u"Eddy @ SAO RAS");
+_USB_STRING_(USB_StringProdDescriptor, u"USB-Serial Controller");
+
+
+/*
+ * default handlers
+ */
+// SET_LINE_CODING
+void WEAK linecoding_handler(usb_LineCoding __attribute__((unused)) *lcd){
+}
+
+// SET_CONTROL_LINE_STATE
+void WEAK clstate_handler(uint16_t __attribute__((unused)) val){
+}
+
+// SEND_BREAK
+void WEAK break_handler(){
+}
+
+static uint16_t wr0(const uint8_t *buf, uint16_t size, uint16_t status){
+    if(setup_packet.wLength < size) size = setup_packet.wLength; // shortened request
+    if(size < endpoints[0].txbufsz){
+        EP_WriteIRQ(0, buf, size);
+        return status;
+    }
+    while(size){
+        uint16_t l = size;
+        if(l > endpoints[0].txbufsz) l = endpoints[0].txbufsz;
+        EP_WriteIRQ(0, buf, l);
+        buf += l;
+        size -= l;
+        uint8_t needzlp = (l == endpoints[0].txbufsz) ? 1 : 0;
+        if(size || needzlp){ // send last data buffer
+            status = SET_NAK_RX(status);
+            status = SET_VALID_TX(status);
+            status = KEEP_DTOG_TX(status);
+            status = KEEP_DTOG_RX(status);
+            status = CLEAR_CTR_RX(status);
+            status = CLEAR_CTR_TX(status);
+            USB->ISTR = 0;
+            USB->EPnR[0] = status;
+            uint32_t ctr = 1000000;
+            while(--ctr && (USB->ISTR & USB_ISTR_CTR) == 0);
+            if((USB->ISTR & USB_ISTR_CTR) == 0){
+                return USB->EPnR[0];
+            }
+            USB->ISTR = 0;
+            status = USB->EPnR[0];
+            if(needzlp) EP_WriteIRQ(0, (uint8_t*)0, 0);
+        }
+    }
+    return status;
+}
+
+static inline uint16_t get_descriptor(uint16_t status){
+    switch(setup_packet.wValue){
+        case DEVICE_DESCRIPTOR:
+            status = wr0(USB_DeviceDescriptor, sizeof(USB_DeviceDescriptor), status);
+        break;
+        case CONFIGURATION_DESCRIPTOR:
+            status = wr0(USB_ConfigDescriptor, sizeof(USB_ConfigDescriptor), status);
+        break;
+        case STRING_LANG_DESCRIPTOR:
+            status = wr0((const uint8_t *)&USB_StringLangDescriptor, STRING_LANG_DESCRIPTOR_SIZE_BYTE, status);
+        break;
+        case STRING_MAN_DESCRIPTOR:
+            status = wr0((const uint8_t *)&USB_StringManufacturingDescriptor, USB_StringManufacturingDescriptor.bLength, status);
+        break;
+        case STRING_PROD_DESCRIPTOR:
+            status = wr0((const uint8_t *)&USB_StringProdDescriptor, USB_StringProdDescriptor.bLength, status);
+        break;
+        case STRING_SN_DESCRIPTOR:
+            status = wr0((const uint8_t *)&USB_StringSerialDescriptor, USB_StringSerialDescriptor.bLength, status);
+        break;
+        case DEVICE_QUALIFIER_DESCRIPTOR:
+            status = wr0(USB_DeviceQualifierDescriptor, USB_DeviceQualifierDescriptor[0], status);
+        break;
+        default:
+        break;
+    }
+    return status;
+}
+
+static uint8_t configuration = 0; // reply for GET_CONFIGURATION (==1 if configured)
+static inline uint16_t std_d2h_req(uint16_t status){
+    uint16_t state = 0; // bus powered
+    switch(setup_packet.bRequest){
+        case GET_DESCRIPTOR:
+            status = get_descriptor(status);
+        break;
+        case GET_STATUS:
+            EP_WriteIRQ(0, (uint8_t *)&state, 2); // send status: Bus Powered
+        break;
+        case GET_CONFIGURATION:
+            EP_WriteIRQ(0, &configuration, 1);
+        break;
+        default:
+        break;
+    }
+    return status;
+}
+
+static inline void std_h2d_req(){
+    switch(setup_packet.bRequest){
+        case SET_ADDRESS:
+            // new address will be assigned later - after  acknowlegement or request to host
+            USB_Dev.USB_Addr = setup_packet.wValue;
+        break;
+        case SET_CONFIGURATION:
+            // Now device configured
+            USB_Dev.USB_Status = USB_CONFIGURE_STATE;
+            configuration = setup_packet.wValue;
+        break;
+        default:
+        break;
+    }
+}
+
+/*
+bmRequestType: 76543210
+7    direction: 0 - host->device, 1 - device->host
+65   type: 0 - standard, 1 - class, 2 - vendor
+4..0 getter: 0 - device, 1 - interface, 2 - endpoint, 3 - other
+*/
+/**
+ * Endpoint0 (control) handler
+ * @param ep - endpoint state
+ * @return data written to EP0R
+ */
+static uint16_t EP0_Handler(ep_t ep){
+    uint16_t epstatus = ep.status; // EP0R on input -> return this value after modifications
+    uint8_t reqtype = setup_packet.bmRequestType & 0x7f;
+    uint8_t dev2host = (setup_packet.bmRequestType & 0x80) ? 1 : 0;
+    if ((ep.rx_flag) && (ep.setup_flag)){
+        switch(reqtype){
+            case STANDARD_DEVICE_REQUEST_TYPE: // standard device request
+                if(dev2host){
+                    epstatus = std_d2h_req(epstatus);
+                }else{
+                    std_h2d_req();
+                    EP_WriteIRQ(0, (uint8_t *)0, 0);
+                }
+                epstatus = SET_NAK_RX(epstatus);
+                epstatus = SET_VALID_TX(epstatus);
+            break;
+            case STANDARD_ENDPOINT_REQUEST_TYPE: // standard endpoint request
+                if(setup_packet.bRequest == CLEAR_FEATURE){
+                    EP_WriteIRQ(0, (uint8_t *)0, 0);
+                    epstatus = SET_NAK_RX(epstatus);
+                    epstatus = SET_VALID_TX(epstatus);
+                }
+            break;
+            case CONTROL_REQUEST_TYPE:
+                switch(setup_packet.bRequest){
+                    case GET_LINE_CODING:
+                        EP_WriteIRQ(0, (uint8_t*)&lineCoding, sizeof(lineCoding));
+                    break;
+                    case SET_LINE_CODING: // omit this for next stage, when data will come
+                    break;
+                    case SET_CONTROL_LINE_STATE:
+                        usbON = 1;
+                        clstate_handler(setup_packet.wValue);
+                    break;
+                    case SEND_BREAK:
+                        break_handler();
+                    break;
+                    default:
+                    break;
+                }
+                //if(!dev2host) EP_WriteIRQ(0, (uint8_t *)0, 0); // write acknowledgement
+                if(setup_packet.bRequest != GET_LINE_CODING) EP_WriteIRQ(0, (uint8_t *)0, 0);
+                epstatus = SET_VALID_RX(epstatus);
+                epstatus = SET_VALID_TX(epstatus);
+            break;
+            default:
+                EP_WriteIRQ(0, (uint8_t *)0, 0);
+                epstatus = SET_NAK_RX(epstatus);
+                epstatus = SET_VALID_TX(epstatus);
+        }
+    }else if (ep.rx_flag){ // got data over EP0 or host acknowlegement
+        if(ep.rx_cnt){
+            if(setup_packet.bRequest == SET_LINE_CODING){
+                linecoding_handler((usb_LineCoding*)ep0databuf);
+            }
+        }
+        // Close transaction
+        epstatus = CLEAR_DTOG_RX(epstatus);
+        epstatus = CLEAR_DTOG_TX(epstatus);
+        // wait for new data from host
+        epstatus = SET_VALID_RX(epstatus);
+        epstatus = SET_STALL_TX(epstatus);
+    } else if (ep.tx_flag){ // package transmitted
+        // now we can change address after enumeration
+        if ((USB->DADDR & USB_DADDR_ADD) != USB_Dev.USB_Addr){
+            USB->DADDR = USB_DADDR_EF | USB_Dev.USB_Addr;
+            // change state to ADRESSED
+            USB_Dev.USB_Status = USB_ADRESSED_STATE;
+        }
+        // end of transaction
+        epstatus = CLEAR_DTOG_RX(epstatus);
+        epstatus = CLEAR_DTOG_TX(epstatus);
+        epstatus = SET_VALID_RX(epstatus);
+        epstatus = SET_VALID_TX(epstatus);
+    }
+    return epstatus;
+}
+
+static uint16_t lastaddr = LASTADDR_DEFAULT;
+/**
+ * Endpoint initialisation
+ * @param number - EP num (0...7)
+ * @param type - EP type (EP_TYPE_BULK, EP_TYPE_CONTROL, EP_TYPE_ISO, EP_TYPE_INTERRUPT)
+ * @param txsz - transmission buffer size @ USB/CAN buffer
+ * @param rxsz - reception buffer size @ USB/CAN buffer
+ * @param uint16_t (*func)(ep_t *ep) - EP handler function
+ * @return 0 if all OK
+ */
+int EP_Init(uint8_t number, uint8_t type, uint16_t txsz, uint16_t rxsz, uint16_t (*func)(ep_t ep)){
+    if(number >= STM32ENDPOINTS) return 4; // out of configured amount
+    if(txsz > USB_BTABLE_SIZE || rxsz > USB_BTABLE_SIZE) return 1; // buffer too large
+    if(lastaddr + txsz + rxsz >= USB_BTABLE_SIZE) return 2; // out of btable
+    USB->EPnR[number] = (type << 9) | (number & USB_EPnR_EA);
+    USB->EPnR[number] ^= USB_EPnR_STAT_RX | USB_EPnR_STAT_TX_1;
+    if(rxsz & 1 || rxsz > 512) return 3; // wrong rx buffer size
+    uint16_t countrx = 0;
+    if(rxsz < 64) countrx = rxsz / 2;
+    else{
+        if(rxsz & 0x1f) return 3; // should be multiple of 32
+        countrx = 31 + rxsz / 32;
+    }
+    USB_BTABLE->EP[number].USB_ADDR_TX = lastaddr;
+    endpoints[number].tx_buf = (uint16_t *)(USB_BTABLE_BASE + lastaddr*2);
+    endpoints[number].txbufsz = txsz;
+    lastaddr += txsz;
+    USB_BTABLE->EP[number].USB_COUNT_TX = 0;
+    USB_BTABLE->EP[number].USB_ADDR_RX = lastaddr;
+    endpoints[number].rx_buf = (uint16_t *)(USB_BTABLE_BASE + lastaddr*2);
+    lastaddr += rxsz;
+    USB_BTABLE->EP[number].USB_COUNT_RX = countrx << 10;
+    endpoints[number].func = func;
+    return 0;
+}
+
+//extern int8_t dump;
+// standard IRQ handler
+void usb_isr(){
+    if (USB->ISTR & USB_ISTR_RESET){
+        usbON = 0;
+        // Reinit registers
+        USB->CNTR = USB_CNTR_RESETM | USB_CNTR_CTRM;// | USB_CNTR_SUSPM;
+        USB->ISTR = 0;
+        // Endpoint 0 - CONTROL
+        // ON USB LS size of EP0 may be 8 bytes, but on FS it should be 64 bytes!
+        lastaddr = LASTADDR_DEFAULT;
+        // clear address, leave only enable bit
+        USB->DADDR = USB_DADDR_EF;
+        // state is default - wait for enumeration
+        USB_Dev.USB_Status = USB_DEFAULT_STATE;
+        if(EP_Init(0, EP_TYPE_CONTROL, USB_EP0_BUFSZ, USB_EP0_BUFSZ, EP0_Handler)){
+            return;
+        }
+    }else if(USB->ISTR & USB_ISTR_CTR){
+        // EP number
+        uint8_t n = USB->ISTR & USB_ISTR_EPID;
+        // copy status register
+        uint16_t epstatus = USB->EPnR[n];
+    //  dump = 1;
+        // Calculate flags
+        endpoints[n].rx_flag = (epstatus & USB_EPnR_CTR_RX) ? 1 : 0;
+        endpoints[n].setup_flag = (epstatus & USB_EPnR_SETUP) ? 1 : 0;
+        endpoints[n].tx_flag = (epstatus & USB_EPnR_CTR_TX) ? 1 : 0;
+        // copy received bytes amount
+        endpoints[n].rx_cnt = USB_BTABLE->EP[n].USB_COUNT_RX & 0x3FF; // low 10 bits is counter
+        // check direction
+        if(USB->ISTR & USB_ISTR_DIR){ // OUT interrupt - receive data, CTR_RX==1 (if CTR_TX == 1 - two pending transactions: receive following by transmit)
+            if(n == 0){ // control endpoint
+                if(epstatus & USB_EPnR_SETUP){ // setup packet -> copy data to conf_pack
+                    EP_Read(0, (uint16_t*)&setup_packet);
+                    ep0dbuflen = 0;
+                    // interrupt handler will be called later
+                }else if(epstatus & USB_EPnR_CTR_RX){ // data packet -> push received data to ep0databuf
+                    ep0dbuflen = endpoints[0].rx_cnt;
+                    EP_Read(0, (uint16_t*)&ep0databuf);
+                }
+            }
+        }else{ // IN interrupt - transmit data, only CTR_TX == 1
+            // enumeration end could be here (if EP0)
+        }
+        // prepare status field for EP handler
+        endpoints[n].status = epstatus;
+        // call EP handler (even if it will change EPnR, it should return new status)
+        epstatus = endpoints[n].func(endpoints[n]);
+        // keep DTOG state
+        epstatus = KEEP_DTOG_TX(epstatus);
+        epstatus = KEEP_DTOG_RX(epstatus);
+        // clear all RX/TX flags
+        epstatus = CLEAR_CTR_RX(epstatus);
+        epstatus = CLEAR_CTR_TX(epstatus);
+        // refresh EPnR
+        USB->EPnR[n] = epstatus;
+    }else if(USB->ISTR & USB_ISTR_SUSP){ // suspend -> usb disconnected
+        // usbON = 0;
+    }
+    USB->ISTR = 0;
+}
+
+void usb_lp_can_rx0_isr(){
+    usb_isr();
+}
+
+void usb_hp_can_tx_isr(){
+    usb_isr();
+}
+
+/**
+ * Write data to EP buffer (called from IRQ handler)
+ * @param number - EP number
+ * @param *buf - array with data
+ * @param size - its size
+ */
+void EP_WriteIRQ(uint8_t number, const uint8_t *buf, uint16_t size){
+    uint8_t i;
+    if(size > USB_TXBUFSZ) size = USB_TXBUFSZ;
+    uint16_t N2 = (size + 1) >> 1;
+    // the buffer is 16-bit, so we should copy data as it would be uint16_t
+    uint16_t *buf16 = (uint16_t *)buf;
+    uint32_t *out = (uint32_t *)endpoints[number].tx_buf;
+    for(i = 0; i < N2; ++i, ++out){
+        *out = buf16[i];
+    }
+    USB_BTABLE->EP[number].USB_COUNT_TX = size;
+}
+
+/**
+ * Write data to EP buffer (called outside IRQ handler)
+ * @param number - EP number
+ * @param *buf - array with data
+ * @param size - its size
+ */
+void EP_Write(uint8_t number, const uint8_t *buf, uint16_t size){
+    uint16_t status = USB->EPnR[number];
+    EP_WriteIRQ(number, buf, size);
+    status = SET_NAK_RX(status);
+    status = SET_VALID_TX(status);
+    status = KEEP_DTOG_TX(status);
+    status = KEEP_DTOG_RX(status);
+    USB->EPnR[number] = status;
+}
+
+/*
+ * Copy data from EP buffer into user buffer area
+ * @param *buf - user array for data
+ * @return amount of data read
+ */
+int EP_Read(uint8_t number, uint16_t *buf){
+    int n = (endpoints[number].rx_cnt + 1) >> 1;
+    uint32_t *in = (uint32_t *)endpoints[number].rx_buf;
+    if(n){
+        for(int i = 0; i < n; ++i, ++in)
+            buf[i] = *(uint16_t*)in;
+    }
+    return endpoints[number].rx_cnt;
+}

F1-nolib/CDC_ACM/usb_lib.h

@@ -0,0 +1,205 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb_lib.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#pragma once
+#ifndef __USB_LIB_H__
+#define __USB_LIB_H__
+
+#include <wchar.h>
+#include "usb_defs.h"
+
+#define EP0DATABUF_SIZE                 (64)
+#define LASTADDR_DEFAULT                (STM32ENDPOINTS * 8)
+
+// Max EP amount (EP0 + other used)
+//#define ENDPOINTS_NUM                   4
+// bmRequestType & 0x7f
+#define STANDARD_DEVICE_REQUEST_TYPE    0
+#define STANDARD_ENDPOINT_REQUEST_TYPE  2
+#define VENDOR_REQUEST_TYPE             0x40
+#define CONTROL_REQUEST_TYPE            0x21
+// bRequest, standard; for bmRequestType == 0x80
+#define GET_STATUS                      0x00
+#define GET_DESCRIPTOR                  0x06
+#define GET_CONFIGURATION               0x08
+// for bmRequestType == 0
+#define CLEAR_FEATURE                   0x01
+#define SET_FEATURE                     0x03    // unused
+#define SET_ADDRESS                     0x05
+#define SET_DESCRIPTOR                  0x07    // unused
+#define SET_CONFIGURATION               0x09
+// for bmRequestType == 0x81, 1 or 0xB2
+#define GET_INTERFACE                   0x0A    // unused
+#define SET_INTERFACE                   0x0B    // unused
+#define SYNC_FRAME                      0x0C    // unused
+#define VENDOR_REQUEST                  0x01    // unused
+
+// Class-Specific Control Requests
+#define SEND_ENCAPSULATED_COMMAND       0x00    // unused
+#define GET_ENCAPSULATED_RESPONSE       0x01    // unused
+#define SET_COMM_FEATURE                0x02    // unused
+#define GET_COMM_FEATURE                0x03    // unused
+#define CLEAR_COMM_FEATURE              0x04    // unused
+#define SET_LINE_CODING                 0x20
+#define GET_LINE_CODING                 0x21
+#define SET_CONTROL_LINE_STATE          0x22
+#define SEND_BREAK                      0x23
+
+// control line states
+#define CONTROL_DTR                     0x01
+#define CONTROL_RTS                     0x02
+
+// wValue
+#define DEVICE_DESCRIPTOR               0x100
+#define CONFIGURATION_DESCRIPTOR        0x200
+#define STRING_LANG_DESCRIPTOR          0x300
+#define STRING_MAN_DESCRIPTOR           0x301
+#define STRING_PROD_DESCRIPTOR          0x302
+#define STRING_SN_DESCRIPTOR            0x303
+#define DEVICE_QUALIFIER_DESCRIPTOR     0x600
+
+// EPnR bits manipulation
+#define CLEAR_DTOG_RX(R)                (R & USB_EPnR_DTOG_RX) ? R : (R & (~USB_EPnR_DTOG_RX))
+#define SET_DTOG_RX(R)                  (R & USB_EPnR_DTOG_RX) ? (R & (~USB_EPnR_DTOG_RX)) : R
+#define TOGGLE_DTOG_RX(R)               (R | USB_EPnR_DTOG_RX)
+#define KEEP_DTOG_RX(R)                 (R & (~USB_EPnR_DTOG_RX))
+#define CLEAR_DTOG_TX(R)                (R & USB_EPnR_DTOG_TX) ? R : (R & (~USB_EPnR_DTOG_TX))
+#define SET_DTOG_TX(R)                  (R & USB_EPnR_DTOG_TX) ? (R & (~USB_EPnR_DTOG_TX)) : R
+#define TOGGLE_DTOG_TX(R)               (R | USB_EPnR_DTOG_TX)
+#define KEEP_DTOG_TX(R)                 (R & (~USB_EPnR_DTOG_TX))
+#define SET_VALID_RX(R)                 ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX)   | (R & (~USB_EPnR_STAT_RX))
+#define SET_NAK_RX(R)                   ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX_1) | (R & (~USB_EPnR_STAT_RX))
+#define SET_STALL_RX(R)                 ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX_0) | (R & (~USB_EPnR_STAT_RX))
+#define KEEP_STAT_RX(R)                 (R & (~USB_EPnR_STAT_RX))
+#define SET_VALID_TX(R)                 ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX)   | (R & (~USB_EPnR_STAT_TX))
+#define SET_NAK_TX(R)                   ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX_1) | (R & (~USB_EPnR_STAT_TX))
+#define SET_STALL_TX(R)                 ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX_0) | (R & (~USB_EPnR_STAT_TX))
+#define KEEP_STAT_TX(R)                 (R & (~USB_EPnR_STAT_TX))
+#define CLEAR_CTR_RX(R)                 (R & (~USB_EPnR_CTR_RX))
+#define CLEAR_CTR_TX(R)                 (R & (~USB_EPnR_CTR_TX))
+#define CLEAR_CTR_RX_TX(R)              (R & (~(USB_EPnR_CTR_TX | USB_EPnR_CTR_RX)))
+
+// USB state: uninitialized, addressed, ready for use
+#define USB_DEFAULT_STATE               0
+#define USB_ADRESSED_STATE              1
+#define USB_CONFIGURE_STATE             2
+#define USB_CONNECTED_STATE             3
+
+// EP types
+#define EP_TYPE_BULK                    0x00
+#define EP_TYPE_CONTROL                 0x01
+#define EP_TYPE_ISO                     0x02
+#define EP_TYPE_INTERRUPT               0x03
+
+#define LANG_US (uint16_t)0x0409
+
+#define _USB_STRING_(name, str)                  \
+static const struct name \
+{                          \
+        uint8_t  bLength;                       \
+        uint8_t  bDescriptorType;               \
+        uint16_t bString[(sizeof(str) - 2) / 2]; \
+    \
+} \
+name = {sizeof(name), 0x03, str}
+
+#define _USB_LANG_ID_(name, lng_id)     \
+    \
+static const struct name \
+{         \
+        uint8_t  bLength;         \
+        uint8_t  bDescriptorType; \
+        uint16_t bString;         \
+    \
+} \
+name = {0x04, 0x03, lng_id}
+#define STRING_LANG_DESCRIPTOR_SIZE_BYTE    (4)
+
+// EP0 configuration packet
+typedef struct {
+    uint8_t bmRequestType;
+    uint8_t bRequest;
+    uint16_t wValue;
+    uint16_t wIndex;
+    uint16_t wLength;
+} config_pack_t;
+
+// endpoints state
+typedef struct __ep_t{
+    uint16_t *tx_buf;           // transmission buffer address
+    uint16_t txbufsz;           // transmission buffer size
+    uint16_t *rx_buf;           // reception buffer address
+    uint16_t (*func)();         // endpoint action function
+    uint16_t status;            // status flags
+    unsigned rx_cnt  : 10;      // received data counter
+    unsigned tx_flag : 1;       // transmission flag
+    unsigned rx_flag : 1;       // reception flag
+    unsigned setup_flag : 1;    // this is setup packet (only for EP0)
+} ep_t;
+
+// USB status & its address
+typedef struct {
+    uint8_t  USB_Status;
+    uint16_t USB_Addr;
+}usb_dev_t;
+
+typedef struct {
+    uint32_t dwDTERate;
+    uint8_t bCharFormat;
+    #define USB_CDC_1_STOP_BITS   0
+    #define USB_CDC_1_5_STOP_BITS 1
+    #define USB_CDC_2_STOP_BITS   2
+    uint8_t bParityType;
+    #define USB_CDC_NO_PARITY     0
+    #define USB_CDC_ODD_PARITY    1
+    #define USB_CDC_EVEN_PARITY   2
+    #define USB_CDC_MARK_PARITY   3
+    #define USB_CDC_SPACE_PARITY  4
+    uint8_t bDataBits;
+} __attribute__ ((packed)) usb_LineCoding;
+
+typedef struct {
+    uint8_t   bmRequestType;
+    uint8_t   bNotificationType;
+    uint16_t  wValue;
+    uint16_t  wIndex;
+    uint16_t  wLength;
+} __attribute__ ((packed)) usb_cdc_notification;
+
+extern ep_t endpoints[];
+extern usb_dev_t USB_Dev;
+extern uint8_t usbON;
+
+void USB_Init();
+void USB_ResetState();
+int EP_Init(uint8_t number, uint8_t type, uint16_t txsz, uint16_t rxsz, uint16_t (*func)(ep_t ep));
+void EP_WriteIRQ(uint8_t number, const uint8_t *buf, uint16_t size);
+void EP_Write(uint8_t number, const uint8_t *buf, uint16_t size);
+int EP_Read(uint8_t number, uint16_t *buf);
+usb_LineCoding getLineCoding();
+
+void linecoding_handler(usb_LineCoding *lc);
+void clstate_handler(uint16_t val);
+void break_handler();
+
+#endif // __USB_LIB_H__

F1-nolib/PL2303/Makefile

@@ -0,0 +1,139 @@
+BINARY		= pl2303
+BOOTPORT	?= /dev/ttyUSB0
+BOOTSPEED	?= 115200
+# MCU FAMILY
+FAMILY		?= F1
+# MCU code
+MCU			?= F103x8
+# density (stm32f10x.h, lines 70-84)
+DENSITY 	?= MD
+# change this linking script depending on particular MCU model,
+LDSCRIPT	?= stm32f103x8.ld
+# debug
+DEFS		= -DEBUG
+
+INDEPENDENT_HEADERS=
+
+FP_FLAGS	?= -msoft-float -mfloat-abi=soft
+ASM_FLAGS	?= -mthumb -mcpu=cortex-m3 -mfix-cortex-m3-ldrd
+ARCH_FLAGS	= $(ASM_FLAGS) $(FP_FLAGS)
+
+###############################################################################
+# Executables
+#PREFIX		?= arm-none-eabi
+# gcc from arm web site 
+PREFIX		?= /opt/bin/arm-none-eabi
+TOOLCHLIB	?= /opt/arm-none-eabi/lib
+RM			:= rm -f
+RMDIR		:= rmdir
+CC			:= $(PREFIX)-gcc
+# don't replace ld with gcc: the binary size would be much greater!!
+LD			:= $(PREFIX)-ld
+AR			:= $(PREFIX)-ar
+AS			:= $(PREFIX)-as
+SIZE 		:= $(PREFIX)-size
+OBJCOPY		:= $(PREFIX)-objcopy
+OBJDUMP		:= $(PREFIX)-objdump
+GDB			:= $(PREFIX)-gdb
+STFLASH		:= $(shell which st-flash)
+STBOOT		:= $(shell which stm32flash)
+DFUUTIL		:= $(shell which dfu-util)
+
+###############################################################################
+# Source files
+OBJDIR 		= mk
+SRC			:= $(wildcard *.c)
+OBJS		:= $(addprefix $(OBJDIR)/, $(SRC:%.c=%.o))
+STARTUP		= $(OBJDIR)/startup.o
+OBJS 		+= $(STARTUP)
+# dependencies: we need them to recompile files if their headers-dependencies changed
+DEPS		:= $(OBJS:.o=.d)
+
+INC_DIR ?= ../inc
+
+INCLUDE 	:= -I$(INC_DIR)/Fx -I$(INC_DIR)/cm
+LIB_DIR		:= $(INC_DIR)/ld
+
+###############################################################################
+# C flags
+CFLAGS		+= -O2 -g -D__thumb2__=1 -MD
+CFLAGS		+= -Wall -Werror -Wextra -Wshadow 
+CFLAGS		+= -fno-common -ffunction-sections -fdata-sections -fno-stack-protector
+CFLAGS		+=  $(ARCH_FLAGS)
+
+###############################################################################
+# Linker flags
+LDFLAGS		+= -nostartfiles --static -nostdlibs 
+LDFLAGS		+= -L$(LIB_DIR) -L$(TOOLCHLIB)
+LDFLAGS		+= -T$(LDSCRIPT)
+
+###############################################################################
+# Used libraries
+LDLIBS		+=  -lc $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+
+DEFS		+= -DSTM32$(FAMILY) -DSTM32$(MCU) -DSTM32F10X_$(DENSITY)
+
+ELF		:= $(OBJDIR)/$(BINARY).elf
+LIST	:= $(OBJDIR)/$(BINARY).list
+BIN		:= $(BINARY).bin
+HEX		:= $(BINARY).hex
+
+all: bin list size
+
+elf: $(ELF)
+bin: $(BIN)
+hex: $(HEX)
+list: $(LIST)
+
+ifneq ($(MAKECMDGOALS),clean)
+-include $(DEPS)
+endif
+
+$(OBJDIR):
+	mkdir $(OBJDIR)
+
+$(STARTUP): $(INC_DIR)/startup/vector.c
+	$(CC) $(CFLAGS) $(DEFS) $(INCLUDE) -o $@ -c $<
+
+$(OBJDIR)/%.o: %.c
+	@echo "  CC      $<"
+	$(CC) $(CFLAGS) $(DEFS) $(INCLUDE) -o $@ -c $<
+
+$(BIN): $(ELF)
+	@echo "  OBJCOPY $(BIN)"
+	$(OBJCOPY) -Obinary $(ELF) $(BIN)
+
+$(HEX): $(ELF)
+	@echo "  OBJCOPY $(HEX)"
+	$(OBJCOPY) -Oihex $(ELF) $(HEX)
+
+$(LIST): $(ELF)
+	@echo "  OBJDUMP $(LIST)"
+	$(OBJDUMP) -S $(ELF) > $(LIST)
+
+$(ELF): $(OBJDIR) $(OBJS)
+	@echo "  LD      $(ELF)"
+	$(LD) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $(ELF)
+
+size: $(ELF)
+	$(SIZE) $(ELF)    
+
+clean:
+	@echo "  CLEAN"
+	$(RM) $(OBJS) $(DEPS) $(ELF) $(HEX) $(LIST)
+	@rmdir $(OBJDIR) 2>/dev/null || true
+
+
+flash: $(BIN)
+	@echo "  FLASH  $(BIN)"
+	$(STFLASH) write $(BIN) 0x8000000
+
+boot: $(BIN)
+	@echo "  LOAD $(BIN) through bootloader"
+	$(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN)
+
+dfuboot: $(BIN)
+	@echo "  LOAD  $(BIN) THROUGH DFU"
+	$(DFUUTIL) -a0 -D $(BIN) -s 0x08000000
+
+.PHONY: clean flash boot

F1-nolib/PL2303/Readme

@@ -0,0 +1 @@
+Empty base for PL2303 emulation

F1-nolib/PL2303/hardware.c

@@ -0,0 +1,41 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * hardware.c - hardware-dependent macros & functions
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#include "hardware.h"
+
+static inline void gpio_setup(){
+    // Enable clocks to the GPIO subsystems (PB for ADC), turn on AFIO clocking to disable SWD/JTAG
+    RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
+    // turn off SWJ/JTAG
+//    AFIO->MAPR = AFIO_MAPR_SWJ_CFG_DISABLE;
+    // turn off USB pullup
+    GPIOA->ODR = (1<<13); // turn off usb pullup & turn on pullups for buttons
+    // Set led as opendrain output
+    GPIOC->CRH |= CRH(13, CNF_ODOUTPUT|MODE_SLOW);
+    // USB pullup (PA13) - opendrain output
+    GPIOA->CRH = CRH(13, CNF_ODOUTPUT|MODE_SLOW);
+}
+
+void hw_setup(){
+    gpio_setup();
+}

F1-nolib/PL2303/hardware.h

@@ -0,0 +1,45 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * hardware.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+#pragma once
+#ifndef __HARDWARE_H__
+#define __HARDWARE_H__
+
+#include "stm32f1.h"
+
+// LED0 - PC13 (bluepill), blinking each second
+#define LED0_port   GPIOC
+#define LED0_pin    (1<<13)
+
+// USB pullup (not present in bluepill) - PA13
+#define USBPU_port  GPIOA
+#define USBPU_pin   (1<<13)
+#define USBPU_ON()  pin_clear(USBPU_port, USBPU_pin)
+#define USBPU_OFF() pin_set(USBPU_port, USBPU_pin)
+
+#define LED_blink(x)    pin_toggle(x ## _port, x ## _pin)
+#define LED_on(x)       pin_clear(x ## _port, x ## _pin)
+#define LED_off(x)      pin_set(x ## _port, x ## _pin)
+
+void hw_setup();
+
+#endif // __HARDWARE_H__

F1-nolib/PL2303/main.c

@@ -0,0 +1,151 @@
+/*
+ * main.c
+ *
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include "hardware.h"
+#include "usb.h"
+#include "usb_lib.h"
+
+volatile uint32_t Tms = 0;
+
+/* Called when systick fires */
+void sys_tick_handler(void){
+    ++Tms;
+}
+
+void iwdg_setup(){
+    uint32_t tmout = 16000000;
+    /* Enable the peripheral clock RTC */
+    /* (1) Enable the LSI (40kHz) */
+    /* (2) Wait while it is not ready */
+    RCC->CSR |= RCC_CSR_LSION; /* (1) */
+    while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
+    /* Configure IWDG */
+    /* (1) Activate IWDG (not needed if done in option bytes) */
+    /* (2) Enable write access to IWDG registers */
+    /* (3) Set prescaler by 64 (1.6ms for each tick) */
+    /* (4) Set reload value to have a rollover each 2s */
+    /* (5) Check if flags are reset */
+    /* (6) Refresh counter */
+    IWDG->KR = IWDG_START; /* (1) */
+    IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
+    IWDG->PR = IWDG_PR_PR_1; /* (3) */
+    IWDG->RLR = 1250; /* (4) */
+    tmout = 16000000;
+    while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
+    IWDG->KR = IWDG_REFRESH; /* (6) */
+}
+
+char *parse_cmd(char *buf){
+    if(buf[1] != '\n') return buf;
+    switch(*buf){
+        case 'p':
+            pin_toggle(USBPU_port, USBPU_pin);
+            USB_send("USB pullup is ");
+            if(pin_read(USBPU_port, USBPU_pin)) USB_send("off\n");
+            else USB_send("on\n");
+            return NULL;
+        break;
+        case 'L':
+            USB_send("Very long test string for USB (it's length is more than 64 bytes).\n"
+                     "This is another part of the string! Can you see all of this?\n");
+            return "OK\n";
+        break;
+        case 'R':
+            USB_send("Soft reset\n");
+            NVIC_SystemReset();
+        break;
+        case 'S':
+            USB_send("Test string for USB\n");
+            return "OK\n";
+        break;
+        case 'W':
+            USB_send("Wait for reboot\n");
+            while(1){nop();};
+        break;
+        default: // help
+            return
+            "'p' - toggle USB pullup\n"
+            "'L' - send long string over USB\n"
+            "'R' - software reset\n"
+            "'S' - send short string over USB\n"
+            "'W' - test watchdog\n"
+            ;
+        break;
+    }
+    return NULL;
+}
+
+// usb getline
+char *get_USB(){
+    static char tmpbuf[512], *curptr = tmpbuf;
+    static int rest = 511;
+    int x = USB_receive(curptr, rest);
+    curptr[x] = 0;
+    if(!x) return NULL;
+    if(curptr[x-1] == '\n'){
+        curptr = tmpbuf;
+        rest = 511;
+        return tmpbuf;
+    }
+    curptr += x; rest -= x;
+    if(rest <= 0){ // buffer overflow
+        curptr = tmpbuf;
+        rest = 511;
+    }
+    return NULL;
+}
+
+int main(void){
+    uint32_t lastT = 0;
+    sysreset();
+    StartHSE();
+    hw_setup();
+    SysTick_Config(72000);
+/*
+    if(RCC->CSR & RCC_CSR_IWDGRSTF){ // watchdog reset occured
+        SEND("WDGRESET=1\n");
+    }
+    if(RCC->CSR & RCC_CSR_SFTRSTF){ // software reset occured
+        SEND("SOFTRESET=1\n");
+    }*/
+    RCC->CSR |= RCC_CSR_RMVF; // remove reset flags
+
+    USBPU_OFF();
+    USB_setup();
+    iwdg_setup();
+    USBPU_ON();
+
+    while (1){
+        IWDG->KR = IWDG_REFRESH; // refresh watchdog
+        if(lastT > Tms || Tms - lastT > 499){
+            LED_blink(LED0);
+            lastT = Tms;
+        }
+        usb_proc();
+        char *txt, *ans;
+        if((txt = get_USB())){
+            ans = parse_cmd(txt);
+            if(ans) USB_send(ans);
+        }
+    }
+    return 0;
+}
+

F1-nolib/PL2303/usb.c

@@ -0,0 +1,165 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb.c - base functions for different USB types
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+#include "usb.h"
+#include "usb_lib.h"
+
+// incoming buffer size
+#define IDATASZ     (256)
+static uint8_t incoming_data[IDATASZ];
+static uint8_t ovfl = 0;
+static uint16_t idatalen = 0;
+static volatile uint8_t tx_succesfull = 0;
+static int8_t usbON = 0; // ==1 when USB fully configured
+
+// interrupt IN handler (never used?)
+static uint16_t EP1_Handler(ep_t ep){
+    if (ep.rx_flag){
+        ep.status = SET_VALID_TX(ep.status);
+        ep.status = KEEP_STAT_RX(ep.status);
+    }else if (ep.tx_flag){
+        ep.status = SET_VALID_RX(ep.status);
+        ep.status = SET_STALL_TX(ep.status);
+    }
+    return ep.status;
+}
+
+// data IN/OUT handler
+static uint16_t EP23_Handler(ep_t ep){
+    if(ep.rx_flag){
+        int rd = ep.rx_cnt, rest = IDATASZ - idatalen;
+        if(rd){
+            if(rd <= rest){
+                idatalen += EP_Read(2, (uint16_t*)&incoming_data[idatalen]);
+                ovfl = 0;
+            }else{
+                ep.status = SET_NAK_RX(ep.status);
+                ovfl = 1;
+                return ep.status;
+            }
+        }
+        // end of transaction: clear DTOGs
+        ep.status = CLEAR_DTOG_RX(ep.status);
+        ep.status = CLEAR_DTOG_TX(ep.status);
+        ep.status = SET_STALL_TX(ep.status);
+    }else if (ep.tx_flag){
+        ep.status = KEEP_STAT_TX(ep.status);
+        tx_succesfull = 1;
+    }
+    ep.status = SET_VALID_RX(ep.status);
+    return ep.status;
+}
+
+void USB_setup(){
+    NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
+    NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);
+    RCC->APB1ENR |= RCC_APB1ENR_USBEN;
+    USB->CNTR   = USB_CNTR_FRES; // Force USB Reset
+    for(uint32_t ctr = 0; ctr < 72000; ++ctr) nop(); // wait >1ms
+    //uint32_t ctr = 0;
+    USB->CNTR   = 0;
+    USB->BTABLE = 0;
+    USB->DADDR  = 0;
+    USB->ISTR   = 0;
+    USB->CNTR   = USB_CNTR_RESETM | USB_CNTR_WKUPM; // allow only wakeup & reset interrupts
+    NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
+    NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn );
+}
+
+void usb_proc(){
+    if(USB_GetState() == USB_CONFIGURE_STATE){ // USB configured - activate other endpoints
+        if(!usbON){ // endpoints not activated
+            // make new BULK endpoint
+            // Buffer have 1024 bytes, but last 256 we use for CAN bus (30.2 of RM: USB main features)
+            EP_Init(1, EP_TYPE_INTERRUPT, 10, 0, EP1_Handler); // IN1 - transmit
+            EP_Init(2, EP_TYPE_BULK, 0, USB_RXBUFSZ, EP23_Handler); // OUT2 - receive data
+            EP_Init(3, EP_TYPE_BULK, USB_TXBUFSZ, 0, EP23_Handler); // IN3 - transmit data
+            usbON = 1;
+        }
+    }else{
+        usbON = 0;
+    }
+}
+
+void USB_send(const char *buf){
+    if(!USB_configured()){
+        return;
+    }
+    char tmpbuf[USB_TXBUFSZ];
+    uint16_t l = 0, ctr = 0;
+    const char *p = buf;
+    while(*p++) ++l;
+    while(l){
+        uint16_t proc = 0, s  = (l > USB_TXBUFSZ - 1) ? USB_TXBUFSZ - 1: l;
+        for(int i = 0; i < s; ++i, ++proc){
+            char c = buf[ctr+proc];
+            /*
+            if(c == '\n' && the_conf.defflags & FLAG_STRENDRN){ // add '\r' before '\n'
+                tmpbuf[i++] = '\r';
+                if(i == s) ++s;
+            }*/
+            tmpbuf[i] = c;
+        }
+        tx_succesfull = 0;
+        EP_Write(3, (uint8_t*)tmpbuf, s);
+        uint32_t ctra = 1000000;
+        while(--ctra && tx_succesfull == 0);
+        l -= proc;
+        ctr += proc;
+    }
+}
+
+/**
+ * @brief USB_receive
+ * @param buf (i) - buffer for received data
+ * @param bufsize - its size
+ * @return amount of received bytes
+ */
+int USB_receive(char *buf, int bufsize){
+    if(!bufsize || !idatalen) return 0;
+    USB->CNTR = 0;
+    int sz = (idatalen > bufsize) ? bufsize : idatalen, rest = idatalen - sz;
+    for(int i = 0; i < sz; ++i) buf[i] = incoming_data[i];
+    if(rest > 0){
+        uint8_t *ptr = &incoming_data[sz];
+        for(int i = 0; i < rest; ++i) incoming_data[i] = *ptr++;
+        //memmove(incoming_data, &incoming_data[sz], rest); - hardfault on memcpy&memmove
+        idatalen = rest;
+    }else idatalen = 0;
+    if(ovfl){
+        EP23_Handler(endpoints[2]);
+        uint16_t epstatus = USB->EPnR[2];
+        epstatus = CLEAR_DTOG_RX(epstatus);
+        epstatus = SET_VALID_RX(epstatus);
+        USB->EPnR[2] = epstatus;
+    }
+    USB->CNTR = USB_CNTR_RESETM | USB_CNTR_CTRM;
+    return sz;
+}
+
+/**
+ * @brief USB_configured
+ * @return 1 if USB is in configured state
+ */
+int USB_configured(){
+    return usbON;
+}

F1-nolib/PL2303/usb.h

@@ -0,0 +1,37 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+#pragma once
+#ifndef __USB_H__
+#define __USB_H__
+
+#include "hardware.h"
+
+#define BUFFSIZE   (64)
+
+void USB_setup();
+void usb_proc();
+void USB_send(const char *buf);
+int USB_receive(char *buf, int bufsize);
+int USB_configured();
+
+#endif // __USB_H__

F1-nolib/PL2303/usb_defs.h

@@ -0,0 +1,117 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb_defs.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#pragma once
+#ifndef __USB_DEFS_H__
+#define __USB_DEFS_H__
+
+#include <stm32f1.h>
+
+// max endpoints number
+#define STM32ENDPOINTS          8
+/**
+ *                 Buffers size definition
+ **/
+#define USB_BTABLE_SIZE         512
+// first 64 bytes of USB_BTABLE are registers!
+//#define USB_EP0_BASEADDR        64
+// for USB FS EP0 buffers are from 8 to 64 bytes long (64 for PL2303)
+#define USB_EP0_BUFSZ           64
+// USB transmit buffer size (64 for PL2303)
+#define USB_TXBUFSZ             64
+// USB receive buffer size (64 for PL2303)
+#define USB_RXBUFSZ             64
+
+#define USB_BTABLE_BASE         0x40006000
+#define USB_BASE                ((uint32_t)0x40005C00)
+#define USB                     ((USB_TypeDef *) USB_BASE)
+
+#ifdef USB_BTABLE
+#undef USB_BTABLE
+#endif
+#define USB_BTABLE              ((USB_BtableDef *)(USB_BTABLE_BASE))
+#define USB_ISTR_EPID           0x0000000F
+#define USB_FNR_LSOF_0          0x00000800
+#define USB_FNR_lSOF_1          0x00001000
+#define USB_LPMCSR_BESL_0       0x00000010
+#define USB_LPMCSR_BESL_1       0x00000020
+#define USB_LPMCSR_BESL_2       0x00000040
+#define USB_LPMCSR_BESL_3       0x00000080
+#define USB_EPnR_CTR_RX         0x00008000
+#define USB_EPnR_DTOG_RX        0x00004000
+#define USB_EPnR_STAT_RX        0x00003000
+#define USB_EPnR_STAT_RX_0      0x00001000
+#define USB_EPnR_STAT_RX_1      0x00002000
+#define USB_EPnR_SETUP          0x00000800
+#define USB_EPnR_EP_TYPE        0x00000600
+#define USB_EPnR_EP_TYPE_0      0x00000200
+#define USB_EPnR_EP_TYPE_1      0x00000400
+#define USB_EPnR_EP_KIND        0x00000100
+#define USB_EPnR_CTR_TX         0x00000080
+#define USB_EPnR_DTOG_TX        0x00000040
+#define USB_EPnR_STAT_TX        0x00000030
+#define USB_EPnR_STAT_TX_0      0x00000010
+#define USB_EPnR_STAT_TX_1      0x00000020
+#define USB_EPnR_EA             0x0000000F
+#define USB_COUNTn_RX_BLSIZE    0x00008000
+#define USB_COUNTn_NUM_BLOCK    0x00007C00
+#define USB_COUNTn_RX           0x0000003F
+
+#ifdef USB_TypeDef
+#define USB_TypeDef USB_TypeDef_custom
+#endif
+
+typedef struct {
+    __IO uint32_t EPnR[STM32ENDPOINTS];
+    __IO uint32_t RESERVED[STM32ENDPOINTS];
+    __IO uint32_t CNTR;
+    __IO uint32_t ISTR;
+    __IO uint32_t FNR;
+    __IO uint32_t DADDR;
+    __IO uint32_t BTABLE;
+} USB_TypeDef;
+
+/*
+typedef struct{
+    __IO uint16_t USB_ADDR_TX;
+    __IO uint16_t res1;
+    __IO uint16_t USB_COUNT_TX;
+    __IO uint16_t res2;
+    __IO uint16_t USB_ADDR_RX;
+    __IO uint16_t res3;
+    __IO uint16_t USB_COUNT_RX;
+    __IO uint16_t res4;
+} USB_EPDATA_TypeDef;*/
+
+typedef struct{
+    __IO uint32_t USB_ADDR_TX;
+    __IO uint32_t USB_COUNT_TX;
+    __IO uint32_t USB_ADDR_RX;
+    __IO uint32_t USB_COUNT_RX;
+} USB_EPDATA_TypeDef;
+
+typedef struct{
+    __IO USB_EPDATA_TypeDef EP[STM32ENDPOINTS];
+} USB_BtableDef;
+
+#endif // __USB_DEFS_H__

F1-nolib/PL2303/usb_lib.c

@@ -0,0 +1,522 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb_lib.c
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#include <stdint.h>
+#include "usb_lib.h"
+
+ep_t endpoints[STM32ENDPOINTS];
+
+static usb_dev_t USB_Dev;
+static usb_LineCoding lineCoding = {115200, 0, 0, 8};
+config_pack_t setup_packet;
+static uint8_t ep0databuf[EP0DATABUF_SIZE];
+static uint8_t ep0dbuflen = 0;
+
+usb_LineCoding getLineCoding(){return lineCoding;}
+
+// definition of parts common for USB_DeviceDescriptor & USB_DeviceQualifierDescriptor
+#define bcdUSB_L        0x10
+#define bcdUSB_H        0x01
+#define bDeviceClass    0
+#define bDeviceSubClass 0
+#define bDeviceProtocol 0
+#define bNumConfigurations 1
+
+static const uint8_t USB_DeviceDescriptor[] = {
+        18,     // bLength
+        0x01,   // bDescriptorType - Device descriptor
+        bcdUSB_L,   // bcdUSB_L - 1.10
+        bcdUSB_H,   // bcdUSB_H
+        bDeviceClass,   // bDeviceClass - USB_COMM
+        bDeviceSubClass,   // bDeviceSubClass
+        bDeviceProtocol,   // bDeviceProtocol
+        USB_EP0_BUFSZ,   // bMaxPacketSize
+        0x7b,   // idVendor_L PL2303: VID=0x067b, PID=0x2303
+        0x06,   // idVendor_H
+        0x03,   // idProduct_L
+        0x23,   // idProduct_H
+        0x00,   // bcdDevice_Ver_L
+        0x03,   // bcdDevice_Ver_H
+        0x01,   // iManufacturer
+        0x02,   // iProduct
+        0x00,   // iSerialNumber
+        bNumConfigurations    // bNumConfigurations
+};
+
+static const uint8_t USB_DeviceQualifierDescriptor[] = {
+        10,     //bLength
+        0x06,   // bDescriptorType - Device qualifier
+        bcdUSB_L,   // bcdUSB_L
+        bcdUSB_H,   // bcdUSB_H
+        bDeviceClass,   // bDeviceClass
+        bDeviceSubClass,   // bDeviceSubClass
+        bDeviceProtocol,   // bDeviceProtocol
+        USB_EP0_BUFSZ,   // bMaxPacketSize0
+        bNumConfigurations,   // bNumConfigurations
+        0x00    // Reserved
+};
+
+static const uint8_t USB_ConfigDescriptor[] = {
+        /*Configuration Descriptor*/
+        0x09, /* bLength: Configuration Descriptor size */
+        0x02, /* bDescriptorType: Configuration */
+        39,   /* wTotalLength:no of returned bytes */
+        0x00,
+        0x01, /* bNumInterfaces: 1 interface */
+        0x01, /* bConfigurationValue: Configuration value */
+        0x00, /* iConfiguration: Index of string descriptor describing the configuration */
+        0xa0, /* bmAttributes - Bus powered, Remote wakeup */
+        0x32, /* MaxPower 100 mA */
+
+        /*---------------------------------------------------------------------------*/
+
+        /*Interface Descriptor */
+        0x09, /* bLength: Interface Descriptor size */
+        0x04, /* bDescriptorType: Interface */
+        0x00, /* bInterfaceNumber: Number of Interface */
+        0x00, /* bAlternateSetting: Alternate setting */
+        0x03, /* bNumEndpoints: 3 endpoints used */
+        0xff, /* bInterfaceClass */
+        0x00, /* bInterfaceSubClass */
+        0x00, /* bInterfaceProtocol */
+        0x00, /* iInterface: */
+///////////////////////////////////////////////////
+        /*Endpoint 1 Descriptor*/
+        0x07, /* bLength: Endpoint Descriptor size */
+        0x05, /* bDescriptorType: Endpoint */
+        0x81, /* bEndpointAddress IN1 */
+        0x03, /* bmAttributes: Interrupt */
+        0x0a, /* wMaxPacketSize LO: */
+        0x00, /* wMaxPacketSize HI: */
+        0x01, /* bInterval: */
+
+        /*Endpoint OUT2 Descriptor*/
+        0x07, /* bLength: Endpoint Descriptor size */
+        0x05, /* bDescriptorType: Endpoint */
+        0x02, /* bEndpointAddress: OUT2 */
+        0x02, /* bmAttributes: Bulk */
+        (USB_RXBUFSZ & 0xff), /* wMaxPacketSize: 64 */
+        (USB_RXBUFSZ >> 8),
+        0x00, /* bInterval: ignore for Bulk transfer */
+
+        /*Endpoint IN3 Descriptor*/
+        0x07, /* bLength: Endpoint Descriptor size */
+        0x05, /* bDescriptorType: Endpoint */
+        0x83, /* bEndpointAddress IN3 */
+        0x02, /* bmAttributes: Bulk */
+        (USB_TXBUFSZ & 0xff), /* wMaxPacketSize: 64 */
+        (USB_TXBUFSZ >> 8),
+        0x00, /* bInterval: ignore for Bulk transfer */
+};
+
+_USB_LANG_ID_(USB_StringLangDescriptor, LANG_US);
+// these descriptors are not used in PL2303 emulator!
+_USB_STRING_(USB_StringSerialDescriptor, u"0");
+_USB_STRING_(USB_StringManufacturingDescriptor, u"Prolific Technology Inc.");
+_USB_STRING_(USB_StringProdDescriptor, u"USB-Serial Controller");
+
+/*
+ * default handlers
+ */
+// SET_LINE_CODING
+void WEAK linecoding_handler(usb_LineCoding __attribute__((unused)) *lc){
+}
+
+// SET_CONTROL_LINE_STATE
+void WEAK clstate_handler(uint16_t __attribute__((unused)) val){
+}
+
+// SEND_BREAK
+void WEAK break_handler(){
+}
+
+// handler of vendor requests
+void WEAK vendor_handler(config_pack_t *packet){
+    if(packet->bmRequestType & 0x80){ // read
+        uint8_t c;
+        switch(packet->wValue){
+            case 0x8484:
+                c = 2;
+            break;
+            case 0x0080:
+                c = 1;
+            break;
+            case 0x8686:
+                c = 0xaa;
+            break;
+            default:
+                c = 0;
+        }
+        EP_WriteIRQ(0, &c, 1);
+    }else{ // write ZLP
+        EP_WriteIRQ(0, (uint8_t *)0, 0);
+    }
+}
+
+static void wr0(const uint8_t *buf, uint16_t size){
+    if(setup_packet.wLength < size) size = setup_packet.wLength;
+    EP_WriteIRQ(0, buf, size);
+}
+
+static inline void get_descriptor(){
+    switch(setup_packet.wValue){
+        case DEVICE_DESCRIPTOR:
+            wr0(USB_DeviceDescriptor, sizeof(USB_DeviceDescriptor));
+        break;
+        case CONFIGURATION_DESCRIPTOR:
+            wr0(USB_ConfigDescriptor, sizeof(USB_ConfigDescriptor));
+        break;
+        case STRING_LANG_DESCRIPTOR:
+            wr0((const uint8_t *)&USB_StringLangDescriptor, STRING_LANG_DESCRIPTOR_SIZE_BYTE);
+        break;
+        case STRING_MAN_DESCRIPTOR:
+            wr0((const uint8_t *)&USB_StringManufacturingDescriptor, USB_StringManufacturingDescriptor.bLength);
+        break;
+        case STRING_PROD_DESCRIPTOR:
+            wr0((const uint8_t *)&USB_StringProdDescriptor, USB_StringProdDescriptor.bLength);
+        break;
+        case STRING_SN_DESCRIPTOR:
+            wr0((const uint8_t *)&USB_StringSerialDescriptor, USB_StringSerialDescriptor.bLength);
+        break;
+        case DEVICE_QUALIFIER_DESCRIPTOR:
+            wr0(USB_DeviceQualifierDescriptor, USB_DeviceQualifierDescriptor[0]);
+        break;
+        default:
+        break;
+    }
+}
+
+static uint8_t configuration = 0; // reply for GET_CONFIGURATION (==1 if configured)
+static inline void std_d2h_req(){
+    uint16_t status = 0; // bus powered
+    switch(setup_packet.bRequest){
+        case GET_DESCRIPTOR:
+            get_descriptor();
+        break;
+        case GET_STATUS:
+            EP_WriteIRQ(0, (uint8_t *)&status, 2); // send status: Bus Powered
+        break;
+        case GET_CONFIGURATION:
+            EP_WriteIRQ(0, &configuration, 1);
+        break;
+        default:
+        break;
+    }
+}
+
+static inline void std_h2d_req(){
+    switch(setup_packet.bRequest){
+        case SET_ADDRESS:
+            // new address will be assigned later - after  acknowlegement or request to host
+            USB_Dev.USB_Addr = setup_packet.wValue;
+        break;
+        case SET_CONFIGURATION:
+            // Now device configured
+            USB_Dev.USB_Status = USB_CONFIGURE_STATE;
+            configuration = setup_packet.wValue;
+        break;
+        default:
+        break;
+    }
+}
+
+/*
+bmRequestType: 76543210
+7    direction: 0 - host->device, 1 - device->host
+65   type: 0 - standard, 1 - class, 2 - vendor
+4..0 getter: 0 - device, 1 - interface, 2 - endpoint, 3 - other
+*/
+/**
+ * Endpoint0 (control) handler
+ * @param ep - endpoint state
+ * @return data written to EP0R
+ */
+static uint16_t EP0_Handler(ep_t ep){
+    uint16_t epstatus = ep.status; // EP0R on input -> return this value after modifications
+    uint8_t reqtype = setup_packet.bmRequestType & 0x7f;
+    uint8_t dev2host = (setup_packet.bmRequestType & 0x80) ? 1 : 0;
+    if ((ep.rx_flag) && (ep.setup_flag)){
+        switch(reqtype){
+            case STANDARD_DEVICE_REQUEST_TYPE: // standard device request
+                if(dev2host){
+                    std_d2h_req();
+                }else{
+                    std_h2d_req();
+                    EP_WriteIRQ(0, (uint8_t *)0, 0);
+                }
+                epstatus = SET_NAK_RX(epstatus);
+                epstatus = SET_VALID_TX(epstatus);
+            break;
+            case STANDARD_ENDPOINT_REQUEST_TYPE: // standard endpoint request
+                if(setup_packet.bRequest == CLEAR_FEATURE){
+                    EP_WriteIRQ(0, (uint8_t *)0, 0);
+                    epstatus = SET_NAK_RX(epstatus);
+                    epstatus = SET_VALID_TX(epstatus);
+                }
+            break;
+            case VENDOR_REQUEST_TYPE:
+                vendor_handler(&setup_packet);
+                epstatus = SET_NAK_RX(epstatus);
+                epstatus = SET_VALID_TX(epstatus);
+            break;
+            case CONTROL_REQUEST_TYPE:
+                switch(setup_packet.bRequest){
+                    case GET_LINE_CODING:
+                        EP_WriteIRQ(0, (uint8_t*)&lineCoding, sizeof(lineCoding));
+                    break;
+                    case SET_LINE_CODING: // omit this for next stage, when data will come
+                    break;
+                    case SET_CONTROL_LINE_STATE:
+                        clstate_handler(setup_packet.wValue);
+                    break;
+                    case SEND_BREAK:
+                        break_handler();
+                    break;
+                    default:
+                    break;
+                }
+                //if(!dev2host) EP_WriteIRQ(0, (uint8_t *)0, 0); // write acknowledgement <- DO WE NEED THIS? TODO!!!
+                // OR THIS: ???
+                if(setup_packet.bRequest != GET_LINE_CODING) EP_WriteIRQ(0, (uint8_t *)0, 0); // write acknowledgement
+
+                epstatus = SET_VALID_RX(epstatus);
+                epstatus = SET_VALID_TX(epstatus);
+            break;
+            default:
+                EP_WriteIRQ(0, (uint8_t *)0, 0);
+                epstatus = SET_NAK_RX(epstatus);
+                epstatus = SET_VALID_TX(epstatus);
+        }
+    }else if (ep.rx_flag){ // got data over EP0 or host acknowlegement
+        if(ep.rx_cnt){
+            //EP_WriteIRQ(0, (uint8_t *)0, 0);
+            if(setup_packet.bRequest == SET_LINE_CODING){
+                linecoding_handler((usb_LineCoding*)ep0databuf);
+            }
+        }
+        // wait for new data from host
+        epstatus = SET_VALID_RX(epstatus);
+        epstatus = SET_VALID_TX(epstatus);
+    } else if (ep.tx_flag){ // package transmitted
+        // now we can change address after enumeration
+        if ((USB->DADDR & USB_DADDR_ADD) != USB_Dev.USB_Addr){
+            USB->DADDR = USB_DADDR_EF | USB_Dev.USB_Addr;
+            // change state to ADRESSED
+            USB_Dev.USB_Status = USB_ADRESSED_STATE;
+        }
+        // end of transaction
+        epstatus = CLEAR_DTOG_RX(epstatus);
+        epstatus = CLEAR_DTOG_TX(epstatus);
+        epstatus = SET_VALID_RX(epstatus);
+        epstatus = SET_VALID_TX(epstatus);
+    }
+    return epstatus;
+}
+
+static uint16_t lastaddr = LASTADDR_DEFAULT;
+/**
+ * Endpoint initialisation
+ * @param number - EP num (0...7)
+ * @param type - EP type (EP_TYPE_BULK, EP_TYPE_CONTROL, EP_TYPE_ISO, EP_TYPE_INTERRUPT)
+ * @param txsz - transmission buffer size @ USB/CAN buffer
+ * @param rxsz - reception buffer size @ USB/CAN buffer
+ * @param uint16_t (*func)(ep_t *ep) - EP handler function
+ * @return 0 if all OK
+ */
+int EP_Init(uint8_t number, uint8_t type, uint16_t txsz, uint16_t rxsz, uint16_t (*func)(ep_t ep)){
+    if(number >= STM32ENDPOINTS) return 4; // out of configured amount
+    if(txsz > USB_BTABLE_SIZE || rxsz > USB_BTABLE_SIZE) return 1; // buffer too large
+    if(lastaddr + txsz + rxsz >= USB_BTABLE_SIZE) return 2; // out of btable
+    USB->EPnR[number] = (type << 9) | (number & USB_EPnR_EA);
+    USB->EPnR[number] ^= USB_EPnR_STAT_RX | USB_EPnR_STAT_TX_1;
+    if(rxsz & 1 || rxsz > 512) return 3; // wrong rx buffer size
+    uint16_t countrx = 0;
+    if(rxsz < 64) countrx = rxsz / 2;
+    else{
+        if(rxsz & 0x1f) return 3; // should be multiple of 32
+        countrx = 31 + rxsz / 32;
+    }
+    USB_BTABLE->EP[number].USB_ADDR_TX = lastaddr;
+    endpoints[number].tx_buf = (uint16_t *)(USB_BTABLE_BASE + lastaddr*2);
+    lastaddr += txsz;
+    USB_BTABLE->EP[number].USB_COUNT_TX = 0;
+    USB_BTABLE->EP[number].USB_ADDR_RX = lastaddr;
+    endpoints[number].rx_buf = (uint16_t *)(USB_BTABLE_BASE + lastaddr*2);
+    lastaddr += rxsz;
+    USB_BTABLE->EP[number].USB_COUNT_RX = countrx << 10;
+    endpoints[number].func = func;
+    return 0;
+}
+
+//extern int8_t dump;
+// standard IRQ handler
+void usb_isr(){
+    if (USB->ISTR & USB_ISTR_RESET){
+        // Reinit registers
+        USB->CNTR = USB_CNTR_RESETM | USB_CNTR_CTRM;
+        USB->ISTR = 0;
+        // Endpoint 0 - CONTROL
+        // ON USB LS size of EP0 may be 8 bytes, but on FS it should be 64 bytes!
+        lastaddr = LASTADDR_DEFAULT;
+        // clear address, leave only enable bit
+        USB->DADDR = USB_DADDR_EF;
+        USB_Dev.USB_Status =USB_DEFAULT_STATE;
+        if(EP_Init(0, EP_TYPE_CONTROL, USB_EP0_BUFSZ, USB_EP0_BUFSZ, EP0_Handler)){
+            return;
+        }
+    }
+    if(USB->ISTR & USB_ISTR_CTR){
+        // EP number
+        uint8_t n = USB->ISTR & USB_ISTR_EPID;
+        // copy status register
+        uint16_t epstatus = USB->EPnR[n];
+    //  dump = 1;
+        // Calculate flags
+        endpoints[n].rx_flag = (epstatus & USB_EPnR_CTR_RX) ? 1 : 0;
+        endpoints[n].setup_flag = (epstatus & USB_EPnR_SETUP) ? 1 : 0;
+        endpoints[n].tx_flag = (epstatus & USB_EPnR_CTR_TX) ? 1 : 0;
+        // copy received bytes amount
+        endpoints[n].rx_cnt = USB_BTABLE->EP[n].USB_COUNT_RX & 0x3FF; // low 10 bits is counter
+        // check direction
+        if(USB->ISTR & USB_ISTR_DIR){ // OUT interrupt - receive data, CTR_RX==1 (if CTR_TX == 1 - two pending transactions: receive following by transmit)
+            if(n == 0){ // control endpoint
+                if(epstatus & USB_EPnR_SETUP){ // setup packet -> copy data to conf_pack
+                    EP_Read(0, (uint16_t*)&setup_packet);
+                    ep0dbuflen = 0;
+                    // interrupt handler will be called later
+                }else if(epstatus & USB_EPnR_CTR_RX){ // data packet -> push received data to ep0databuf
+                    ep0dbuflen = endpoints[0].rx_cnt;
+                    EP_Read(0, (uint16_t*)&ep0databuf);
+                }
+            }
+        }else{ // IN interrupt - transmit data, only CTR_TX == 1
+            // enumeration end could be here (if EP0)
+        }
+        // prepare status field for EP handler
+        endpoints[n].status = epstatus;
+        // call EP handler (even if it will change EPnR, it should return new status)
+        epstatus = endpoints[n].func(endpoints[n]);
+        // keep DTOG state
+        epstatus = KEEP_DTOG_TX(epstatus);
+        epstatus = KEEP_DTOG_RX(epstatus);
+        // clear all RX/TX flags
+        epstatus = CLEAR_CTR_RX(epstatus);
+        epstatus = CLEAR_CTR_TX(epstatus);
+        // refresh EPnR
+        USB->EPnR[n] = epstatus;
+    }
+}
+
+/*
+    if (USB->ISTR & USB_ISTR_PMAOVR) {
+        MSG("PMAOVR\n");
+        // Handle PMAOVR status
+    }
+    if (USB->ISTR & USB_ISTR_SUSP) {
+        MSG("SUSP\n");
+        if (USB->DADDR & 0x7f) {
+            USB->DADDR = 0;
+            USB->CNTR &= ~ 0x800;
+        }
+    }
+    if (USB->ISTR & USB_ISTR_ERR) {
+        MSG("ERR\n");
+        // Handle Error
+    }
+    if (USB->ISTR & USB_ISTR_WKUP) {
+        MSG("WKUP\n");
+        // Handle Wakeup
+    }
+    if (USB->ISTR & USB_ISTR_SOF) {
+        MSG("SOF\n");
+        // Handle SOF
+    }
+    if (USB->ISTR & USB_ISTR_ESOF) {
+        MSG("ESOF\n");
+        // Handle ESOF
+    }
+    USB->ISTR = 0;
+*/
+
+void usb_lp_can_rx0_isr(){
+    usb_isr();
+}
+
+void usb_hp_can_tx_isr(){
+    usb_isr();
+}
+
+/**
+ * Write data to EP buffer (called from IRQ handler)
+ * @param number - EP number
+ * @param *buf - array with data
+ * @param size - its size
+ */
+void EP_WriteIRQ(uint8_t number, const uint8_t *buf, uint16_t size){
+    uint8_t i;
+    if(size > USB_TXBUFSZ) size = USB_TXBUFSZ;
+    uint16_t N2 = (size + 1) >> 1;
+    // the buffer is 16-bit, so we should copy data as it would be uint16_t
+    uint16_t *buf16 = (uint16_t *)buf;
+    uint32_t *out = (uint32_t *)endpoints[number].tx_buf;
+    for(i = 0; i < N2; ++i, ++out){
+        *out = buf16[i];
+    }
+    USB_BTABLE->EP[number].USB_COUNT_TX = size;
+}
+
+/**
+ * Write data to EP buffer (called outside IRQ handler)
+ * @param number - EP number
+ * @param *buf - array with data
+ * @param size - its size
+ */
+void EP_Write(uint8_t number, const uint8_t *buf, uint16_t size){
+    uint16_t status = USB->EPnR[number];
+    EP_WriteIRQ(number, buf, size);
+    status = SET_NAK_RX(status);
+    status = SET_VALID_TX(status);
+    status = KEEP_DTOG_TX(status);
+    status = KEEP_DTOG_RX(status);
+    USB->EPnR[number] = status;
+}
+
+/*
+ * Copy data from EP buffer into user buffer area
+ * @param *buf - user array for data
+ * @return amount of data read
+ */
+int EP_Read(uint8_t number, uint16_t *buf){
+    int n = (endpoints[number].rx_cnt + 1) >> 1;
+    uint32_t *in = (uint32_t *)endpoints[number].rx_buf;
+    if(n){
+        for(int i = 0; i < n; ++i, ++in)
+            buf[i] = *(uint16_t*)in;
+    }
+    return endpoints[number].rx_cnt;
+}
+
+// USB status
+uint8_t USB_GetState(){
+    return USB_Dev.USB_Status;
+}

F1-nolib/PL2303/usb_lib.h

@@ -0,0 +1,202 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * usb_lib.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#pragma once
+#ifndef __USB_LIB_H__
+#define __USB_LIB_H__
+
+#include <wchar.h>
+#include "usb_defs.h"
+
+#define EP0DATABUF_SIZE                 (64)
+#define LASTADDR_DEFAULT                (STM32ENDPOINTS * 8)
+
+// Max EP amount (EP0 + other used)
+//#define ENDPOINTS_NUM                   4
+// bmRequestType & 0x7f
+#define STANDARD_DEVICE_REQUEST_TYPE    0
+#define STANDARD_ENDPOINT_REQUEST_TYPE  2
+#define VENDOR_REQUEST_TYPE             0x40
+#define CONTROL_REQUEST_TYPE            0x21
+// bRequest, standard; for bmRequestType == 0x80
+#define GET_STATUS                      0x00
+#define GET_DESCRIPTOR                  0x06
+#define GET_CONFIGURATION               0x08
+// for bmRequestType == 0
+#define CLEAR_FEATURE                   0x01
+#define SET_FEATURE                     0x03    // unused
+#define SET_ADDRESS                     0x05
+#define SET_DESCRIPTOR                  0x07    // unused
+#define SET_CONFIGURATION               0x09
+// for bmRequestType == 0x81, 1 or 0xB2
+#define GET_INTERFACE                   0x0A    // unused
+#define SET_INTERFACE                   0x0B    // unused
+#define SYNC_FRAME                      0x0C    // unused
+#define VENDOR_REQUEST                  0x01    // unused
+
+// Class-Specific Control Requests
+#define SEND_ENCAPSULATED_COMMAND       0x00    // unused
+#define GET_ENCAPSULATED_RESPONSE       0x01    // unused
+#define SET_COMM_FEATURE                0x02    // unused
+#define GET_COMM_FEATURE                0x03    // unused
+#define CLEAR_COMM_FEATURE              0x04    // unused
+#define SET_LINE_CODING                 0x20
+#define GET_LINE_CODING                 0x21
+#define SET_CONTROL_LINE_STATE          0x22
+#define SEND_BREAK                      0x23
+
+// control line states
+#define CONTROL_DTR                     0x01
+#define CONTROL_RTS                     0x02
+
+// wValue
+#define DEVICE_DESCRIPTOR               0x100
+#define CONFIGURATION_DESCRIPTOR        0x200
+#define STRING_LANG_DESCRIPTOR          0x300
+#define STRING_MAN_DESCRIPTOR           0x301
+#define STRING_PROD_DESCRIPTOR          0x302
+#define STRING_SN_DESCRIPTOR            0x303
+#define DEVICE_QUALIFIER_DESCRIPTOR     0x600
+
+// EPnR bits manipulation
+#define CLEAR_DTOG_RX(R)                (R & USB_EPnR_DTOG_RX) ? R : (R & (~USB_EPnR_DTOG_RX))
+#define SET_DTOG_RX(R)                  (R & USB_EPnR_DTOG_RX) ? (R & (~USB_EPnR_DTOG_RX)) : R
+#define TOGGLE_DTOG_RX(R)               (R | USB_EPnR_DTOG_RX)
+#define KEEP_DTOG_RX(R)                 (R & (~USB_EPnR_DTOG_RX))
+#define CLEAR_DTOG_TX(R)                (R & USB_EPnR_DTOG_TX) ? R : (R & (~USB_EPnR_DTOG_TX))
+#define SET_DTOG_TX(R)                  (R & USB_EPnR_DTOG_TX) ? (R & (~USB_EPnR_DTOG_TX)) : R
+#define TOGGLE_DTOG_TX(R)               (R | USB_EPnR_DTOG_TX)
+#define KEEP_DTOG_TX(R)                 (R & (~USB_EPnR_DTOG_TX))
+#define SET_VALID_RX(R)                 ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX)   | (R & (~USB_EPnR_STAT_RX))
+#define SET_NAK_RX(R)                   ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX_1) | (R & (~USB_EPnR_STAT_RX))
+#define SET_STALL_RX(R)                 ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX_0) | (R & (~USB_EPnR_STAT_RX))
+#define KEEP_STAT_RX(R)                 (R & (~USB_EPnR_STAT_RX))
+#define SET_VALID_TX(R)                 ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX)   | (R & (~USB_EPnR_STAT_TX))
+#define SET_NAK_TX(R)                   ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX_1) | (R & (~USB_EPnR_STAT_TX))
+#define SET_STALL_TX(R)                 ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX_0) | (R & (~USB_EPnR_STAT_TX))
+#define KEEP_STAT_TX(R)                 (R & (~USB_EPnR_STAT_TX))
+#define CLEAR_CTR_RX(R)                 (R & (~USB_EPnR_CTR_RX))
+#define CLEAR_CTR_TX(R)                 (R & (~USB_EPnR_CTR_TX))
+#define CLEAR_CTR_RX_TX(R)              (R & (~(USB_EPnR_CTR_TX | USB_EPnR_CTR_RX)))
+
+// USB state: uninitialized, addressed, ready for use
+#define USB_DEFAULT_STATE               0
+#define USB_ADRESSED_STATE              1
+#define USB_CONFIGURE_STATE             2
+
+// EP types
+#define EP_TYPE_BULK                    0x00
+#define EP_TYPE_CONTROL                 0x01
+#define EP_TYPE_ISO                     0x02
+#define EP_TYPE_INTERRUPT               0x03
+
+#define LANG_US (uint16_t)0x0409
+
+#define _USB_STRING_(name, str)                  \
+static const struct name \
+{                          \
+        uint8_t  bLength;                       \
+        uint8_t  bDescriptorType;               \
+        uint16_t bString[(sizeof(str) - 2) / 2]; \
+    \
+} \
+name = {sizeof(name), 0x03, str}
+
+#define _USB_LANG_ID_(name, lng_id)     \
+    \
+static const struct name \
+{         \
+        uint8_t  bLength;         \
+        uint8_t  bDescriptorType; \
+        uint16_t bString;         \
+    \
+} \
+name = {0x04, 0x03, lng_id}
+#define STRING_LANG_DESCRIPTOR_SIZE_BYTE    (4)
+
+// EP0 configuration packet
+typedef struct {
+    uint8_t bmRequestType;
+    uint8_t bRequest;
+    uint16_t wValue;
+    uint16_t wIndex;
+    uint16_t wLength;
+} config_pack_t;
+
+// endpoints state
+typedef struct __ep_t{
+    uint16_t *tx_buf;           // transmission buffer address
+    uint16_t *rx_buf;           // reception buffer address
+    uint16_t (*func)();         // endpoint action function
+    uint16_t status;            // status flags
+    unsigned rx_cnt  : 10;      // received data counter
+    unsigned tx_flag : 1;       // transmission flag
+    unsigned rx_flag : 1;       // reception flag
+    unsigned setup_flag : 1;    // this is setup packet (only for EP0)
+} ep_t;
+
+// USB status & its address
+typedef struct {
+    uint8_t  USB_Status;
+    uint16_t USB_Addr;
+}usb_dev_t;
+
+typedef struct {
+    uint32_t dwDTERate;
+    uint8_t bCharFormat;
+    #define USB_CDC_1_STOP_BITS   0
+    #define USB_CDC_1_5_STOP_BITS 1
+    #define USB_CDC_2_STOP_BITS   2
+    uint8_t bParityType;
+    #define USB_CDC_NO_PARITY     0
+    #define USB_CDC_ODD_PARITY    1
+    #define USB_CDC_EVEN_PARITY   2
+    #define USB_CDC_MARK_PARITY   3
+    #define USB_CDC_SPACE_PARITY  4
+    uint8_t bDataBits;
+} __attribute__ ((packed)) usb_LineCoding;
+
+typedef struct {
+    uint8_t   bmRequestType;
+    uint8_t   bNotificationType;
+    uint16_t  wValue;
+    uint16_t  wIndex;
+    uint16_t  wLength;
+} __attribute__ ((packed)) usb_cdc_notification;
+
+extern ep_t endpoints[];
+
+void USB_Init();
+uint8_t USB_GetState();
+int EP_Init(uint8_t number, uint8_t type, uint16_t txsz, uint16_t rxsz, uint16_t (*func)(ep_t ep));
+void EP_WriteIRQ(uint8_t number, const uint8_t *buf, uint16_t size);
+void EP_Write(uint8_t number, const uint8_t *buf, uint16_t size);
+int EP_Read(uint8_t number, uint16_t *buf);
+usb_LineCoding getLineCoding();
+
+void WEAK linecoding_handler(usb_LineCoding *lc);
+void WEAK clstate_handler(uint16_t val);
+void WEAK break_handler();
+void WEAK vendor_handler(config_pack_t *packet);
+
+#endif // __USB_LIB_H__

F1-nolib/chronometer_v1/inc/Fx/common_macros.h

@@ -0,0 +1,47 @@
+/*
+ * common_macros.h - common usable things
+ *
+ * Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+#ifndef __COMMON_MACROS_H__
+#define __COMMON_MACROS_H__
+
+#ifndef TRUE_INLINE
+#define TRUE_INLINE  __attribute__((always_inline)) static inline
+#endif
+
+#ifndef NULL
+#define NULL (0)
+#endif
+
+// some good things from CMSIS
+#define nop()   __NOP()
+
+#define pin_toggle(gpioport, gpios)  do{  \
+    register uint32_t __port = gpioport->ODR;  \
+    gpioport->BSRR = ((__port & gpios) << 16) | (~__port & gpios);}while(0)
+
+#define pin_set(gpioport, gpios)  do{gpioport->BSRR = gpios;}while(0)
+#define pin_clear(gpioport, gpios) do{gpioport->BSRR = ((gpios) << 16);}while(0)
+#define pin_read(gpioport, gpios) (gpioport->IDR & (gpios) ? 1 : 0)
+#define pin_write(gpioport, gpios)  do{gpioport->ODR = gpios;}while(0)
+
+
+
+#endif // __COMMON_MACROS_H__

F1-nolib/chronometer_v1/inc/Fx/stm32f0.h

@@ -0,0 +1,213 @@
+/*
+ * stm32f0.h
+ *
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+#ifndef __STM32F0_H__
+#define __STM32F0_H__
+
+#include "stm32f0xx.h"
+#include "common_macros.h"
+
+
+/************************* RCC *************************/
+// reset clocking registers
+TRUE_INLINE void sysreset(void){
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+#if defined (STM32F051x8) || defined (STM32F058x8)
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+    RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+    /* Reset PREDIV[3:0] bits */
+    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+    #if defined (STM32F072xB) || defined (STM32F078xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F071xB)
+    /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+    /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+#elif defined (STM32F030x4) || defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+    /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+    /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+    /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+    RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
+    /* Set default USB clock to PLLCLK, since there is no HSI48 */
+    RCC->CFGR3 |= (uint32_t)0x00000080;
+#else
+#error "No target selected"
+#endif
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+    /* Reset HSI14 bit */
+    RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+    // Enable Prefetch Buffer and set Flash Latency
+    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+    /* PCLK = HCLK */
+    RCC->CFGR |= RCC_CFGR_PPRE_DIV1;
+    /* PLL configuration = (HSI/2) * 12 = ~48 MHz */
+    RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
+    RCC->CFGR |= RCC_CFGR_PLLMUL12;
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0){}
+    /* Select PLL as system clock source */
+    RCC->CFGR &= ~RCC_CFGR_SW;
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL){}
+}
+
+TRUE_INLINE void StartHSE(){
+    // disable PLL
+    RCC->CR &= ~RCC_CR_PLLON;
+    RCC->CR |= RCC_CR_HSEON;
+    while ((RCC->CIR & RCC_CIR_HSERDYF) != 0);
+    RCC->CIR |= RCC_CIR_HSERDYC; // clear rdy flag
+    /* PLL configuration = (HSE) * 12 = ~48 MHz */
+    RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
+    RCC->CFGR |= RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL12;
+    RCC->CR |= RCC_CR_PLLON;
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL){}
+}
+
+#if !defined (STM32F030x4) && !defined (STM32F030x6) && !defined (STM32F030x8) && !defined (STM32F031x6) && !defined (STM32F038xx) && !defined (STM32F030xC)
+TRUE_INLINE void StartHSI48(){
+    // disable PLL
+    RCC->CR &= ~RCC_CR_PLLON;
+    RCC->CR2 &= RCC_CR2_HSI48ON; // turn on HSI48
+    while((RCC->CR2 & RCC_CR2_HSI48RDY) == 0);
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL));
+    // HSI48/2 * 2 = HSI48
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI48_PREDIV | RCC_CFGR_PLLMUL2);
+    RCC->CR |= RCC_CR_PLLON;
+    // select HSI48 as system clock source
+    RCC->CFGR &= ~RCC_CFGR_SW;
+    RCC->CFGR |= RCC_CFGR_SW_HSI48;
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI48){}
+}
+#endif
+
+/************************* GPIO *************************/
+
+/*******************  Bit definition for GPIO_MODER register  *****************/
+// _AI - analog inpt, _O - general output, _AF - alternate function
+#define GPIO_MODER_MODER0_AI        ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_O         ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_AF        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1_AI        ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_O         ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_AF        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2_AI        ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_O         ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_AF        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3_AI        ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_O         ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_AF        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4_AI        ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_O         ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_AF        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5_AI        ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_O         ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_AF        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6_AI        ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_O         ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_AF        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7_AI        ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_O         ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_AF        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8_AI        ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_O         ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_AF        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9_AI        ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_O         ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_AF        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10_AI       ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_O        ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_AF       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11_AI       ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_O        ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_AF       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12_AI       ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_O        ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_AF       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13_AI       ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_O        ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_AF       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14_AI       ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_O        ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_AF       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15_AI       ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_O        ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_AF       ((uint32_t)0x80000000)
+
+
+/************************* ADC *************************/
+/* inner termometer calibration values
+ *         Temp = (V30 - Vsense)/Avg_Slope + 30
+ *         Avg_Slope = (V30 - V110) / (110 - 30)
+ */
+#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
+#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
+// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
+#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
+#define VDD_CALIB ((uint16_t) (330))
+#define VDD_APPLI ((uint16_t) (300))
+
+/************************* USART *************************/
+
+#define USART_CR2_ADD_SHIFT     24
+// set address/character match value
+#define USART_CR2_ADD_VAL(x)        ((x) << USART_CR2_ADD_SHIFT)
+
+/************************* IWDG *************************/
+#define IWDG_REFRESH      (uint32_t)(0x0000AAAA)
+#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
+#define IWDG_START        (uint32_t)(0x0000CCCC)
+
+
+//#define  do{}while(0)
+
+
+
+
+#endif // __STM32F0_H__

F1-nolib/chronometer_v1/inc/Fx/stm32f0xx.h

@@ -0,0 +1,202 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx.h
+  * @author  MCD Application Team
+  * @version V2.2.0
+  * @date    05-December-2014
+  * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F0xx device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e.
+  *                code will be based on direct access to peripheral's registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx
+  * @{
+  */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+#if !defined (STM32F030x4) && !defined (STM32F030x6) && !defined (STM32F030x8) && \
+    !defined (STM32F031x6) && !defined (STM32F038xx) &&                           \
+    !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
+    !defined (STM32F051x8) && !defined (STM32F058xx) &&                           \
+    !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+    !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
+    #error "Define STM32 family, for example -DSTM32F042x6"
+#endif
+
+/**
+  * @brief CMSIS Device version number V2.2.0
+  */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                                |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                                |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                                |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+// arch-dependent defines
+#if defined(STM32F030x4)
+  #include "stm32f030x6.h"
+#elif defined(STM32F030x6)
+  #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+  #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+  #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+  #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+  #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+  #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+  #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+  #include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+  #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+  #include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+  #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+  #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+  #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+  #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+  #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+  #include "stm32f030xc.h"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

F1-nolib/chronometer_v1/inc/Fx/stm32f1.h

@@ -0,0 +1,218 @@
+/*
+ * stm32f1.h
+ *
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+#ifndef __STM32F1_H__
+#define __STM32F1_H__
+
+#include "vector.h"
+#include "stm32f10x.h"
+#include "common_macros.h"
+
+
+/************************* RCC *************************/
+// reset clocking registers
+TRUE_INLINE void sysreset(void){
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */ 
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+TRUE_INLINE void StartHSE()
+{
+  __IO uint32_t StartUpCounter = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    ++StartUpCounter;
+  } while(!(RCC->CR & RCC_CR_HSERDY) && (StartUpCounter < 10000));
+
+
+  if (RCC->CR & RCC_CR_HSERDY) // HSE started
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    StartUpCounter = 0;
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0 && ++StartUpCounter < 1000){}
+       
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    StartUpCounter = 0;
+    while((RCC->CR & RCC_CR_PLLRDY) == 0 && ++StartUpCounter < 1000){}
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    StartUpCounter = 0;
+    while(((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) && ++StartUpCounter < 1000){}
+  }
+  else // HSE fails to start-up
+  { 
+        ; // add some code here (use HSI)
+  }  
+}
+
+
+
+/************************* GPIO *************************/
+/**
+CNF1: 0 - general output or input; 1 - alternate output or pullup/down input
+CNF0: 0 - push/pull, analog or pullup/down input
+MODE: 00 - input, 01 - 10MHz, 10 - 2MHz, 11 - 50MHz
+Pullup/down: ODR = 0 - pulldown, 1 - pullup
+GPIO_BSRR and BRR also works
+IDR - input, ODR - output (or pullups management), 
+*/
+// MODE:
+#define MODE_INPUT      0
+#define MODE_NORMAL     1  // 10MHz
+#define MODE_SLOW       2  // 2MHz
+#define MODE_FAST       3  // 50MHz
+// CNF:
+#define CNF_ANALOG      (0 << 2)
+#define CNF_PPOUTPUT    (0 << 2)
+#define CNF_FLINPUT     (1 << 2)
+#define CNF_ODOUTPUT    (1 << 2)
+#define CNF_PUDINPUT    (2 << 2)
+#define CNF_AFPP        (2 << 2)
+#define CNF_AFOD        (3 << 2)
+
+#define CRL(pin, cnfmode)  ((cnfmode) << (pin*4))
+#define CRH(pin, cnfmode)  ((cnfmode) << ((pin-8)*4))
+
+
+/************************* ADC *************************/
+/* inner termometer calibration values
+ *         Temp = (V25 - Vsense)/Avg_Slope + 25
+ */
+#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
+
+/************************* IWDG *************************/
+#define IWDG_REFRESH      (uint32_t)(0x0000AAAA)
+#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
+#define IWDG_START        (uint32_t)(0x0000CCCC)
+
+
+#if 0
+/************************* ADC *************************/
+/* inner termometer calibration values
+ *         Temp = (V30 - Vsense)/Avg_Slope + 30
+ *         Avg_Slope = (V30 - V110) / (110 - 30)
+ */
+#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
+#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
+// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
+#define VDD_CALIB ((uint16_t) (330))
+#define VDD_APPLI ((uint16_t) (300))
+
+/************************* USART *************************/
+
+#define USART_CR2_ADD_SHIFT     24
+// set address/character match value
+#define USART_CR2_ADD_VAL(x)        ((x) << USART_CR2_ADD_SHIFT)
+
+
+//#define  do{}while(0)
+
+
+#endif
+
+#endif // __STM32F1_H__

F1-nolib/chronometer_v1/inc/Fx/vector.h

@@ -0,0 +1,410 @@
+/*
+ * vector.h
+ *
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+#ifndef VECTOR_H
+#define VECTOR_H 
+
+#ifndef WEAK
+#define WEAK __attribute__((weak))
+#endif
+
+void WEAK reset_handler(void);
+void WEAK nmi_handler(void);
+void WEAK hard_fault_handler(void);
+void WEAK sv_call_handler(void);
+void WEAK pend_sv_handler(void);
+void WEAK sys_tick_handler(void);
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+void WEAK mem_manage_handler(void);
+void WEAK bus_fault_handler(void);
+void WEAK usage_fault_handler(void);
+void WEAK debug_monitor_handler(void);
+#endif
+
+#if defined STM32F0
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK rtc_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_1_isr(void);
+void WEAK exti2_3_isr(void);
+void WEAK exti4_15_isr(void);
+void WEAK tsc_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_3_isr(void);
+void WEAK dma1_channel4_5_isr(void);
+void WEAK adc_comp_isr(void);
+void WEAK tim1_brk_up_trg_com_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK tim14_isr(void);
+void WEAK tim15_isr(void);
+void WEAK tim16_isr(void);
+void WEAK tim17_isr(void);
+void WEAK i2c1_isr(void);
+void WEAK i2c2_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_4_isr(void);
+void WEAK cec_can_isr(void);
+void WEAK usb_isr(void);
+
+#elif defined STM32F1 
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamper_isr(void);
+void WEAK rtc_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_isr(void);
+void WEAK dma1_channel3_isr(void);
+void WEAK dma1_channel4_isr(void);
+void WEAK dma1_channel5_isr(void);
+void WEAK dma1_channel6_isr(void);
+void WEAK dma1_channel7_isr(void);
+void WEAK adc1_2_isr(void);
+void WEAK usb_hp_can_tx_isr(void);
+void WEAK usb_lp_can_rx0_isr(void);
+void WEAK can_rx1_isr(void);
+void WEAK can_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_isr(void);
+void WEAK tim1_up_isr(void);
+void WEAK tim1_trg_com_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_wakeup_isr(void);
+void WEAK tim8_brk_isr(void);
+void WEAK tim8_up_isr(void);
+void WEAK tim8_trg_com_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK adc3_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_channel1_isr(void);
+void WEAK dma2_channel2_isr(void);
+void WEAK dma2_channel3_isr(void);
+void WEAK dma2_channel4_5_isr(void);
+void WEAK dma2_channel5_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+
+#elif defined STM32F2
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+
+#elif defined STM32F3
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_tsc_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_isr(void);
+void WEAK dma1_channel3_isr(void);
+void WEAK dma1_channel4_isr(void);
+void WEAK dma1_channel5_isr(void);
+void WEAK dma1_channel6_isr(void);
+void WEAK dma1_channel7_isr(void);
+void WEAK adc1_2_isr(void);
+void WEAK usb_hp_can1_tx_isr(void);
+void WEAK usb_lp_can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim15_isr(void);
+void WEAK tim1_up_tim16_isr(void);
+void WEAK tim1_trg_com_tim17_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_exti23_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_exti24_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_exti25_isr(void);
+void WEAK usart2_exti26_isr(void);
+void WEAK usart3_exti28_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_wkup_a_isr(void);
+void WEAK tim8_brk_isr(void);
+void WEAK tim8_up_isr(void);
+void WEAK tim8_trg_com_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK adc3_isr(void);
+void WEAK reserved_1_isr(void);
+void WEAK reserved_2_isr(void);
+void WEAK reserved_3_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_exti34_isr(void);
+void WEAK uart5_exti35_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_channel1_isr(void);
+void WEAK dma2_channel2_isr(void);
+void WEAK dma2_channel3_isr(void);
+void WEAK dma2_channel4_isr(void);
+void WEAK dma2_channel5_isr(void);
+void WEAK eth_isr(void);
+void WEAK reserved_4_isr(void);
+void WEAK reserved_5_isr(void);
+void WEAK comp123_isr(void);
+void WEAK comp456_isr(void);
+void WEAK comp7_isr(void);
+void WEAK reserved_6_isr(void);
+void WEAK reserved_7_isr(void);
+void WEAK reserved_8_isr(void);
+void WEAK reserved_9_isr(void);
+void WEAK reserved_10_isr(void);
+void WEAK reserved_11_isr(void);
+void WEAK reserved_12_isr(void);
+void WEAK usb_hp_isr(void);
+void WEAK usb_lp_isr(void);
+void WEAK usb_wkup_isr(void);
+void WEAK reserved_13_isr(void);
+void WEAK reserved_14_isr(void);
+void WEAK reserved_15_isr(void);
+void WEAK reserved_16_isr(void);
+
+#elif defined STM32F4
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+void WEAK fpu_isr(void);
+void WEAK uart7_isr(void);
+void WEAK uart8_isr(void);
+void WEAK spi4_isr(void);
+void WEAK spi5_isr(void);
+void WEAK spi6_isr(void);
+void WEAK sai1_isr(void);
+void WEAK lcd_tft_isr(void);
+void WEAK lcd_tft_err_isr(void);
+void WEAK dma2d_isr(void);
+
+#else
+    #error "Not supported platform"
+#endif
+
+#endif // VECTOR_H

F1-nolib/chronometer_v1/inc/cm/core_cm0.h

@@ -0,0 +1,713 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       // FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+// == 0 if counted to 0 since last reading
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+// 0 = reference clock, 1 = processor clock
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+// generate interrupt on 0
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+// enable counter
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+    \param [in]  div8   Does systick run directly from source (0) or from F/8 (1)
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks, uint32_t div8)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;
+  if(!div8) SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+  return (0);
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

F1-nolib/chronometer_v1/inc/cm/core_cm0plus.h

@@ -0,0 +1,822 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

F1-nolib/chronometer_v1/inc/cm/core_cmFunc.h

@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

F1-nolib/chronometer_v1/inc/cm/core_cmInstr.h

@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

F1-nolib/chronometer_v1/inc/cm/core_cmSimd.h

@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

F1-nolib/chronometer_v1/inc/cm/core_sc000.h

@@ -0,0 +1,842 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

F1-nolib/chronometer_v1/inc/ld/devices.data

@@ -0,0 +1,393 @@
+################################################################################
+#
+# Device chip tree definition file.
+#
+# Copyright (c) 2013 Frantisek Burian <Bufran@seznam.cz>
+# Copyright (C) 2013 Werner Almesberger <wpwrak>
+#
+# Line description:
+#   <pattern> <parent> (<data> ...)
+#
+#   <pattern>: is the pattern for the chip description to be searched for.
+#       The case of the pattern string is ignored.
+#       Pattern match symbols:
+#            ?  - matches exactly one character
+#            *  - matches none or more characters
+#            +  - matches single or more characters
+#
+#   <parent>: is the parent group name, where the search will continue.
+#       There are special parents names that controls traversing:
+#             "END" - Exit traversal.
+#             "+"   - Don't change the parent. Use for split long line to two.
+#
+#   <data>: space-separated list of preprocessor symbols supplied to the linker.
+#       -D option name is automatically prepended to each symbol definition
+#
+# All lines starting with # symbol are treated as Comments
+#
+# Recommended tree hierarchy:
+#
+#   <device name> <family group> <device specific params>
+#       +- <family group> <family> <family group specific params>
+#           +- <family> <architecture> <device family specific params>
+#               +- <architecture> END <architecture specific params>
+#
+# You can split the long line into two or more by using "+" in the parent field,
+# and defining same regex with appropriate parent on the next line. Example:
+#
+#    device + PARAM1=aaa PARAM2=bbbb PARAM3=ccc PARAM4=dddd PARAM5=eeee
+#    device parent PARAM6=ffff PARAM7=gggg PARAM8=hhhh
+#    parent END
+#
+# The order of the lines is important. After the regex match, its parent will
+# be used for match on the next line. If two regexp lines matches input, only
+# the first will be evaluated, except special group definition "+"
+#
+# The regex matches entire sym
+#
+# Example:
+#
+# --- devices.data file ---
+# stm32f05[01]?4* stm32f0 ROM=16K RAM=4K
+# stm32f0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000
+# stm32 END
+#
+# --- queried chip name ---
+# stm32f051c8t6
+#
+# --- output of the awk script ---
+# -DROM=16K -DRAM=4K -DROM_OFF=0x08000000 -DRAM_OFF=0x20000000
+#
+# The generated linker script file will contain sections rom and ram with 
+# appropriate initialization code, specified in linker file source linker.ld.S
+#
+
+################################################################################
+# the STM32 chips
+
+stm32f03[01]?4* stm32f0 ROM=16K RAM=4K
+stm32f03[01]?6* stm32f0 ROM=32K RAM=4K
+stm32f030?8* stm32f0 ROM=64K RAM=8K
+stm32f050?4* stm32f0 ROM=16K RAM=4K
+stm32f050?6* stm32f0 ROM=32K RAM=4K
+stm32f051?4* stm32f0 ROM=16K RAM=8K
+stm32f051?6* stm32f0 ROM=32K RAM=8K
+stm32f051?8* stm32f0 ROM=64K RAM=8K
+stm32f072?8* stm32f0 ROM=64K RAM=16K
+stm32f07[12]?B* stm32f0 ROM=128K RAM=16K
+
+stm32f10[012]?4* stm32f1 ROM=16K RAM=4K
+stm32f103?4* stm32f1 ROM=16K RAM=6K
+stm32f100?6* stm32f1 ROM=32K RAM=4K
+stm32f103?6* stm32f1 ROM=32K RAM=10K
+stm32f10[12]?6* stm32f1 ROM=32K RAM=6K
+stm32f100?8* stm32f1 ROM=64K RAM=8K
+stm32f10[12]?8* stm32f1 ROM=64K RAM=10K
+stm32f103?8* stm32f1 ROM=64K RAM=20K
+stm32f100?b* stm32f1 ROM=128K RAM=8K
+stm32f10[12]?b* stm32f1 ROM=128K RAM=16K
+stm32f103?b* stm32f1 ROM=128K RAM=20K
+stm32f10[57]?b* stm32f1 ROM=128K RAM=64K
+stm32f100?c* stm32f1 ROM=256K RAM=24K
+stm32f101?c* stm32f1 ROM=256K RAM=32K
+stm32f103?c* stm32f1 ROM=256K RAM=48K
+stm32f10[57]?c* stm32f1 ROM=256K RAM=64K
+stm32f100?d* stm32f1 ROM=384K RAM=32K
+stm32f101?d* stm32f1 ROM=384K RAM=48K
+stm32f103?d* stm32f1 ROM=384K RAM=64K
+stm32f100?e* stm32f1 ROM=512K RAM=32K
+stm32f101?e* stm32f1 ROM=512K RAM=48K
+stm32f103?e* stm32f1 ROM=512K RAM=64K
+stm32f100?f* stm32f1 ROM=768K RAM=80K
+stm32f103?f* stm32f1 ROM=768K RAM=96K
+stm32f100?g* stm32f1 ROM=1024K RAM=80K
+stm32f103?g* stm32f1 ROM=1024K RAM=96K
+
+stm32f205?b* stm32f2 ROM=128K RAM=64K
+stm32f205?c* stm32f2 ROM=256K RAM=96K
+stm32f207?c* stm32f2 ROM=256K RAM=128K
+stm32f2[01][57]?e* stm32f2 ROM=512K RAM=128K
+stm32f20[57]?f* stm32f2 ROM=768K RAM=128K
+stm32f2[01][57]?g* stm32f2 ROM=1024K RAM=128K
+
+stm32f302?b* stm32f3ccm ROM=128K RAM=24K CCM=8K
+stm32f302?c* stm32f3ccm ROM=256K RAM=32K CCM=8K
+stm32f303?b* stm32f3ccm ROM=128K RAM=40K CCM=8K
+stm32f3[01]3?c* stm32f3ccm ROM=256K RAM=48K CCM=8K
+stm32f373?8* stm32f3 ROM=64K RAM=16K
+stm32f373?b* stm32f3 ROM=128K RAM=24K
+stm32f3[78]3?8* stm32f3 ROM=256K RAM=32K
+
+stm32f401?b* stm32f4 ROM=128K RAM=64K
+stm32f401?c* stm32f4 ROM=256K RAM=64K
+stm32f401?d* stm32f4 ROM=512K RAM=96K
+stm32f401?e* stm32f4 ROM=384K RAM=96K
+stm32f4[01][57]?e* stm32f4ccm ROM=512K RAM=128K CCM=64K
+stm32f4[01][57]?g* stm32f4ccm ROM=1024K RAM=128K CCM=64K
+stm32f4[23][79]?g* stm32f4ccm ROM=1024K RAM=192K CCM=64K
+stm32f4[23][79]?i* stm32f4ccm ROM=2048K RAM=192K CCM=64K
+
+stm32l0???6* stm32l0 ROM=32K RAM=8K
+stm32l0???8* stm32l0 ROM=64K RAM=8K
+
+stm32l100?6* stm32l1 ROM=32K RAM=4K
+stm32l100?8* stm32l1 ROM=64K RAM=8K
+stm32l100?b* stm32l1 ROM=128K RAM=10K
+stm32l100?c* stm32l1 ROM=256K RAM=16K
+stm32l15[12]?6* stm32l1eep ROM=32K RAM=10K EEP=4K
+stm32l15[12]?8* stm32l1eep ROM=64K RAM=10K EEP=4K
+stm32l15[12]?b* stm32l1eep ROM=128K RAM=16K EEP=4K
+stm32l15[12]?c* stm32l1eep ROM=256K RAM=32K EEP=8K
+stm32l15[12]?d* stm32l1eep ROM=384K RAM=48K EEP=12K
+stm32l162?c* stm32l1eep ROM=256K RAM=32K EEP=8K
+stm32l162?d* stm32l1eep ROM=384K RAM=48K EEP=12K
+
+stm32ts60 stm32t ROM=32K RAM=10K
+
+stm32w108c8 stm32w ROM=64K RAM=8K
+stm32w108?b stm32w ROM=128K RAM=8K
+stm32w108cz stm32w ROM=192K RAM=12K
+stm32w108cc stm32w ROM=256K RAM=16K
+
+################################################################################
+# the SAM3 chips
+
+sam3a4* sam3a ROM=256K RAM=32K RAM1=32K
+sam3a8* sam3a ROM=512K RAM=64K RAM1=32K
+
+sam3n00* sam3n ROM=16K RAM=4K
+sam3n0* sam3n ROM=32K RAM=8K
+sam3n1* sam3n ROM=64K RAM=8K
+sam3n2* sam3n ROM=128K RAM=16K
+sam3n4* sam3n ROM=256K RAM=24K
+
+sam3s1* sam3s ROM=64K RAM=16K
+sam3s2* sam3s ROM=128K RAM=32K
+sam3s4* sam3s ROM=256K RAM=48K
+sam3s8* sam3s ROM=512K RAM=64K
+sam3sd8* sam3s ROM=512K RAM=64K
+
+sam3u1* sam3u ROM=64K RAM=8K RAM1=8K
+sam3u2* sam3u ROM=128K RAM=16K RAM1=16K
+sam3u4* sam3u ROM=265K RAM=32K RAM1=16K
+
+sam3x4c* sam3x ROM=256K RAM=32K RAM1=32K
+sam3x4e* sam3xnfc ROM=256K RAM=32K RAM1=32K
+sam3x8c* sam3x ROM=512K RAM=64K RAM1=32K
+sam3x8e* sam3xnfc ROM=512K RAM=64K RAM1=32K
+
+################################################################################
+# the lpc chips
+
+lpc1311* lpc13 ROM=8K RAM=4K
+lpc1313* lpc13 ROM=32K RAM=8K
+lpc1342* lpc13 ROM=16K RAM=4K
+lpc1343* lpc13 ROM=32K RAM=8K
+lpc1315* lpc13u ROM=32K RAM=8K
+lpc1316* lpc13u ROM=48K RAM=8K
+lpc1317* lpc13u ROM=64K RAM=8K RAM1=2K
+lpc1345* lpc13u ROM=32K RAM=8K USBRAM=2K
+lpc1346* lpc13u ROM=48K RAM=8K USBRAM=2K
+lpc1346* lpc13u ROM=64K RAM=8K USBRAM=2K RAM1=2K
+
+lpc1751* lpc175x ROM=32K RAM=8K
+lpc1752* lpc175x ROM=64K RAM=16K
+lpc1754* lpc175x ROM=128K RAM=16K RAM1=16K
+lpc1756* lpc175x ROM=256K RAM=16K RAM1=16K
+lpc1758* lpc175x ROM=512K RAM=32K RAM1=16K RAM2=16K
+lpc1759* lpc175x ROM=512K RAM=32K RAM1=16K RAM2=16K
+lpc1763* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K
+lpc1764* lpc176x ROM=128K RAM=16K RAM1=16K
+lpc1765* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K
+lpc1766* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K
+lpc1767* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K
+lpc1768* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K
+lpc1769* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K
+lpc1774* lpc177x ROM=128K RAM=32K RAM1=8K
+lpc1776* lpc177x ROM=256K RAM=64K RAM1=16K
+lpc1777* lpc177x ROM=512K RAM=64K RAM1=16K RAM2=16K
+lpc1778* lpc177x ROM=512K RAM=64K RAM1=16K RAM2=16K
+lpc1785* lpc178x ROM=256K RAM=64K RAM1=16K
+lpc1786* lpc178x ROM=256K RAM=64K RAM1=16K
+lpc1787* lpc178x ROM=512K RAM=64K RAM1=16K RAM2=16K
+lpc1788* lpc178x ROM=512K RAM=64K RAM1=16K RAM2=16K
+
+################################################################################
+# the efm32 chips
+
+# Zero Gecko
+efm32zg???f4 efm32zg ROM=4K RAM=2K
+efm32zg???f8 efm32zg ROM=8K RAM=2K
+efm32zg???f16 efm32zg ROM=16K RAM=4K
+efm32zg???f32 efm32zg ROM=32K RAM=4K
+
+# Tiny Gecko
+efm32tg108f4 efm32tg ROM=4K RAM=1K
+efm32tg110f4 efm32tg ROM=4K RAM=2K
+efm32tg???f8 efm32tg ROM=8K RAM=2K
+efm32tg???f16 efm32tg ROM=16K RAM=4K
+efm32tg???f32 efm32tg ROM=32K RAM=4K
+
+# Gecko
+efm32g200f16 efm32g ROM=16K RAM=8K
+efm32g???f32 efm32g ROM=32K RAM=8K
+efm32g???f64 efm32g ROM=64K RAM=16K
+efm32g???f128 efm32g ROM=128K RAM=16K
+
+# Large Gecko
+efm32lg???f64 efm32lg ROM=64K RAM=32K
+efm32lg???f128 efm32lg ROM=128K RAM=32K
+efm32lg???f256 efm32lg ROM=256K RAM=32K
+
+# Giant Gecko
+efm32gg???f512 efm32gg ROM=512K RAM=128K
+efm32gg???f1024 efm32gg ROM=1024K RAM=128K
+
+# Wonder Gecko
+efm32wg???f64 efm32gg ROM=64K RAM=32K
+efm32wg???f128 efm32gg ROM=128K RAM=32K
+efm32wg???f256 efm32gg ROM=256K RAM=32K
+
+################################################################################
+# the TI cortex M3 chips
+
+lm3s101 lm3sandstorm ROM=8K RAM=2K
+lm3s102 lm3sandstorm ROM=8K RAM=2K
+
+lm3s300 lm3sandstorm ROM=16K RAM=4K
+lm3s301 lm3sandstorm ROM=16K RAM=2K
+lm3s308 lm3sandstorm ROM=16K RAM=4K
+lm3s310 lm3sandstorm ROM=16K RAM=4K
+lm3s315 lm3sandstorm ROM=16K RAM=4K
+lm3s316 lm3sandstorm ROM=16K RAM=4K
+lm3s317 lm3sandstorm ROM=16K RAM=4K
+lm3s328 lm3sandstorm ROM=16K RAM=4K
+lm3s600 lm3sandstorm ROM=32K RAM=8K
+lm3s601 lm3sandstorm ROM=32K RAM=8K
+lm3s608 lm3sandstorm ROM=32K RAM=8K
+lm3s610 lm3sandstorm ROM=32K RAM=8K
+lm3s611 lm3sandstorm ROM=32K RAM=8K
+lm3s612 lm3sandstorm ROM=32K RAM=8K
+lm3s613 lm3sandstorm ROM=32K RAM=8K
+lm3s615 lm3sandstorm ROM=32K RAM=8K
+lm3s617 lm3sandstorm ROM=32K RAM=8K
+lm3s618 lm3sandstorm ROM=32K RAM=8K
+lm3s628 lm3sandstorm ROM=32K RAM=8K
+lm3s800 lm3sandstorm ROM=64K RAM=8K
+lm3s801 lm3sandstorm ROM=64K RAM=8K
+lm3s808 lm3sandstorm ROM=64K RAM=8K
+lm3s811 lm3sandstorm ROM=64K RAM=8K
+lm3s812 lm3sandstorm ROM=64K RAM=8K
+lm3s815 lm3sandstorm ROM=64K RAM=8K
+lm3s817 lm3sandstorm ROM=64K RAM=8K
+lm3s818 lm3sandstorm ROM=64K RAM=8K
+lm3s828 lm3sandstorm ROM=64K RAM=8K
+
+lm3s1110 lm3fury ROM=64K RAM=16K
+lm3s1133 lm3fury ROM=64K RAM=16K
+lm3s1138 lm3fury ROM=64K RAM=16K
+lm3s1150 lm3fury ROM=64K RAM=16K
+lm3s1162 lm3fury ROM=64K RAM=16K
+lm3s1165 lm3fury ROM=64K RAM=16K
+lm3s1332 lm3fury ROM=96K RAM=16K
+lm3s1435 lm3fury ROM=96K RAM=32K
+lm3s1439 lm3fury ROM=96K RAM=32K
+lm3s1512 lm3fury ROM=96K RAM=64K
+lm3s1538 lm3fury ROM=96K RAM=64K
+lm3s1601 lm3fury ROM=128K RAM=32K
+lm3s1607 lm3fury ROM=128K RAM=32K
+lm3s1608 lm3fury ROM=128K RAM=32K
+lm3s1620 lm3fury ROM=128K RAM=32K
+lm3s8962 lm3fury ROM=256K RAM=64K
+
+################################################################################
+# the TI cortex R4F chips
+
+rm46l852* rm46l ROM=1280K RAM=192K
+
+################################################################################
+################################################################################
+################################################################################
+# the STM32 family groups
+
+stm32f3ccm stm32f3 CCM_OFF=0x10000000
+stm32f4ccm stm32f4 CCM_OFF=0x10000000
+stm32l1eep stm32l1 EEP_OFF=0x08080000
+
+################################################################################
+# the SAM3 family groups
+sam3xnfc sam3x NFCRAM=4K NFCRAM_OFF=0x20100000
+
+################################################################################
+# the lpc family groups
+
+
+lpc13u lpc13 USBRAM_OFF=0x20004000
+
+lpc17[56]x lpc17 RAM1_OFF=0x2007C000 RAM2_OFF=0x20080000
+lpc17[78]x lpc17 RAM1_OFF=0x20000000 RAM2_OFF=0x20040000
+
+################################################################################
+################################################################################
+################################################################################
+# the STM32 families
+
+stm32f0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m0 -mthumb -DSTM32F0 -lopencm3_stm32f0 -msoft-float
+stm32f1 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DSTM32F1 -lopencm3_stm32f1 -msoft-float
+stm32f2 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DSTM32F2 -lopencm3_stm32f2 -msoft-float
+stm32f3 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m4 -mthumb -DSTM32F3 -lopencm3_stm32f3 -mfloat-abi=hard -mfpu=fpv4-sp-d16
+stm32f4 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m4 -mthumb -DSTM32F4 -lopencm3_stm32f4 -mfloat-abi=hard -mfpu=fpv4-sp-d16
+stm32l0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m0 -mthumb -DSTM32L0 -lopencm3_stm32l0 -msoft-float
+stm32l1 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DSTM32L1 -lopencm3_stm32l1 -msoft-float
+stm32w stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb
+stm32t stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb
+
+################################################################################
+# the SAM3 families
+
+sam3a sam3 ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000
+sam3n sam3 ROM_OFF=0x00400000 RAM_OFF=0x20000000
+sam3s sam3 ROM_OFF=0x00400000 RAM_OFF=0x20000000
+sam3u sam3 ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000 NFCRAM=4K NFCRAM_OFF=0x20100000
+sam3x sam3 ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000
+
+################################################################################
+# the lpc families
+
+lpc13 lpc ROM_OFF=0x00000000 RAM_OFF=0x10000000 RAM1_OFF=0x20000000
+lpc17 lpc ROM_OFF=0x00000000 RAM_OFF=0x10000000
+
+################################################################################
+# the efm32 Gecko families
+
+efm32zg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
+efm32tg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
+efm32g efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
+efm32lg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
+efm32gg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
+efm32wg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
+
+################################################################################
+# Cortex LM3 families
+
+lm3fury lm3 ROM_OFF=0x00000000 RAM_OFF=0x20000000
+lm3sandstorm lm3 ROM_OFF=0x00000000 RAM_OFF=0x20000000
+
+
+################################################################################
+# Cortex R4F families
+
+rm46l rm4 ROM_OFF=0x00000000 RAM_OFF=0x08000000 RAM1_OFF=0x08400000
+
+################################################################################
+################################################################################
+################################################################################
+# the architectures
+
+stm32 END
+sam3 END
+lpc END
+efm32 END
+lm3 END
+rm4 END
+

F1-nolib/chronometer_v1/inc/ld/stm32f01234.ld

@@ -0,0 +1,93 @@
+/*
+********************************************************************************
+*                                                                              *
+* Copyright (c) 2017 Andrea Loi                                                *
+*                                                                              *
+* Permission is hereby granted, free of charge, to any person obtaining a      *
+* copy of this software and associated documentation files (the "Software"),   *
+* to deal in the Software without restriction, including without limitation    *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,     *
+* and/or sell copies of the Software, and to permit persons to whom the        *
+* Software is furnished to do so, subject to the following conditions:         *
+*                                                                              *
+* The above copyright notice and this permission notice shall be included      *
+* in all copies or substantial portions of the Software.                       *
+*                                                                              *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR   *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,     *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL      *
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER   *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING      *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER          *
+* DEALINGS IN THE SOFTWARE.                                                    *
+*                                                                              *
+********************************************************************************
+*/
+
+
+
+/******************************************************************************/
+/*          DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING!           */
+/******************************************************************************/
+
+/* _isrvectors_tend =    0x00000150; - different for different series */
+
+ENTRY(reset_handler)
+
+SECTIONS {
+  .vector_table 0x08000000 :
+  {
+    _sisrvectors = .;
+    KEEP(*(.vector_table))
+    /* ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!"); */
+    _eisrvectors = .;
+  } >rom
+
+  .text :
+  {
+    . = ALIGN(4);
+    _stext = .;
+    *(.text*)
+    *(.rodata*)
+    . = ALIGN(4);
+    _etext = .;
+  } >rom
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >rom
+  
+  .ARM : {
+    *(.ARM.exidx*)
+  } >rom
+  
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;
+    *(.data*)
+    . = ALIGN(4);
+    _edata = .;
+  } >ram AT >rom
+
+  .myvars :
+  {
+    . = ALIGN(1024);
+    KEEP(*(.myvars))
+  } > rom
+
+  _ldata = LOADADDR(.data);
+
+  .bss :
+  {
+    . = ALIGN(4);
+    _sbss = .;
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    _ebss = .;
+  } >ram
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));

F1-nolib/chronometer_v1/inc/ld/stm32f030f.ld

@@ -0,0 +1,12 @@
+/* Linker script for STM32F030f4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+    rom   (rx) : ORIGIN = 0x08000000, LENGTH = 16K
+    ram  (rwx) : ORIGIN = 0x20000000, LENGTH = 4K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103x4.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 16K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103x6.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH =  32K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 10K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103x8.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH =  64K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103xB.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103xC.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103xD.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 384K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103xE.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103xF.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 768K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/inc/ld/stm32f103xG.ld

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH =  96K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

F1-nolib/chronometer_v1/kicad/Chrono.lib

@@ -0,0 +1,31 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# L80-R
+#
+DEF L80-R U 0 40 Y Y 1 F N
+F0 "U" 0 -375 50 H V C CNN
+F1 "L80-R" 0 425 50 H V C CNN
+F2 "chrono:L80-R" 0 0 50 H I C CNN
+F3 "" -550 -50 50 H I C CNN
+$FPLIST
+ L80-R
+$ENDFPLIST
+DRAW
+S -250 350 250 -325 0 1 0 N
+X RXD 1 -450 250 200 R 50 50 1 1 P
+X RESET 10 450 50 200 L 50 50 1 1 P
+X Res 11 450 150 200 L 50 50 1 1 P
+X Gnd 12 450 250 200 L 50 50 1 1 P
+X TXD 2 -450 150 200 R 50 50 1 1 P
+X Gnd 3 -450 50 200 R 50 50 1 1 P
+X Vcc 4 -450 -50 200 R 50 50 1 1 P
+X V_BKP 5 -450 -150 200 R 50 50 1 1 P
+X PPS 6 -450 -250 200 R 50 50 1 1 P
+X Res 7 450 -250 200 L 50 50 1 1 P
+X Res 8 450 -150 200 L 50 50 1 1 P
+X NC 9 450 -50 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library

F1-nolib/chronometer_v1/kicad/chrono.pretty/L80-R.kicad_mod

@@ -0,0 +1,54 @@
+(module L80-R (layer F.Cu) (tedit 5D162F3C)
+  (fp_text reference U3 (at 0 4) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text value L80-R (at 0 -15) (layer F.Fab)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start -8 -14) (end -8 3) (layer F.SilkS) (width 0.15))
+  (fp_line (start -8 3) (end 8 3) (layer F.SilkS) (width 0.15))
+  (fp_line (start 8 3) (end 8 -14) (layer F.SilkS) (width 0.15))
+  (fp_line (start 8 -14) (end -8 -14) (layer F.SilkS) (width 0.15))
+  (fp_text user 1 (at 10 3) (layer F.SilkS)
+    (effects (font (size 2.5 2.5) (thickness 0.15)))
+  )
+  (fp_line (start -4 3) (end -4 1) (layer F.SilkS) (width 0.15))
+  (fp_line (start -4 1) (end -8 1) (layer F.SilkS) (width 0.15))
+  (fp_line (start 8 2) (end 7 3) (layer F.SilkS) (width 0.15))
+  (fp_text user Keepout (at 0 -8) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text user area (at 0 -3.5) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_line (start -18 -24) (end -18 13) (layer F.SilkS) (width 0.15))
+  (fp_line (start -18 13) (end 18 13) (layer F.SilkS) (width 0.15))
+  (fp_line (start 18 13) (end 18 -24) (layer F.SilkS) (width 0.15))
+  (fp_line (start 18 -24) (end -18 -24) (layer F.SilkS) (width 0.15))
+  (fp_text user "Clear area" (at 0 -22) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (fp_text user "Clear area" (at 0 -22) (layer B.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+  )
+  (fp_line (start -18 -24) (end -18 13) (layer B.SilkS) (width 0.15))
+  (fp_line (start -18 13) (end 18 13) (layer B.SilkS) (width 0.15))
+  (fp_line (start 18 13) (end 18 -24) (layer B.SilkS) (width 0.15))
+  (fp_line (start 18 -24) (end -18 -24) (layer B.SilkS) (width 0.15))
+  (pad 1 smd rect (at 8 0) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 2 smd rect (at 8 -2.54) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 3 smd rect (at 8 -5.08) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 4 smd rect (at 8 -7.62) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 5 smd rect (at 8 -10.16) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 6 smd rect (at 8 -12.7) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 12 smd rect (at -8 0) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 11 smd rect (at -8 -2.54) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 10 smd rect (at -8 -5.08) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 9 smd rect (at -8 -7.62) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 8 smd rect (at -8 -10.16) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad 7 smd rect (at -8 -12.7) (size 4 2) (layers F.Cu F.Paste F.Mask))
+  (pad ~ smd circle (at 0 -5.5) (size 0.1 0.1) (layers B.Cu)
+    (solder_mask_margin 1.5) (solder_paste_margin 1.5) (clearance 1.3) (zone_connect 0))
+  (pad ~ smd circle (at 0 -5.5) (size 0.1 0.1) (layers F.Cu)
+    (solder_mask_margin 1.5) (solder_paste_margin 1.5) (clearance 1.3) (zone_connect 0))
+)

F1-nolib/chronometer_v1/kicad/chrono.pro

@@ -0,0 +1,78 @@
+update=Вт 22 окт 2019 19:09:03
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=chrono.net
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.2
+TrackWidth2=0.2
+TrackWidth3=0.3
+TrackWidth4=0.5
+TrackWidth5=1
+ViaDiameter1=0.8
+ViaDrill1=0.5
+ViaDiameter2=0.8
+ViaDrill2=0.5
+ViaDiameter3=1.2
+ViaDrill3=0.6
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0.051
+SolderMaskMinWidth=0.25
+SolderPasteClearance=0
+SolderPasteRatio=-0

F1-nolib/chronometer_v1/kicad/fp-lib-table

@@ -0,0 +1,7 @@
+(fp_lib_table
+  (lib (name chrono)(type KiCad)(uri ${KIPRJMOD}/chrono.pretty)(options "")(descr ""))
+  (lib (name TerminalBlock_Phoenix)(type KiCad)(uri ${KISYSMOD}/TerminalBlock_Phoenix.pretty)(options "")(descr ""))
+  (lib (name Inductor_SMD)(type KiCad)(uri ${KISYSMOD}/Inductor_SMD.pretty)(options "")(descr ""))
+  (lib (name LED_THT)(type KiCad)(uri ${KISYSMOD}/LED_THT.pretty)(options "")(descr ""))
+  (lib (name Crystal)(type KiCad)(uri ${KISYSMOD}/Crystal.pretty)(options "")(descr ""))
+)

F1-nolib/chronometer_v1/kicad/stm32-rescue.lib

@@ -0,0 +1,694 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# +3.3V
+#
+DEF +3.3V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+3.3V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# +5V
+#
+DEF +5V #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "+5V" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +5V 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# 74HC4051
+#
+DEF 74HC4051 U 0 10 Y Y 1 F N
+F0 "U" 0 0 50 H V C CNN
+F1 "74HC4051" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+$FPLIST
+ SO16
+ TSSOP16
+ SSOP16
+ DHVQFN16
+$ENDFPLIST
+DRAW
+S -400 450 400 -450 0 1 0 N
+X Y4 1 700 -50 300 L 50 50 1 1 B
+X S1 10 -700 250 300 R 50 50 1 1 I
+X S0 11 -700 350 300 R 50 50 1 1 I
+X Y3 12 700 50 300 L 50 50 1 1 B
+X Y0 13 700 350 300 L 50 50 1 1 B
+X Y1 14 700 250 300 L 50 50 1 1 B
+X Y2 15 700 150 300 L 50 50 1 1 B
+X VCC 16 -700 -100 300 R 50 50 1 1 W
+X Y6 2 700 -250 300 L 50 50 1 1 B
+X Z 3 0 -750 300 U 50 50 1 1 B
+X Y7 4 700 -350 300 L 50 50 1 1 B
+X Y5 5 700 -150 300 L 50 50 1 1 B
+X ~E 6 -700 -350 300 R 50 50 1 1 I I
+X VEE 7 -700 0 300 R 50 50 1 1 W
+X GND 8 -700 -200 300 R 50 50 1 1 W
+X S2 9 -700 150 300 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "C" 25 -100 50 H V L CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_01X01
+#
+DEF CONN_01X01 J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "CONN_01X01" 100 0 50 V V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Pin_Header_Straight_1X*
+ Pin_Header_Angled_1X*
+ Socket_Strip_Straight_1X*
+ Socket_Strip_Angled_1X*
+$ENDFPLIST
+DRAW
+S -50 5 10 -5 0 1 0 N
+S -50 50 50 -50 0 1 0 N
+X P1 1 -200 0 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_01X03
+#
+DEF CONN_01X03 J 0 40 Y N 1 F N
+F0 "J" 0 200 50 H V C CNN
+F1 "CONN_01X03" 100 0 50 V V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Pin_Header_Straight_1X*
+ Pin_Header_Angled_1X*
+ Socket_Strip_Straight_1X*
+ Socket_Strip_Angled_1X*
+$ENDFPLIST
+DRAW
+S -50 -95 10 -105 0 1 0 N
+S -50 5 10 -5 0 1 0 N
+S -50 105 10 95 0 1 0 N
+S -50 150 50 -150 0 1 0 N
+X P1 1 -200 100 150 R 50 50 1 1 P
+X P2 2 -200 0 150 R 50 50 1 1 P
+X P3 3 -200 -100 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_01X04
+#
+DEF CONN_01X04 J 0 40 Y N 1 F N
+F0 "J" 0 250 50 H V C CNN
+F1 "CONN_01X04" 100 0 50 V V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Pin_Header_Straight_1X*
+ Pin_Header_Angled_1X*
+ Socket_Strip_Straight_1X*
+ Socket_Strip_Angled_1X*
+$ENDFPLIST
+DRAW
+S -50 -145 10 -155 0 1 0 N
+S -50 -45 10 -55 0 1 0 N
+S -50 55 10 45 0 1 0 N
+S -50 155 10 145 0 1 0 N
+S -50 200 50 -200 0 1 0 N
+X P1 1 -200 150 150 R 50 50 1 1 P
+X P2 2 -200 50 150 R 50 50 1 1 P
+X P3 3 -200 -50 150 R 50 50 1 1 P
+X P4 4 -200 -150 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_01X08
+#
+DEF CONN_01X08 J 0 40 Y N 1 F N
+F0 "J" 0 450 50 H V C CNN
+F1 "CONN_01X08" 100 0 50 V V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Pin_Header_Straight_1X*
+ Pin_Header_Angled_1X*
+ Socket_Strip_Straight_1X*
+ Socket_Strip_Angled_1X*
+$ENDFPLIST
+DRAW
+S -50 -400 50 400 0 1 0 N
+S -50 -345 10 -355 0 1 0 N
+S -50 -245 10 -255 0 1 0 N
+S -50 -145 10 -155 0 1 0 N
+S -50 -45 10 -55 0 1 0 N
+S -50 55 10 45 0 1 0 N
+S -50 155 10 145 0 1 0 N
+S -50 255 10 245 0 1 0 N
+S -50 355 10 345 0 1 0 N
+X P1 1 -200 350 150 R 50 50 1 1 P
+X P2 2 -200 250 150 R 50 50 1 1 P
+X P3 3 -200 150 150 R 50 50 1 1 P
+X P4 4 -200 50 150 R 50 50 1 1 P
+X P5 5 -200 -50 150 R 50 50 1 1 P
+X P6 6 -200 -150 150 R 50 50 1 1 P
+X P7 7 -200 -250 150 R 50 50 1 1 P
+X P8 8 -200 -350 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CP
+#
+DEF CP C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "CP" 25 -100 50 H V L CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+S -90 20 -90 40 0 1 0 N
+S -90 20 90 20 0 1 0 N
+S 90 -20 -90 -40 0 1 0 F
+S 90 40 -90 40 0 1 0 N
+S 90 40 90 20 0 1 0 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 110 -50 70 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# D
+#
+DEF D D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "D" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+P 2 0 1 8 -50 50 -50 -50 N
+P 2 0 1 0 50 0 -50 0 N
+P 4 0 1 8 50 50 50 -50 -50 0 50 50 N
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# D_Schottky
+#
+DEF D_Schottky D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "D_Schottky" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+P 2 0 1 0 50 0 -50 0 N
+P 4 0 1 8 50 50 50 -50 -50 0 50 50 N
+P 6 0 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# D_Zener
+#
+DEF D_Zener D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "D_Zener" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+P 2 0 1 0 50 0 -50 0 N
+P 3 0 1 8 -50 -50 -50 50 -30 50 N
+P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# Jumper_NO_Small
+#
+DEF Jumper_NO_Small JP 0 30 N N 1 F N
+F0 "JP" 0 80 50 H V C CNN
+F1 "Jumper_NO_Small" 10 -60 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C -40 0 20 0 1 0 N
+C 40 0 20 0 1 0 N
+X 1 1 -100 0 40 R 50 50 0 1 P
+X 2 2 100 0 40 L 50 50 0 1 P
+ENDDRAW
+ENDDEF
+#
+# L
+#
+DEF L L 0 40 N N 1 F N
+F0 "L" -50 0 50 V V C CNN
+F1 "L" 75 0 50 V V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Choke_*
+ *Coil*
+ Inductor_*
+ L_*
+$ENDFPLIST
+DRAW
+A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50
+A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0
+A 0 25 25 -899 899 0 1 0 N 0 0 0 50
+A 0 75 25 -899 899 0 1 0 N 0 50 0 100
+X 1 1 0 150 50 D 50 50 1 1 P
+X 2 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# LED-RESCUE-stm32
+#
+DEF LED-RESCUE-stm32 D 0 40 Y N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "LED-RESCUE-stm32" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+$FPLIST
+ LED*
+$ENDFPLIST
+DRAW
+P 2 0 1 8 -50 -50 -50 50 N
+P 2 0 1 0 -50 0 50 0 N
+P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
+P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
+P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# LM1117-3.3-RESCUE-stm32
+#
+DEF LM1117-3.3-RESCUE-stm32 U 0 30 Y Y 1 F N
+F0 "U" 100 -250 50 H V C CNN
+F1 "LM1117-3.3-RESCUE-stm32" 0 250 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ SOT-223*
+ TO-263*
+ TO-252*
+$ENDFPLIST
+DRAW
+S -200 -200 200 200 0 1 10 f
+X GND/ADJ 1 0 -300 100 U 50 50 1 1 W
+X VO 2 300 50 100 L 50 50 1 1 P
+X VI 3 -300 0 100 R 50 50 1 1 W
+X VO 4 300 -50 100 L 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# LM2576HV
+#
+DEF LM2576HV U 0 40 Y Y 1 F N
+F0 "U" -350 250 60 H V C CNN
+F1 "LM2576HV" 250 250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+F4 "Texas Instruments" 0 350 60 H I C CNN "Manufacturer"
+$FPLIST
+ *DIP8
+ SOIC8
+$ENDFPLIST
+DRAW
+S -400 200 400 -250 0 1 0 N
+X VIN 1 -700 100 300 R 50 50 1 1 W
+X VOUT 2 700 -100 300 L 50 50 1 1 w
+X GND 3 100 -550 300 U 50 50 1 1 W
+X FB 4 700 100 300 L 50 50 1 1 I
+X ON/OFF 5 -100 -550 300 U 50 50 1 1 I I
+ENDDRAW
+ENDDEF
+#
+# MAX471-RESCUE-stm32
+#
+DEF MAX471-RESCUE-stm32 U 0 40 Y Y 1 F N
+F0 "U" -300 350 50 H V L CNN
+F1 "MAX471-RESCUE-stm32" -300 -350 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S -300 300 300 -300 0 1 10 f
+X SHDN 1 -400 -100 100 R 50 50 1 1 I
+X RS+ 2 -400 200 100 R 50 50 1 1 W
+X RS+ 3 -400 100 100 R 50 50 1 1 P
+X GND 4 -400 -200 100 R 50 50 1 1 W
+X SIGN 5 400 -100 100 L 50 50 1 1 C
+X RS- 6 400 200 100 L 50 50 1 1 w
+X RS- 7 400 100 100 L 50 50 1 1 P
+X OUT 8 400 -200 100 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# MCP2551-I_SN
+#
+DEF MCP2551-I_SN U 0 40 Y Y 1 F N
+F0 "U" -400 350 50 H V L CNN
+F1 "MCP2551-I_SN" 100 350 50 H V L CNN
+F2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" 0 -500 50 H I C CIN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ SOIC*Pitch1.27mm*
+$ENDFPLIST
+DRAW
+S -400 300 400 -300 0 1 10 f
+X TXD 1 -500 200 100 R 50 50 1 1 I
+X VSS 2 0 -400 100 U 50 50 1 1 W
+X VDD 3 0 400 100 D 50 50 1 1 W
+X RXD 4 -500 100 100 R 50 50 1 1 O
+X Vref 5 -500 -100 100 R 50 50 1 1 w
+X CANL 6 500 -100 100 L 50 50 1 1 B
+X CANH 7 500 100 100 L 50 50 1 1 B
+X Rs 8 -500 -200 100 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PESD1CAN
+#
+DEF PESD1CAN D 0 30 Y N 1 F N
+F0 "D" 0 -350 50 H V C CNN
+F1 "PESD1CAN" 50 150 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+$FPLIST
+ SOT23
+$ENDFPLIST
+DRAW
+S -200 100 300 -300 0 1 0 N
+P 2 0 1 0 -140 -200 150 -200 N
+P 2 0 1 0 -140 0 150 0 N
+P 3 0 1 8 -150 -150 -150 -250 -150 -250 N
+P 3 0 1 8 -150 50 -150 -50 -150 -50 N
+P 3 0 1 8 150 -150 150 -250 150 -250 N
+P 3 0 1 8 150 50 150 -50 150 -50 N
+P 4 0 1 8 -150 -150 -170 -150 -170 -160 -170 -160 N
+P 4 0 1 8 -150 50 -170 50 -170 40 -170 40 N
+P 4 0 1 8 150 -250 170 -250 170 -240 170 -240 N
+P 4 0 1 8 150 -150 130 -150 130 -160 130 -160 N
+P 4 0 1 8 150 -50 170 -50 170 -40 170 -40 N
+P 4 0 1 0 150 0 250 0 250 -200 150 -200 N
+P 4 0 1 8 150 50 130 50 130 40 130 40 N
+P 5 0 1 8 -130 -240 -130 -250 -150 -250 -150 -250 -150 -250 N
+P 5 0 1 8 -130 -40 -130 -50 -150 -50 -150 -50 -150 -50 N
+P 6 0 1 8 -50 -250 -150 -200 -50 -150 -50 -250 -50 -250 -50 -250 N
+P 6 0 1 8 -50 -50 -150 0 -50 50 -50 -50 -50 -50 -50 -50 N
+P 6 0 1 8 50 -150 150 -200 50 -250 50 -150 50 -150 50 -150 N
+P 6 0 1 8 50 50 150 0 50 -50 50 50 50 50 50 50 N
+X K 1 -300 0 150 R 50 50 0 1 P
+X K 2 -300 -200 150 R 50 50 0 1 P
+X O 3 400 -100 150 L 50 50 0 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+X pwr 1 0 0 0 U 50 50 0 0 w
+ENDDRAW
+ENDDEF
+#
+# Q_PMOS_GSD
+#
+DEF Q_PMOS_GSD Q 0 0 Y N 1 F N
+F0 "Q" 200 50 50 H V L CNN
+F1 "Q_PMOS_GSD" 200 -50 50 H V L CNN
+F2 "" 200 100 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 65 0 111 0 1 10 N
+C 100 -70 11 0 1 0 F
+C 100 70 11 0 1 0 F
+P 2 0 1 0 2 0 10 0 N
+P 2 0 1 0 30 -70 100 -70 N
+P 2 0 1 10 30 -50 30 -90 N
+P 2 0 1 0 30 0 100 0 N
+P 2 0 1 10 30 20 30 -20 N
+P 2 0 1 0 30 70 100 70 N
+P 2 0 1 10 30 90 30 50 N
+P 2 0 1 0 100 -70 100 -100 N
+P 2 0 1 0 100 -70 100 0 N
+P 2 0 1 0 100 100 100 70 N
+P 3 0 1 10 10 75 10 -75 10 -75 N
+P 4 0 1 0 90 0 50 -15 50 15 90 0 F
+P 4 0 1 0 100 -70 130 -70 130 70 100 70 N
+P 4 0 1 0 110 -20 115 -15 145 -15 150 -10 N
+P 4 0 1 0 130 -15 115 10 145 10 130 -15 N
+X G 1 -200 0 200 R 50 50 1 1 I
+X S 2 100 -200 100 U 50 50 1 1 P
+X D 3 100 200 100 D 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# STM32F042C6Tx
+#
+DEF STM32F042C6Tx U 0 40 Y Y 1 L N
+F0 "U" -3000 1725 50 H V L BNN
+F1 "STM32F042C6Tx" 3000 1725 50 H V R BNN
+F2 "LQFP48" 3000 1675 50 H V R TNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+S -3000 -1700 3000 1700 0 1 10 f
+X VBAT 1 -3100 1100 100 R 50 50 1 1 W
+X ADC_IN0/RTC_TAMP2/SYS_WKUP1/TIM2_CH1/TIM2_ETR/TSC_G1_IO1/USART2_CTS/PA0 10 3100 100 100 L 50 50 1 1 B
+X ADC_IN1/TIM2_CH2/TSC_G1_IO2/USART2_DE/USART2_RTS/PA1 11 3100 0 100 L 50 50 1 1 B
+X ADC_IN2/SYS_WKUP4/TIM2_CH3/TSC_G1_IO3/USART2_TX/PA2 12 3100 -100 100 L 50 50 1 1 B
+X ADC_IN3/TIM2_CH4/TSC_G1_IO4/USART2_RX/PA3 13 3100 -200 100 L 50 50 1 1 B
+X ADC_IN4/I2S1_WS/SPI1_NSS/TIM14_CH1/TSC_G2_IO1/USART2_CK/USB_OE/PA4 14 3100 -300 100 L 50 50 1 1 B
+X ADC_IN5/CEC/I2S1_CK/SPI1_SCK/TIM2_CH1/TIM2_ETR/TSC_G2_IO2/PA5 15 3100 -400 100 L 50 50 1 1 B
+X ADC_IN6/I2S1_MCK/SPI1_MISO/TIM16_CH1/TIM1_BKIN/TIM3_CH1/TSC_G2_IO3/PA6 16 3100 -500 100 L 50 50 1 1 B
+X ADC_IN7/I2S1_SD/SPI1_MOSI/TIM14_CH1/TIM17_CH1/TIM1_CH1N/TIM3_CH2/TSC_G2_IO4/PA7 17 3100 -600 100 L 50 50 1 1 B
+X PB0/ADC_IN8/TIM1_CH2N/TIM3_CH3/TSC_G3_IO2 18 -3100 100 100 R 50 50 1 1 B
+X PB1/ADC_IN9/TIM14_CH1/TIM1_CH3N/TIM3_CH4/TSC_G3_IO3 19 -3100 0 100 R 50 50 1 1 B
+X PC13/RTC_OUT_ALARM/RTC_OUT_CALIB/RTC_TAMP1/RTC_TS/SYS_WKUP2 2 -3100 500 100 R 50 50 1 1 B
+X PB2/TSC_G3_IO4 20 -3100 -100 100 R 50 50 1 1 B
+X PB10/CEC/I2C1_SCL/SPI2_SCK/TIM2_CH3/TSC_SYNC 21 -3100 -900 100 R 50 50 1 1 B
+X PB11/I2C1_SDA/TIM2_CH4 22 -3100 -1000 100 R 50 50 1 1 B
+X VSS 23 -200 -1800 100 U 50 50 1 1 W
+X VDD 24 -200 1800 100 D 50 50 1 1 W
+X PB12/SPI2_NSS/TIM1_BKIN 25 -3100 -1100 100 R 50 50 1 1 B
+X PB13/I2C1_SCL/SPI2_SCK/TIM1_CH1N 26 -3100 -1200 100 R 50 50 1 1 B
+X PB14/I2C1_SDA/SPI2_MISO/TIM1_CH2N 27 -3100 -1300 100 R 50 50 1 1 B
+X PB15/RTC_REFIN/SPI2_MOSI/SYS_WKUP7/TIM1_CH3N 28 -3100 -1400 100 R 50 50 1 1 B
+X CRS_SYNC/RCC_MCO/TIM1_CH1/USART1_CK/PA8 29 3100 -700 100 L 50 50 1 1 B
+X PC14/RCC_OSC32_IN 3 -3100 400 100 R 50 50 1 1 B
+X I2C1_SCL/TIM1_CH2/TSC_G4_IO1/USART1_TX/PA9 30 3100 -800 100 L 50 50 1 1 B
+X I2C1_SDA/TIM17_BKIN/TIM1_CH3/TSC_G4_IO2/USART1_RX/PA10 31 3100 -900 100 L 50 50 1 1 B
+X CAN_RX/I2C1_SCL/TIM1_CH4/TSC_G4_IO3/USART1_CTS/USB_DM/PA11 32 3100 -1000 100 L 50 50 1 1 B
+X CAN_TX/I2C1_SDA/TIM1_ETR/TSC_G4_IO4/USART1_DE/USART1_RTS/USB_DP/PA12 33 3100 -1100 100 L 50 50 1 1 B
+X IR_OUT/SYS_SWDIO/USB_OE/PA13 34 3100 -1200 100 L 50 50 1 1 B
+X VSS 35 -100 -1800 100 U 50 50 1 1 W
+X VDDIO2 36 100 1800 100 D 50 50 1 1 W
+X SYS_SWCLK/USART2_TX/PA14 37 3100 -1300 100 L 50 50 1 1 B
+X I2S1_WS/SPI1_NSS/TIM2_CH1/TIM2_ETR/USART2_RX/USB_OE/PA15 38 3100 -1400 100 L 50 50 1 1 B
+X PB3/I2S1_CK/SPI1_SCK/TIM2_CH2/TSC_G5_IO1 39 -3100 -200 100 R 50 50 1 1 B
+X PC15/RCC_OSC32_OUT 4 -3100 300 100 R 50 50 1 1 B
+X PB4/I2S1_MCK/SPI1_MISO/TIM17_BKIN/TIM3_CH1/TSC_G5_IO2 40 -3100 -300 100 R 50 50 1 1 B
+X PB5/I2C1_SMBA/I2S1_SD/SPI1_MOSI/SYS_WKUP6/TIM16_BKIN/TIM3_CH2 41 -3100 -400 100 R 50 50 1 1 B
+X PB6/I2C1_SCL/TIM16_CH1N/TSC_G5_IO3/USART1_TX 42 -3100 -500 100 R 50 50 1 1 B
+X PB7/I2C1_SDA/TIM17_CH1N/TSC_G5_IO4/USART1_RX 43 -3100 -600 100 R 50 50 1 1 B
+X PF11 44 -3100 700 100 R 50 50 1 1 B
+X PB8/CAN_RX/CEC/I2C1_SCL/TIM16_CH1/TSC_SYNC 45 -3100 -700 100 R 50 50 1 1 B
+X PB9/CAN_TX/I2C1_SDA/IR_OUT/SPI2_NSS/TIM17_CH1 46 -3100 -800 100 R 50 50 1 1 B
+X VSS 47 0 -1800 100 U 50 50 1 1 W
+X VDD 48 -100 1800 100 D 50 50 1 1 W
+X PF0/CRS_SYNC/I2C1_SDA/RCC_OSC_IN 5 -3100 900 100 R 50 50 1 1 I
+X PF1/I2C1_SCL/RCC_OSC_OUT 6 -3100 800 100 R 50 50 1 1 I
+X NRST 7 -3100 1300 100 R 50 50 1 1 I
+X VSSA 8 100 -1800 100 U 50 50 1 1 W
+X VDDA 9 0 1800 100 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# TPS2051
+#
+DEF TPS2051 U 0 40 Y Y 1 F N
+F0 "U" 0 -300 60 H V C CNN
+F1 "TPS2051" 0 300 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 250 250 -250 0 1 0 N
+X GND 1 -450 150 200 R 50 50 1 1 W
+X IN 2 -450 50 200 R 50 50 1 1 W
+X IN 3 -450 -50 200 R 50 50 1 1 P
+X EN 4 -450 -150 200 R 50 50 1 1 I
+X ~OC 5 450 -150 200 L 50 50 1 1 O
+X OUT 6 450 -50 200 L 50 50 1 1 P
+X OUT 7 450 50 200 L 50 50 1 1 P
+X OUT 8 450 150 200 L 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# USB6B1
+#
+DEF USB6B1 D 0 30 Y N 1 F N
+F0 "D" 0 -450 50 H V C CNN
+F1 "USB6B1" 0 400 50 H V C CNN
+F2 "" 200 -100 50 V V C CNN
+F3 "" 200 -100 50 V V C CNN
+$FPLIST
+ SO8
+$ENDFPLIST
+DRAW
+C -150 -300 7 0 1 0 N
+C -150 100 7 0 1 0 N
+C -150 300 7 0 1 0 N
+C 0 -300 7 0 1 0 N
+C 0 -100 7 0 1 0 N
+C 0 300 7 0 1 0 N
+C 200 -300 7 0 1 0 N
+C 200 300 7 0 1 0 N
+S -300 -100 300 -100 0 1 0 N
+S -300 300 300 300 0 1 0 N
+S -200 -150 -100 -150 0 1 0 N
+S -200 250 -100 250 0 1 0 N
+S -150 300 -150 -300 0 1 0 N
+S -50 -150 50 -150 0 1 0 N
+S -50 250 50 250 0 1 0 N
+S 0 300 0 -300 0 1 0 N
+S 200 300 200 -300 0 1 0 N
+S 300 -300 -300 -300 0 1 0 N
+S 300 100 -300 100 0 1 0 N
+P 3 0 1 8 150 50 250 50 250 50 N
+P 4 0 1 8 150 50 150 30 160 30 160 30 N
+P 4 0 1 8 250 50 250 70 240 70 240 70 N
+P 5 0 1 0 -250 350 300 350 300 -350 -250 -350 -250 350 N
+P 6 0 1 8 -200 -250 -150 -150 -100 -250 -200 -250 -200 -250 -200 -250 N
+P 6 0 1 8 -200 150 -150 250 -100 150 -200 150 -200 150 -200 150 N
+P 6 0 1 8 -50 -250 0 -150 50 -250 -50 -250 -50 -250 -50 -250 N
+P 6 0 1 8 -50 150 0 250 50 150 -50 150 -50 150 -50 150 N
+P 6 0 1 8 150 -50 200 50 250 -50 150 -50 150 -50 150 -50 N
+X VCC 1 -500 300 200 R 50 50 1 1 P
+X I/O1 2 -500 100 200 R 50 50 1 1 P
+X I/O2 3 -500 -100 200 R 50 50 1 1 P
+X GND 4 -500 -300 200 R 50 50 1 1 P
+X GND 5 500 -300 200 L 50 50 1 1 P
+X I/O2 6 500 -100 200 L 50 50 1 1 P
+X I/O1 7 500 100 200 L 50 50 1 1 P
+X VCC 8 500 300 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# USB_A-RESCUE-stm32
+#
+DEF USB_A-RESCUE-stm32 P 0 40 Y Y 1 F N
+F0 "P" 200 -200 50 H V C CNN
+F1 "USB_A-RESCUE-stm32" -50 200 50 H V C CNN
+F2 "" -50 -100 50 V V C CNN
+F3 "" -50 -100 50 V V C CNN
+$FPLIST
+ USB*
+$ENDFPLIST
+DRAW
+S -250 -150 150 150 0 1 0 N
+S -205 -150 -195 -120 0 1 0 N
+S -105 -150 -95 -120 0 1 0 N
+S -5 -150 5 -120 0 1 0 N
+S 95 -150 105 -120 0 1 0 N
+X VBUS 1 -200 -300 150 U 50 50 1 1 W
+X D- 2 -100 -300 150 U 50 50 1 1 P
+X D+ 3 0 -300 150 U 50 50 1 1 P
+X GND 4 100 -300 150 U 50 50 1 1 W
+X shield 5 300 100 150 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library

F1-nolib/chronometer_v1/kicad/sym-lib-table

@@ -0,0 +1,4 @@
+(sym_lib_table
+  (lib (name Chrono)(type Legacy)(uri ${KIPRJMOD}/Chrono.lib)(options "")(descr ""))
+  (lib (name stm32-rescue)(type Legacy)(uri ${KIPRJMOD}/stm32-rescue.lib)(options "")(descr ""))
+)

F1-nolib/chronometer_v1/src_new/GPS.c

@@ -0,0 +1,186 @@
+/*
+ * GPS.c
+ *
+ * Copyright 2015 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include "GPS.h"
+#include "hardware.h"
+#include "time.h"
+#include "usart.h"
+#include "str.h"
+#include "usb.h"
+#include <string.h> // memcpy
+
+#define GPS_endline() do{usart_send(GPS_USART, "\r\n"); transmit_tbuf(GPS_USART); }while(0)
+#define GPS_send_string(str) do{usart_send(GPS_USART, str);}while(0)
+
+gps_status GPS_status = GPS_NOTFOUND;
+int need2startseq = 1;
+
+static uint8_t hex(uint8_t n){
+    return ((n < 10) ? (n+'0') : (n+'A'-10));
+}
+
+/**
+ * Check checksum
+ */
+static int checksum_true(const char *buf){
+    char *eol;
+    uint8_t checksum = 0, cs[3];
+    if(*buf != '$' || !(eol = getchr(buf, '*'))){
+        return 0;
+    }
+    while(++buf != eol)
+        checksum ^= (uint8_t)*buf;
+    ++buf;
+    cs[0] = hex(checksum >> 4);
+    cs[1] = hex(checksum & 0x0f);
+    if(buf[0] == cs[0] && buf[1] == cs[1])
+        return 1;
+    return 0;
+}
+
+static void send_chksum(uint8_t chs){
+    usart_putchar(GPS_USART, hex(chs >> 4));
+    //usart_putchar(1, hex(chs >> 4));
+    usart_putchar(GPS_USART, hex(chs & 0x0f));
+    //usart_putchar(1, hex(chs & 0x0f));
+}
+/**
+ * Calculate checksum & write message to port
+ * @param  buf - command to write (without leading $ and trailing *)
+ * return 0 if fails
+ */
+static void write_with_checksum(const char *buf){
+    char *txt = NULL;
+     // clear old buffer data
+    for(int i = 0; i < 10000; ++i){
+        if(usartrx(GPS_USART)){
+            usart_getline(GPS_USART, &txt);
+            DBG("Old data");
+            GPS_parse_answer(txt);
+            break;
+        }
+    }
+    //DBG("Send:");
+    uint8_t checksum = 0;
+    usart_putchar(GPS_USART, '$');
+    //usart_putchar(1, '$');
+    GPS_send_string(buf);
+    //SEND(buf);
+    do{
+        checksum ^= *buf++;
+    }while(*buf);
+    usart_putchar(GPS_USART, '*');
+    //usart_putchar(1, '*');
+    send_chksum(checksum);
+    //newline();
+    GPS_endline();
+}
+
+
+/*
+ * MTK fields format:
+ *      $PMTKxxx,yyy,zzz*2E
+ *          P - proprietary, MTK - always this, xxx - packet type, yyy,zzz - packet data
+ * Packet types:
+ * 220 - PMTK_SET_POS_FIX, data - position fix interval (msec, > 200)
+ * 255 - PMTK_SET_SYNC_PPS_NMEA - turn on/off (def - off) PPS, data = 0/1 ->  "$PMTK255,1" turn ON
+ * 285 - PMTK_SET_PPS_CONFIG - set PPS configuration, data fields:
+ *      1st - 0-disable, 1-after 1st fix, 2-3D only, 3-2D/3D only, 4-always
+ *      2nd - 2..998 - pulse width
+ * 314 - PMTK_API_SET_NMEA_OUTPUT - set output messages, N== N fixes per output,
+ *      order of messages: GLL,RMC,VTG,GGA,GSA,GSV,GRS,GST, only RMC per every pos fix:
+ *      $PMTK314,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+ * 386 - PMTK_API_SET_STATIC_NAV_THD speed threshold (m/s) for static navigation
+ *      $PMTK386,1.5
+ * ;
+ */
+
+/**
+ * Send starting sequences (get only RMC messages)
+ */
+void GPS_send_start_seq(){
+    DBG("Send start seq");
+    // turn ON PPS:
+    write_with_checksum("PMTK255,1");
+    // set pulse width to 10ms with working after 1st fix
+    write_with_checksum("PMTK285,1,10");
+    // set only RMC:
+    write_with_checksum("PMTK314,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
+    // set static speed threshold
+    write_with_checksum("PMTK386,1.5");
+    need2startseq = 0;
+}
+
+// send "full cold start" command to clear all almanach & location data
+void GPS_send_FullColdStart(){
+    write_with_checksum("PMTK104");
+}
+
+/**
+ * Parse answer from GPS module
+ *
+ * Recommended minimum specific GPS/Transit data
+ * $GPRMC,hhmmss.sss,status,latitude,N,longitude,E,spd,cog,ddmmyy,mv,mvE,mode*cs
+ * 1    = UTC of position fix
+ * 2    = Data status (V=valid, A=invalid)
+ * 3    = Latitude (ddmm.mmmm)
+ * 4    = N or S
+ * 5    = Longitude (dddmm.mmmm)
+ * 6    = E or W
+ * 7    = Speed over ground in knots
+ * 8    = Cource over ground in degrees
+ * 9    = UT date (ddmmyy)
+ * 10   = Magnetic variation degrees (Easterly var. subtracts from true course)
+ * 11   = E or W
+ * 12   = Mode: N(bad), E(approx), A(auto), D(diff)
+ * 213457.00,A,4340.59415,N,04127.47560,E,2.494,,290615,,,A*7B
+ */
+void GPS_parse_answer(const char *buf){
+    char *ptr;
+    if(buf[1] == 'P') return; // answers to proprietary messages
+    if(cmpstr(buf+3, "RMC", 3)){ // not RMC message
+        need2startseq = 1;
+        return;
+    }
+    if(!checksum_true(buf)){
+        return; // wrong checksum
+    }
+    if(showGPSstr){
+        showGPSstr = 0;
+        USB_send(buf);
+    }
+    buf += 7; // skip header
+    if(*buf == ','){ // time unknown
+        GPS_status = GPS_WAIT;
+        return;
+    }
+    ptr = getchr(buf, ',');
+    if(!ptr ) return;
+    *ptr++ = 0;
+    if(*ptr == 'A'){
+        GPS_status = GPS_VALID;
+        set_time(buf);
+    }else{
+        uint8_t goth = (buf[0]-'0')*10 + buf[1]-'0';
+        if(current_time.H != goth) set_time(buf); // set time once per hour even if it's not valid
+        GPS_status = GPS_NOT_VALID;
+    }
+}

F1-nolib/chronometer_v1/src_new/GPS.h

@@ -0,0 +1,43 @@
+/*
+ * GPS.h
+ *
+ * Copyright 2015 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#pragma once
+#ifndef __GPS_H__
+#define __GPS_H__
+
+#include "stm32f1.h"
+
+extern int need2startseq;
+
+typedef enum{
+     GPS_NOTFOUND   // default status before first RMC message
+    ,GPS_WAIT       // wait for satellites
+    ,GPS_NOT_VALID  // time known, but not valid
+    ,GPS_VALID
+} gps_status;
+
+extern gps_status GPS_status;
+
+void GPS_parse_answer(const char *string);
+void GPS_send_start_seq();
+void GPS_send_FullColdStart();
+
+#endif // __GPS_H__

F1-nolib/chronometer_v1/src_new/Makefile

@@ -0,0 +1,142 @@
+BINARY		= chrono
+BOOTPORT	?= /dev/ttyUSB0
+BOOTSPEED	?= 115200
+# MCU FAMILY
+FAMILY		?= F1
+# MCU code
+MCU			?= F103x8
+# density (stm32f10x.h, lines 70-84)
+DENSITY 	?= MD
+# change this linking script depending on particular MCU model,
+LDSCRIPT	?= stm32F103xB.ld
+DEFS		= -DVERSION=\"0.0.2\"
+# debug
+#DEFS		+= -DEBUG
+# proxy GPS output over USART1
+DEFS += -DUSART1PROXY
+
+INDEPENDENT_HEADERS=
+
+FP_FLAGS	?= -msoft-float -mfloat-abi=soft
+ASM_FLAGS	?= -mthumb -mcpu=cortex-m3 -mfix-cortex-m3-ldrd
+ARCH_FLAGS	= $(ASM_FLAGS) $(FP_FLAGS)
+
+###############################################################################
+# Executables
+#PREFIX		?= arm-none-eabi
+# gcc from arm web site 
+PREFIX		?= /opt/bin/arm-none-eabi
+TOOLCHLIB	?= /opt/arm-none-eabi/lib
+RM			:= rm -f
+RMDIR		:= rmdir
+CC			:= $(PREFIX)-gcc
+# don't replace ld with gcc: the binary size would be much greater!!
+LD			:= $(PREFIX)-ld
+AR			:= $(PREFIX)-ar
+AS			:= $(PREFIX)-as
+SIZE 		:= $(PREFIX)-size
+OBJCOPY		:= $(PREFIX)-objcopy
+OBJDUMP		:= $(PREFIX)-objdump
+GDB			:= $(PREFIX)-gdb
+STFLASH		:= $(shell which st-flash)
+STBOOT		:= $(shell which stm32flash)
+DFUUTIL		:= $(shell which dfu-util)
+
+###############################################################################
+# Source files
+OBJDIR 		= mk
+SRC			:= $(wildcard *.c)
+OBJS		:= $(addprefix $(OBJDIR)/, $(SRC:%.c=%.o))
+STARTUP		= $(OBJDIR)/startup.o
+OBJS 		+= $(STARTUP)
+# dependencies: we need them to recompile files if their headers-dependencies changed
+DEPS		:= $(OBJS:.o=.d)
+
+INC_DIR ?= ../inc
+
+INCLUDE 	:= -I$(INC_DIR)/Fx -I$(INC_DIR)/cm
+LIB_DIR		:= $(INC_DIR)/ld
+
+###############################################################################
+# C flags
+CFLAGS		+= -O2 -g -D__thumb2__=1 -MD
+CFLAGS		+= -Wall -Werror -Wextra -Wshadow 
+CFLAGS		+= -fno-common -ffunction-sections -fdata-sections -fno-stack-protector
+CFLAGS		+=  $(ARCH_FLAGS)
+
+###############################################################################
+# Linker flags
+LDFLAGS		+= --static -nostartfiles -nostdlibs 
+LDFLAGS		+= -L$(LIB_DIR) -L$(TOOLCHLIB)
+LDFLAGS		+= -T$(LDSCRIPT)
+
+###############################################################################
+# Used libraries
+LDLIBS		+=  -lc $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+
+DEFS		+= -DSTM32$(FAMILY) -DSTM32$(MCU) -DSTM32F10X_$(DENSITY)
+
+ELF		:= $(OBJDIR)/$(BINARY).elf
+LIST	:= $(OBJDIR)/$(BINARY).list
+BIN		:= $(BINARY).bin
+HEX		:= $(BINARY).hex
+
+all: bin list size
+
+elf: $(ELF)
+bin: $(BIN)
+hex: $(HEX)
+list: $(LIST)
+
+ifneq ($(MAKECMDGOALS),clean)
+-include $(DEPS)
+endif
+
+$(OBJDIR):
+	mkdir $(OBJDIR)
+
+$(STARTUP): $(INC_DIR)/startup/vector.c
+	$(CC) $(CFLAGS) $(DEFS) $(INCLUDE) -o $@ -c $<
+
+$(OBJDIR)/%.o: %.c
+	@echo "  CC      $<"
+	$(CC) $(CFLAGS) $(DEFS) $(INCLUDE) -o $@ -c $<
+
+$(BIN): $(ELF)
+	@echo "  OBJCOPY $(BIN)"
+	$(OBJCOPY) -Obinary $(ELF) $(BIN)
+
+$(HEX): $(ELF)
+	@echo "  OBJCOPY $(HEX)"
+	$(OBJCOPY) -Oihex $(ELF) $(HEX)
+
+$(LIST): $(ELF)
+	@echo "  OBJDUMP $(LIST)"
+	$(OBJDUMP) -S $(ELF) > $(LIST)
+
+$(ELF): $(OBJDIR) $(OBJS) $(LDSCRIPT)
+	@echo "  LD      $(ELF)"
+	$(LD) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $(ELF)
+
+size: $(ELF)
+	$(SIZE) $(ELF)    
+
+clean:
+	@echo "  CLEAN"
+	$(RM) $(OBJS) $(DEPS) $(ELF) $(HEX) $(LIST)
+	@rmdir $(OBJDIR) 2>/dev/null || true
+
+
+flash: $(BIN)
+	@echo "  FLASH  $(BIN)"
+	$(STFLASH) write $(BIN) 0x8000000
+
+boot: $(BIN)
+	@echo "  LOAD $(BIN) through bootloader"
+	$(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN)
+
+dfuboot: $(BIN)
+	@echo "  LOAD  $(BIN) THROUGH DFU"
+	$(DFUUTIL) -a0 -D $(BIN) -s 0x08000000
+
+.PHONY: clean flash boot

F1-nolib/chronometer_v1/src_new/Readme.md

@@ -0,0 +1,33 @@
+Chronometer for downhill competitions
+=====================================
+
+## Pinout
+
+- PA11/12 - USB
+- PA9(Tx),PA10 (debug mode) - USART1 - debug console
+- PA2(Tx), PA3 - USART2 - GPS
+- PB10(Tx), PB11 - USART3 - LIDAR - TRIG3
+
+- PA1  - PPS signal from GPS (EXTI)
+
+- PA4  - TRIG2 - 12V trigger (EXTI)
+- PA13 - TRIG0 - button0 (EXTI)
+- PA14 - TRIG1 - button1/laser/etc (EXTI)
+- PA15 - USB pullup
+
+- PB8, PB9 - onboard LEDs (0/1)
+
+- PC13 - buzzer
+
+## LEDS
+
+- LED0 - shining when there's no PPS signal, fades for 0.25s on PPS
+- LED1 - don't shines if no GPS found, shines when time not valid, blinks when time valid
+
+### Not implemented yet:
+
+- PA5,6,7 (SCK, MISO, MOSI) - SPI
+- PB0 - TRIG4 - ADC channel 8
+- PB6/7 (SCL, SDA) - I2C
+
+

F1-nolib/chronometer_v1/src_new/Readme_rus.txt

@@ -0,0 +1,147 @@
+!!! инвертировать USB_PU
+
+
+****** Распиновка ******
+
+=== Интерфейсы I/O ===
+- PA11/12 - USB
+- PA9(Tx), PA10(Rx) - USART1 - прокси RMC-сообщений GPS. 
+- PA2(Tx), PA3(Rx) - USART2 - подключение GPS-приемника.
+- PB10(Tx), PB11(Rx) - USART3 - подключение лидара.
+
+=== Остальные порты ===
+- PA1  - PPS сигнал от GPS; сюда можно подключать любой дополнительный высокоомный вход напрямую.
+- PA4  - TRIG2 - подключен к каналу 12В.
+- PA13 - TRIG0 - кнопка или створ, замыкающий контакты.
+- PA14 - TRIG1 - так же, как и вход TRIG0.
+- PA15 - подтяжка USB.
+- PB0 - TRIG4 - триггер по АЦП.
+- PB8, PB9 - индикаторные светодиоды.
+- PC13 - пищалка.
+
+=== Светодиоды ===
+- LED0 (зеленый) - при отсутствии сигнала PPS просто горит, если PPS появляется - мигает (затухает на 0.25с на каждый сигнал).
+- LED1 (красный) - индикатор GPS: не горит, если приемник не обнаружен, горит, если неуверенный прием времени (буква "V" во второй позиции RMC-сообщения), мигает при уверенном приеме (буква "A" во второй позиции).
+Судя по эксперименту, даже через час после пропадания сигнала точность определения события - не хуже 1мс. Сам GPS-приемник выдает
+PPS даже при отсутствии спутников - лишь бы он успел "подхватить" точное время и начать генерировать pps. Начинать работу можно сразу,
+как только замигает зеленый светодиод после мигающего красного.
+
+
+****** Триггеры ******
+На прототипе распаяно два входа на триггеры: TRIG0 и TRIG2. К TRIG2 нужно подключать 12-вольтный сигнал, ток не меньше 10мА.
+Если створ имеет открытый коллектор, то выход створа подключается к минусу TRIG2, а к плюсу подключается 12В с источника питания.
+TRIG0 предназначен для подключения кнопки или концевика, просто замыкающего контакты. Никакого внешнего напряжения там быть не должно!
+
+TRIG4 - аналоговый вход. Если будут ложные срабатывания на девбордах, порт PB0 нужно напрямую или через резистор до 10кОм посадить на землю.
+
+Иногда бывают ложные срабатывания триггеров TRIG0..TRIG2, связанные с мощными источниками искр (зажигание, искрящиеся обмотки и т.п.). 
+В случае таких ложных срабатываний рекомендуется заземлить катод источника питания хронометра. 
+
+При подключении внешней кнопки желательно, чтобы она имела нормально замкнутые контакты - это предотвратит ложные срабатывания из-за электромагнитных помех.
+
+
+****** Подключение ******
+Хронометр эмулирует "китайский" преобразователь PL2303. В линуксе нужно, чтобы был скомпилирован соответствующий модуль ядра.
+В андроиде работает "из коробки". В мастдайке новые драйвера PL2303 имеют защиту от подделок (те просто не работают с этими дровами),
+поэтому для нормальной работы необходимо найти и установить старые драйвера.
+
+К выходам PA9/PA10 можно подключить преобразователь USART<>USB или накинуть их напрямую на ноги Rx/Tx "малинки" (не забыв соединить
+земли хронометра и малинки): PA9(Tx) соединить с Rx, PA10(Rx) - с Tx. Этот USART проксирует RMC-сообщения GPS-приемника (уже после
+обработки микроконтроллером, поэтому если МК выключен, а приемник включен, сигнала все равно не будет).
+
+Для подключения PPS сигнала к "малинке" нужно напрямую соединить соответствующую ногу GPIO "малинки" с портом PA1 девборды. 
+На прототипе нужно подпаяться к дорожке, выходящей с ноги PPS (отмечено маркером).
+
+Подтяжка USB есть лишь на прототипе, на девбордах ее нет. Поэтому в случае перезагрузки микроконтроллера девборды для возобновления
+соединения необходимо переткнуть шнурок USB. В этом плане прототип надежней: сбросить МК можно независимо от питания GPS.
+
+На прототипе и девбордах отсутствует подсоединение пищалки. На девбордах при желании можно накинуть на PC13 что-нибудь для индикации
+срабатывания створа (активный выход - "1" в течение 0.3с).
+
+На девбордах не распаяны светодиодные индикаторы. Особого смысла в них нет, но если понадобится подключить, нагрузка должна висеть на
+PB8/PB9. Активный выход - низкий. Нога МК настроена в режиме open-drain, но внешняя подтяжка не должна быть выше +3.5В. И потребление
+не больше 5мА на ногу.
+
+
+****** Конфигурация ******
+Хронометр конфигурируется через USB. Ввод команд не сопровождается эхом (чтобы удобней было работать из внешних программ), поэтому
+для удобства можно тексты команд копировать из окна текстового редактора.
+Чтобы увидеть подсказку, достаточно отправить любую строку, начинающуюся с вопросительного знака. Появится справка:
+
+adcmax - max ADC value treshold for trigger
+adcmin - min -//- (triggered when ADval>min & <max
+adcval - get ADC value
+buzzerS - turn buzzer ON/OFF
+distmin - min distance threshold (cm)
+distmax - max distance threshold (cm)
+gpsrestart - send Full Cold Restart to GPS
+gpsstring - current GPS data string
+ledsS - turn leds on/off (1/0)
+mcutemp - MCU temperature
+pullupNS - triggers pullups state (N - trigger No, S - 0/1 for off/on)
+showconf - show current configuration
+time - print time
+store - store new configuration in flash
+triglevelNS - working trigger N level S
+trigpauseNP - pause (P, ms) after trigger N shots
+trigtimeN - show last trigger N time
+vdd - Vdd value
+
+Из нужного здесь: 
+- gpsrestart - перезапуск GPS (если вдруг начнет глючить - у меня такого не случалось), делает "холодный" рестарт. Команда 
+	проверялась лишь на прототипе.
+- gpsstring - вывод очередного сообщения от GPS. Если все нормально, то появится строка RMC вроде
+	$GPRMC,124001.000,A,4340.9369,N,04127.5034,E,0.00,33.26,150819,,,A*5C
+- pullupNS - включить или выключить внутренние верхние подтяжки для триггеров 0..3 (особо не нужно, т.к. подтяжки слабые, и если
+	будет нужна подтяжка, лучше сделать сильную внешнюю).
+- showconf - отображение текущей конфигурации, например:
+	CONFIG:
+	DISTMIN=50
+	DISTMAX=1000
+	ADCMIN=1024
+	ADCMAX=3072
+	PULLUPS=255
+	TRIGLVL=0
+	TRIGPAUSE={400, 400, 400, 300, 300}
+	ENDCONFIG
+
+	пункты конфигурации: DISTMIN/DISTMAX относятся к лидару, ADCMIN/ADCMAX ко входу АЦП, PULLUPS - состояние подтяжек
+		(каждый бит, начиная с младшего - состояние соответствующей подтяжки; 0 - не активна, 1 - активна).
+	TRIGLVL - конфигурация уровней срабатывания, каждый бит, начиная с младшего (всего три младших бита, как и в PULLUPS),
+		равен нулю, если для соответствующего триггера срабатывание при перепаде 1->0, равен единице, если при
+		перепаде 0->1.
+	TRIGPAUSE - пауза между срабатываниями триггера: если после срабатывания произойдет следующее событие за интервал, меньший
+		данного, это событие учитываться не будет.
+- time - отображает текущее время так, как оно бы отобразилось при срабатывании триггера, например,
+	55725.961 (15:28:45)
+	ВРЕМЯ ИЗМЕРЯЕТСЯ В UTC!!! Первое число - количество секунд и миллисекунд с начала суток по UTC, в скобках
+	указывается человекочитаемое время.
+- store - сохранить новую конфигурацию во флеш-памяти МК.
+- triglevelNS - рабочий уровень триггера. Здесь N - номер триггера (0..2), S - уровень (0/1). Скажем, чтобы триггер 0 срабатывал
+	при перепаде 1->0, нужно написать команду
+	triglevel00
+	а чтобы триггер 2 срабатывал при перепаде 0->1,
+	triglevel21
+- trigpauseNP - задать паузу для триггера N, пауза в миллисекундах. Если написать 0, паузы не будет и каждое срабатывание 
+	будет вызывать соответствующее сообщение. Эта пауза нужнад для защиты от "звона" и нескольких срабатываний на "дырках"
+	в объекте. Меньше 50мс лучше не делать.
+- trigtimeN - отображение последнего времени срабатывания триггера N, например, на запрос trigtime0, может быть выведено:
+	TRIG0=45212.930 (12:33:32)
+	Если срабатываний с момента включения не было, выведутся нули:
+	TRIG4=0.000 (00:00:00)
+
+После изменения конфигурации и ее сохранения необходимо нажатием на reset или отключением/включением питания перезагрузить МК,
+т.к. некоторые параметры активируются лишь при старте.
+
+
+****** Девборды и плата-прототип ******
+На платках из девборд два канала опторазвязок подключены к триггерам TRIG0 и TRIG1.
+Синий провод - земля, красные - +12В для каждого канала. Т.е. схема рассчитана на срабатывание по появлению плюса на одном из каналов.
+
+В случае необходимости срабатывания по подтяжке к земле, нужно разорвать землю на входах опторазвязок и, наоборот, объединить плюсы.
+На плюсы подать +12В, минусы подключить к сигнальным выходам створов.
+
+На прототипе распаяны развязки только на два канала: TRIG0 - для подключения чего-то, замыкающего контакты, и TRIG2 - для подключения
+чего-то, выдающего 12В. Я оставил такую конфигурацию: к TRIG0 можно подключить нормально замкнутую кнопку (triglevel01), а TRIG2
+сработает при поступлении туда 12В (triglevel21).
+

F1-nolib/chronometer_v1/src_new/adc.c

@@ -0,0 +1,93 @@
+/*
+ * This file is part of the chronometer project.
+ * Copyright 2018 Edward V. Emelianov <edward.emelianoff@gmail.com>.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "adc.h"
+#include "flash.h"
+#include "hardware.h"
+
+/**
+ * @brief ADC_array - array for ADC channels with median filtering:
+ * 0 - Rvar
+ * 1 - internal Tsens
+ * 2 - Vref
+ */
+uint16_t ADC_array[NUMBER_OF_ADC_CHANNELS*9];
+
+/**
+ * @brief getADCval - calculate median value for `nch` channel
+ * @param nch - number of channel
+ * @return
+ */
+uint16_t getADCval(int nch){
+    int i, addr = nch;
+    register uint16_t temp;
+#define PIX_SORT(a,b) { if ((a)>(b)) PIX_SWAP((a),(b)); }
+#define PIX_SWAP(a,b) { temp=(a);(a)=(b);(b)=temp; }
+    uint16_t p[9];
+    for(i = 0; i < 9; ++i, addr += NUMBER_OF_ADC_CHANNELS) // first we should prepare array for optmed
+        p[i] = ADC_array[addr];
+    PIX_SORT(p[1], p[2]) ; PIX_SORT(p[4], p[5]) ; PIX_SORT(p[7], p[8]) ;
+    PIX_SORT(p[0], p[1]) ; PIX_SORT(p[3], p[4]) ; PIX_SORT(p[6], p[7]) ;
+    PIX_SORT(p[1], p[2]) ; PIX_SORT(p[4], p[5]) ; PIX_SORT(p[7], p[8]) ;
+    PIX_SORT(p[0], p[3]) ; PIX_SORT(p[5], p[8]) ; PIX_SORT(p[4], p[7]) ;
+    PIX_SORT(p[3], p[6]) ; PIX_SORT(p[1], p[4]) ; PIX_SORT(p[2], p[5]) ;
+    PIX_SORT(p[4], p[7]) ; PIX_SORT(p[4], p[2]) ; PIX_SORT(p[6], p[4]) ;
+    PIX_SORT(p[4], p[2]) ;
+    return p[4];
+#undef PIX_SORT
+#undef PIX_SWAP
+}
+
+// return MCU temperature (degrees of celsius * 10)
+int32_t getMCUtemp(){
+    // Temp = (V25 - Vsense)/Avg_Slope + 25
+    // V_25 = 1.45V,  Slope = 4.3e-3
+    int32_t Vsense = getVdd() * getADCval(1);
+    int32_t temperature = 593920 - Vsense; // 593920 == 145*4096
+    temperature /= 172; // == /(4096*10*4.3e-3), 10 - to convert from *100 to *10
+    temperature += 250;
+    return(temperature);
+}
+
+// return Vdd * 100 (V)
+uint32_t getVdd(){
+    uint32_t vdd = 120 * 4096; // 1.2V
+    vdd /= getADCval(2);
+    return vdd;
+}
+
+/**
+ * @brief chkADCtrigger - check ADC trigger state
+ * @return value of `triggered`
+ */
+uint8_t chkADCtrigger(){
+    static uint8_t triggered = 0;
+    savetrigtime();
+    int16_t val = getADCval(0);
+    if(triggered){ // check untriggered action
+        if(val < (int16_t)the_conf.ADC_min - ADC_THRESHOLD || val > (int16_t)the_conf.ADC_max + ADC_THRESHOLD){
+            triggered = 0;
+        }
+    }else{ // check if thigger shot
+        if(val > (int16_t)the_conf.ADC_min + ADC_THRESHOLD && val < (int16_t)the_conf.ADC_max - ADC_THRESHOLD){
+            triggered = 1;
+            fillshotms(ADC_TRIGGER);
+        }
+    }
+    return triggered;
+}

F1-nolib/chronometer_v1/src_new/adc.h

@@ -0,0 +1,35 @@
+/*
+ * This file is part of the chronometer project.
+ * Copyright 2018 Edward V. Emelianov <edward.emelianoff@gmail.com>.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef ADC_H
+#define ADC_H
+#include "stm32f1.h"
+
+#define NUMBER_OF_ADC_CHANNELS (3)
+
+// interval of trigger's shot (>min && <max), maybe negative
+#define ADC_MIN_VAL     (1024)
+#define ADC_MAX_VAL     (3072)
+// 2*ADC_THRESHOLD = hysteresis width
+#define ADC_THRESHOLD   (50)
+
+extern uint16_t ADC_array[];
+int32_t getMCUtemp();
+uint32_t getVdd();
+uint16_t getADCval(int nch);
+uint8_t chkADCtrigger();
+#endif // ADC_H

F1-nolib/chronometer_v1/src_new/flash.c

@@ -0,0 +1,321 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * flash.c
+ *
+ * Copyright 2017 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+/**
+  ATTENTION!!
+  This things works only if you will add next section:
+
+    .myvars :
+    {
+     . = ALIGN(1024);
+     KEEP(*(.myvars))
+    } > rom
+
+  after section .data
+*/
+
+#include "stm32f1.h"
+
+#include "adc.h"
+#include "flash.h"
+#include "lidar.h"
+#include "str.h"
+#include "usart.h"  // DBG
+#include "usb.h"    // printout
+#include <string.h> // memcpy
+
+// max amount of records stored: Config & Logs
+int maxCnum = FLASH_BLOCK_SIZE / sizeof(user_conf);
+int maxLnum = FLASH_BLOCK_SIZE / sizeof(user_conf);
+
+// common structure for all datatypes stored
+/*typedef struct {
+    uint16_t userconf_sz;
+} flash_storage;*/
+
+#define USERCONF_INITIALIZER  {             \
+/*    .magick = 0xAB, */                    \
+    .userconf_sz = sizeof(user_conf)        \
+    ,.dist_min = LIDAR_MIN_DIST             \
+    ,.dist_max = LIDAR_MAX_DIST             \
+    ,.trigstate = 0                         \
+    ,.trigpause = {400, 400, 400, 300, 300} \
+    ,.ADC_min = ADC_MIN_VAL                 \
+    ,.ADC_max = ADC_MAX_VAL                 \
+    ,.USART_speed = USART1_DEFAULT_SPEED    \
+    ,.defflags = 0                          \
+    ,.NLfreeWarn = 100                      \
+    }
+
+// change to placement
+/*
+__attribute__ ((section(".logs"))) const uint32_t *logsstart;
+__attribute__ ((section(".myvars"))) const user_conf *Flash_Data;
+*/
+
+static int erase_flash(const void*, const void*);
+static int write2flash(const void*, const void*, int);
+
+const user_conf *Flash_Data = (const user_conf *)&__varsstart;
+const event_log *logsstart = (event_log*) &__logsstart;
+
+user_conf the_conf = USERCONF_INITIALIZER;
+
+static int currentconfidx = -1; // index of current configuration
+static int currentlogidx = -1; // index of current logs record
+
+/**
+ * @brief binarySearch - binary search in flash for last non-empty cell
+ *          any struct searched should have its sizeof() @ the first field!!!
+ * @param l - left index
+ * @param r - right index (should be @1 less than last index!)
+ * @param start - starting address
+ * @param stor_size - size of structure to search
+ * @return index of non-empty cell or -1
+ */
+static int binarySearch(int l, int r, uint8_t *start, int stor_size){
+/*DBG("start: "); printuhex(1, (uint32_t)start);
+DBG("\nsizeof: "); printu(1, stor_size);
+newline();*/
+    while(r >= l){
+        int mid = l + (r - l) / 2;
+        uint8_t *s = start + mid * stor_size;
+        if(*((uint16_t*)s) == stor_size){
+            if(*((uint16_t*)(s + stor_size)) == 0xffff){
+                return mid;
+            }else{ // element is to the right
+                l = mid + 1;
+            }
+        }else{ // element is to the left
+            r = mid - 1;
+        }
+    }
+    return -1; // not found
+}
+
+/**
+ * @brief flashstorage_init - initialization of user conf & logs storage
+ * run in once @ start
+ */
+void flashstorage_init(){
+    maxCnum = ((uint32_t)&_varslen) / sizeof(user_conf);
+//SEND("maxCnum="); printu(1, maxCnum);
+    if(FLASH_SIZE > 0 && FLASH_SIZE < 20000){
+        uint32_t flsz = FLASH_SIZE * 1024; // size in bytes
+        flsz -= (uint32_t)logsstart - FLASH_BASE;
+        maxLnum = flsz / sizeof(event_log);
+//SEND("\nmaxLnum="); printu(1, maxLnum);
+    }
+    // -1 if there's no data at all & flash is clear; maxnum-1 if flash is full
+    currentconfidx = binarySearch(0, maxCnum-2, (uint8_t*)Flash_Data, sizeof(user_conf));
+    if(currentconfidx > -1){
+        memcpy(&the_conf, &Flash_Data[currentconfidx], sizeof(user_conf));
+    }
+    currentlogidx = binarySearch(0, maxLnum-2, (uint8_t*)logsstart, sizeof(event_log));
+}
+
+// store new configuration
+// @return 0 if all OK
+int store_userconf(){
+    // maxnum - 3 means that there always should be at least one empty record after last data
+    // for binarySearch() checking that there's nothing more after it!
+    if(currentconfidx > maxCnum - 3){ // there's no more place
+        currentconfidx = 0;
+        DBG("Need to erase flash!");
+        if(erase_flash(Flash_Data, logsstart)) return 1;
+    }else ++currentconfidx; // take next data position (0 - within first run after firmware flashing)
+    return write2flash(&Flash_Data[currentconfidx], &the_conf, sizeof(the_conf));
+}
+
+/**
+ * @brief store_log - save log record L into flash memory
+ * @param L - event log (or NULL to delete flash)
+ * @return 0 if all OK
+ */
+int store_log(event_log *L){
+    if(!L){
+        currentlogidx = -1;
+        return erase_flash(logsstart, NULL);
+    }
+    if(currentlogidx > maxLnum - 3){ // there's no more place
+        /*currentlogidx = 0;
+        DBG("Need to erase flash!");
+        if(erase_flash(logsstart, NULL)) return 1;*/
+        // prevent automatic logs erasing!
+        USB_send("\n\nERROR!\nCan't save logs: delete old manually!!!\n");
+        return 1;
+    }else ++currentlogidx; // take next data position (0 - within first run after firmware flashing)
+    // put warning if there's little space
+    if(currentlogidx + the_conf.NLfreeWarn > maxLnum - 3){
+        uint32_t nfree = maxLnum - 2 - currentlogidx;
+        USB_send("\n\nWARNING!\nCan store only ");
+        USB_send(u2str(nfree));
+        USB_send(" logs!\n\n");
+    }
+/*
+USB_send("Stored #"); USB_send(u2str(currentlogidx));
+USB_send(", max="); USB_send(u2str(maxLnum));
+USB_send(", warn="); USB_send(u2str(the_conf.NLfreeWarn));
+USB_send("\n");
+*/
+    return write2flash(&logsstart[currentlogidx], L, sizeof(event_log));
+}
+
+/**
+ * @brief dump_log - dump N log records
+ * @param start - first record to show (if start<0, then first=last+start)
+ * @param Nlogs - amount of logs to show (if Nlogs<=0, then show all logs)
+ * @return 0 if all OK, 1 if there's no logs in flash
+ */
+int dump_log(int start, int Nlogs){
+    if(currentlogidx < 0) return 1;
+    if(start < 0){
+        start += currentlogidx + 1;
+        if(start < 0) start = 0;
+    }
+    if(start > currentlogidx) return 1;
+    int nlast;
+    if(Nlogs > 0){
+        nlast = start + Nlogs - 1;
+        if(nlast > currentlogidx) nlast = currentlogidx;
+    }else nlast = currentlogidx;
+    ++nlast;
+    const event_log *l = logsstart + start;
+    for(int i = start; i < nlast; ++i, ++l){
+        IWDG->KR = IWDG_REFRESH;
+        USB_send(get_trigger_shot(i, l));
+    }
+    return 0;
+}
+
+static int write2flash(const void *start, const void *wrdata, int stor_size){
+    int ret = 0;
+    if (FLASH->CR & FLASH_CR_LOCK){ // unloch flash
+        FLASH->KEYR = FLASH_KEY1;
+        FLASH->KEYR = FLASH_KEY2;
+    }
+    while (FLASH->SR & FLASH_SR_BSY);
+    if(FLASH->SR & FLASH_SR_WRPRTERR) return 1; // write protection
+    FLASH->SR = FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPRTERR; // clear all flags
+    FLASH->CR |= FLASH_CR_PG;
+    uint16_t *data = (uint16_t*) wrdata;
+    uint16_t *address = (uint16_t*) start;
+    uint32_t i, count = (stor_size + 1) / 2;
+    for (i = 0; i < count; ++i){
+        IWDG->KR = IWDG_REFRESH;
+        *(volatile uint16_t*)(address + i) = data[i];
+        while (FLASH->SR & FLASH_SR_BSY);
+        if(FLASH->SR &  FLASH_SR_PGERR) ret = 1; // program error - meet not 0xffff
+        else while (!(FLASH->SR & FLASH_SR_EOP));
+        FLASH->SR = FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPRTERR;
+    }
+    FLASH->CR &= ~(FLASH_CR_PG);
+    return ret;
+}
+
+/**
+ * @brief erase_flash - erase N pages of flash memory
+ * @param start  - first address
+ * @param end    - last address (or NULL if need to erase all flash remaining)
+ * @return 0 if succeed
+ */
+static int erase_flash(const void *start, const void *end){
+    int ret = 0;
+    uint32_t nblocks = 1, flsz = 0;
+    if(!end){ // erase all remaining
+        if(FLASH_SIZE > 0 && FLASH_SIZE < 20000){
+            flsz = FLASH_SIZE * 1024; // size in bytes
+            flsz -= (uint32_t)start - FLASH_BASE;
+        }
+    }else{ // erase a part
+        flsz = (uint32_t)end - (uint32_t)start;
+    }
+    nblocks = flsz / FLASH_BLOCK_SIZE;
+    if(nblocks == 0 || nblocks >= FLASH_SIZE) return 1;
+    for(uint32_t i = 0; i < nblocks; ++i){
+#ifdef EBUG
+        SEND("Try to erase page #"); printu(1,i); newline();
+#endif
+        IWDG->KR = IWDG_REFRESH;
+        /* (1) Wait till no operation is on going */
+        /* (2) Clear error & EOP bits */
+        /* (3) Check that the Flash is unlocked */
+        /* (4) Perform unlock sequence */
+        while ((FLASH->SR & FLASH_SR_BSY) != 0){} /* (1) */
+        FLASH->SR = FLASH_SR_EOP | FLASH_SR_PGERR | FLASH_SR_WRPRTERR;  /* (2) */
+      /*  if (FLASH->SR & FLASH_SR_EOP){
+            FLASH->SR |= FLASH_SR_EOP;
+        }*/
+        if ((FLASH->CR & FLASH_CR_LOCK) != 0){ /* (3) */
+            FLASH->KEYR = FLASH_KEY1; /* (4) */
+            FLASH->KEYR = FLASH_KEY2;
+        }
+        /* (1) Set the PER bit in the FLASH_CR register to enable page erasing */
+        /* (2) Program the FLASH_AR register to select a page to erase */
+        /* (3) Set the STRT bit in the FLASH_CR register to start the erasing */
+        /* (4) Wait until the  EOP flag in the FLASH_SR register set */
+        /* (5) Clear EOP flag by software by writing EOP at 1 */
+        /* (6) Reset the PER Bit to disable the page erase */
+        FLASH->CR |= FLASH_CR_PER; /* (1) */
+        FLASH->AR = (uint32_t)Flash_Data + i*FLASH_BLOCK_SIZE; /* (2) */
+        FLASH->CR |= FLASH_CR_STRT; /* (3) */
+        while(!(FLASH->SR & FLASH_SR_EOP));
+        FLASH->SR |= FLASH_SR_EOP; /* (5)*/
+        if(FLASH->SR & FLASH_SR_WRPRTERR){ /* Check Write protection error */
+            ret = 1;
+            DBG("Write protection error!");
+            FLASH->SR |= FLASH_SR_WRPRTERR; /* Clear the flag by software by writing it at 1*/
+            break;
+        }
+        FLASH->CR &= ~FLASH_CR_PER; /* (6) */
+    }
+    return ret;
+}
+
+#ifdef EBUG
+void dump_userconf(){
+    SEND("userconf_sz="); printu(1, the_conf.userconf_sz);
+    SEND("\ndist_min="); printu(1, the_conf.dist_min);
+    SEND("\ndist_max="); printu(1, the_conf.dist_max);
+    SEND("\ntrigstate="); printuhex(1, the_conf.trigstate);
+    SEND("\ntrigpause={");
+    for(int i = 0; i < TRIGGERS_AMOUNT; ++i){
+        if(i) SEND(", ");
+        printu(1, the_conf.trigpause[i]);
+    }
+    SEND("}\n");
+    transmit_tbuf(1);
+}
+
+void addNrecs(int N){
+    SEND("Try to store userconf for "); printu(1, N); SEND(" times\n");
+    for(int i = 0; i < N; ++i){
+        if(store_userconf()){
+            SEND("Error @ "); printu(1, i); newline();
+            return;
+        }
+    }
+    SEND("Curr idx: "); printu(1, currentconfidx); newline();
+}
+
+#endif

F1-nolib/chronometer_v1/src_new/flash.h

@@ -0,0 +1,88 @@
+/*
+ * flash.h
+ *
+ * Copyright 2017 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#pragma once
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+#include <stm32f1.h>
+#include "hardware.h"
+
+#define FLASH_BLOCK_SIZE    (1024)
+#define FLASH_SIZE_REG      ((uint32_t)0x1FFFF7E0)
+#define FLASH_SIZE          *((uint16_t*)FLASH_SIZE_REG)
+
+/*
+ * struct to save user configurations
+ */
+typedef struct __attribute__((packed, aligned(4))){
+    uint16_t userconf_sz;       // "magick number"
+    uint16_t NLfreeWarn;        // warn user when there's less free log records than NLfreeWarn
+    int16_t  ADC_min;           // min&max values of ADC (shot when ADval > ADC_min && < ADC_max)
+    int16_t  ADC_max;           // !!! BOTH ARE SIGNED! so you can include 0 & 4096
+    uint8_t  trigstate;         // level in `triggered` state
+    uint8_t  defflags;          // default flags
+    uint32_t dist_min;          // minimal distance for LIDAR
+    uint32_t dist_max;          // maximal -//-
+    uint32_t USART_speed;       // USART1 speed (115200 by default)
+    int32_t  trigpause[TRIGGERS_AMOUNT]; // pause (ms) for false shots
+} user_conf;
+
+// values for user_conf.defflags:
+// save events in flash
+#define FLAG_SAVE_EVENTS        (1 << 0)
+// strings ends with "\r\n" instead of normal "\n"
+#define FLAG_STRENDRN           (1 << 1)
+// proxy GPS messages over USART1
+#define FLAG_GPSPROXY           (1 << 2)
+
+
+/*
+ * struct to save events logs
+ */
+typedef struct __attribute__((packed, aligned(4))){
+    uint16_t elog_sz;
+    uint8_t trigno;
+    trigtime shottime;
+    int16_t triglen;
+    uint16_t lidar_dist;
+} event_log;
+
+extern user_conf the_conf;
+extern const user_conf *Flash_Data;
+extern const event_log *logsstart;
+extern int maxCnum, maxLnum;
+// data from ld-file
+extern uint32_t _varslen, __varsstart, __logsstart;
+
+
+void flashstorage_init();
+int store_userconf();
+int store_log(event_log *L);
+int dump_log(int start, int Nlogs);
+
+#ifdef EBUG
+void dump_userconf();
+void addNrecs(int N);
+#endif
+
+#endif // __FLASH_H__

F1-nolib/chronometer_v1/src_new/hardware.c

@@ -0,0 +1,252 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * hardware.c - hardware-dependent macros & functions
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+
+#include "adc.h"
+#include "hardware.h"
+#include "flash.h"
+#include "lidar.h"
+#include "str.h"
+#include "time.h"
+#include "usart.h"
+
+#include <string.h> // memcpy
+
+uint8_t buzzer_on = 1; // buzzer ON by default
+uint8_t LEDSon = 1; // LEDS are working
+// ports of triggers
+static GPIO_TypeDef *trigport[DIGTRIG_AMOUNT] = {GPIOA, GPIOA, GPIOA};
+// pins of triggers: PA13, PA14, PA4
+static uint16_t trigpin[DIGTRIG_AMOUNT] = {1<<13, 1<<14, 1<<4};
+// value of pin in `triggered` state
+static uint8_t trigstate[DIGTRIG_AMOUNT];
+// time of triggers shot
+trigtime shottime[TRIGGERS_AMOUNT];
+// Tms value when they shot
+uint32_t shotms[TRIGGERS_AMOUNT];
+// trigger length (-1 if > MAX_TRIG_LEN)
+int16_t triglen[TRIGGERS_AMOUNT];
+// if trigger[N] shots, the bit N will be 1
+uint8_t trigger_shot = 0;
+
+static inline void gpio_setup(){
+    BUZZER_OFF(); // turn off buzzer @start
+    LED_on(); // turn ON LED0 @start
+    LED1_off(); // turn off LED1 @start
+    USBPU_OFF(); // turn off USB pullup @start
+    // Enable clocks to the GPIO subsystems (PB for ADC), turn on AFIO clocking to disable SWD/JTAG
+    RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
+    // turn off SWJ/JTAG
+    AFIO->MAPR = AFIO_MAPR_SWJ_CFG_DISABLE;
+    // pullups: PA1 - PPS, PA15 - USB pullup
+    GPIOA->ODR = (1<<12)|(1<<15);
+    // buzzer (PC13): pushpull output
+    GPIOC->CRH = CRH(13, CNF_PPOUTPUT|MODE_SLOW);
+    // Set leds (PB8) as opendrain output
+    GPIOB->CRH = CRH(8, CNF_ODOUTPUT|MODE_SLOW) | CRH(9, CNF_ODOUTPUT|MODE_SLOW);
+    // PPS pin (PA1) - input with weak pullup
+    GPIOA->CRL = CRL(1, CNF_PUDINPUT|MODE_INPUT);
+    // Set USB pullup (PA15) - opendrain output
+    GPIOA->CRH = CRH(15, CNF_ODOUTPUT|MODE_SLOW);
+    // ---------------------> config-depengent block, interrupts & pullup inputs:
+    GPIOA->CRH |= CRH(13, CNF_PUDINPUT|MODE_INPUT) | CRH(14, CNF_PUDINPUT|MODE_INPUT);
+    GPIOA->CRL |= CRL(4, CNF_PUDINPUT|MODE_INPUT);
+    // <---------------------
+    // EXTI: all three EXTI are on PA -> AFIO_EXTICRx = 0
+    // interrupt on pulse front: buttons - 1->0, PPS - 0->1
+    EXTI->IMR = EXTI_IMR_MR1;
+    EXTI->RTSR = EXTI_RTSR_TR1; // rising trigger
+    // PA4/PA13/PA14 - buttons
+    for(int i = 0; i < DIGTRIG_AMOUNT; ++i){
+        uint16_t pin = trigpin[i];
+        // fill trigstate array
+        uint8_t trgs = (the_conf.trigstate & (1<<i)) ? 1 : 0;
+        trigstate[i] = trgs;
+        trigport[i]->ODR |= pin; // turn on pullups
+        EXTI->IMR |= pin;
+        if(trgs){ // triggered @1 -> rising interrupt
+            EXTI->RTSR |= pin;
+        }else{ // falling interrupt
+            EXTI->FTSR |= pin;
+        }
+    }
+    // ---------------------> config-depengent block, interrupts & pullup inputs:
+    // !!! change AFIO_EXTICRx if some triggers not @GPIOA
+    NVIC_EnableIRQ(EXTI4_IRQn);
+    NVIC_EnableIRQ(EXTI15_10_IRQn);
+    // <---------------------
+    NVIC_EnableIRQ(EXTI1_IRQn);
+}
+
+static inline void adc_setup(){
+    GPIOB->CRL |= CRL(0, CNF_ANALOG|MODE_INPUT);
+    uint32_t ctr = 0;
+    // Enable clocking
+    RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
+    RCC->CFGR &= ~(RCC_CFGR_ADCPRE);
+    RCC->CFGR |= RCC_CFGR_ADCPRE_DIV8; // ADC clock = RCC / 8
+    // sampling time - 239.5 cycles for channels 8, 16 and 17
+    ADC1->SMPR2 = ADC_SMPR2_SMP8;
+    ADC1->SMPR1 = ADC_SMPR1_SMP16 | ADC_SMPR1_SMP17;
+    // we have three conversions in group -> ADC1->SQR1[L] = 2, order: 8->16->17
+    ADC1->SQR3 = 8 | (16<<5) | (17<<10);
+    ADC1->SQR1 = ADC_SQR1_L_1;
+    ADC1->CR1 |= ADC_CR1_SCAN; // scan mode
+    // DMA configuration
+    RCC->AHBENR |= RCC_AHBENR_DMA1EN;
+    DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR));
+    DMA1_Channel1->CMAR = (uint32_t)(ADC_array);
+    DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNELS * 9;
+    DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
+                          | DMA_CCR_CIRC | DMA_CCR_PL | DMA_CCR_EN;
+    // continuous mode & DMA; enable vref & Tsens; wake up ADC
+    ADC1->CR2 |= ADC_CR2_DMA | ADC_CR2_TSVREFE | ADC_CR2_CONT | ADC_CR2_ADON;
+    // wait for Tstab - at least 1us
+    while(++ctr < 0xff) nop();
+    // calibration
+    ADC1->CR2 |= ADC_CR2_RSTCAL;
+    ctr = 0; while((ADC1->CR2 & ADC_CR2_RSTCAL) && ++ctr < 0xfffff);
+    ADC1->CR2 |= ADC_CR2_CAL;
+    ctr = 0; while((ADC1->CR2 & ADC_CR2_CAL) && ++ctr < 0xfffff);
+    // turn ON ADC
+    ADC1->CR2 |= ADC_CR2_ADON;
+}
+
+void hw_setup(){
+    gpio_setup();
+    adc_setup();
+}
+
+void exti1_isr(){ // PPS - PA1
+    systick_correction();
+    LED_off(); // turn off LED0 @ each PPS
+    EXTI->PR = EXTI_PR_PR1;
+}
+
+static trigtime trgtm;
+void savetrigtime(){
+    trgtm.millis = Timer;
+    memcpy(&trgtm.Time, &current_time, sizeof(curtime));
+}
+
+/**
+ * @brief fillshotms - save trigger shot time
+ * @param i - trigger number
+ */
+void fillshotms(int i){
+    if(i < 0 || i >= TRIGGERS_AMOUNT) return;
+    if(Tms - shotms[i] > (uint32_t)the_conf.trigpause[i] || i == LIDAR_TRIGGER){
+        memcpy(&shottime[i], &trgtm, sizeof(trigtime));
+        shotms[i] = Tms;
+        trigger_shot |= 1<<i;
+        BUZZER_ON();
+    }
+}
+
+/**
+ * @brief fillunshotms - calculate trigger length time
+ */
+void fillunshotms(){
+    if(!trigger_shot) return;
+    uint8_t X = 1;
+    for(int i = 0; i < TRIGGERS_AMOUNT; ++i, X<<=1){
+        IWDG->KR = IWDG_REFRESH;
+        // check whether trigger is OFF but shot recently
+        if(trigger_shot & X){
+            uint32_t len = Tms - shotms[i];
+            uint8_t rdy = 0;
+            if(len > MAX_TRIG_LEN){
+                triglen[i] = -1;
+                rdy = 1;
+            }else triglen[i] = (uint16_t) len;
+            if(i == LIDAR_TRIGGER){
+                if(!parse_lidar_data(NULL)) rdy = 1;
+            }else if(i == ADC_TRIGGER){
+                if(!chkADCtrigger()) rdy = 1;
+            }else{
+                uint8_t pinval = (trigport[i]->IDR & trigpin[i]) ? 1 : 0;
+                if(pinval != trigstate[i]) rdy = 1; // trigger is OFF
+            }
+            if(rdy){
+                if(i != LIDAR_TRIGGER) shotms[i] = Tms;
+                show_trigger_shot(X);
+                trigger_shot &= ~X;
+            }
+        }
+    }
+}
+
+void exti4_isr(){ // PA4 - trigger[2]
+    savetrigtime();
+    fillshotms(2);
+    EXTI->PR = EXTI_PR_PR4;
+}
+
+void exti15_10_isr(){ // PA13 - trigger[0], PA14 - trigger[1]
+    savetrigtime();
+    if(EXTI->PR & EXTI_PR_PR13){
+        fillshotms(0);
+        EXTI->PR = EXTI_PR_PR13;
+    }
+    if(EXTI->PR & EXTI_PR_PR14){
+        fillshotms(1);
+        EXTI->PR = EXTI_PR_PR14;
+    }
+}
+
+#ifdef EBUG
+/**
+ * @brief gettrig - get trigger state
+ * @return 1 if trigger active or 0
+ */
+uint8_t gettrig(uint8_t N){
+    if(N >= TRIGGERS_AMOUNT) return 0;
+    uint8_t curval = (trigport[N]->IDR & trigpin[N]) ? 1 : 0;
+    if(curval == trigstate[N]) return 1;
+    else return 0;
+}
+#endif
+
+void chk_buzzer(){
+    static uint32_t Ton = 0; // Time of first buzzer check
+    if(!BUZZER_GET()) return; // buzzer if OFF
+    if(!trigger_shot){ // should we turn off buzzer?
+        uint8_t notrg = 1;
+        for(int i = 0; i < DIGTRIG_AMOUNT; ++i){
+            uint8_t curval = (trigport[i]->IDR & trigpin[i]) ? 1 : 0;
+            if(curval == trigstate[i]){
+                notrg = 0; // cheep while digital trigger is ON
+                break;
+            }
+        }
+        if(notrg){ // turn off buzzer when there's no trigger events & timeout came
+            if(Tms - Ton < BUZZER_CHEEP_TIME) return;
+            Ton = 0;
+            BUZZER_OFF();
+        }
+    }else{ // buzzer is ON - check timer
+        if(Ton == 0){
+            Ton = Tms;
+            if(!Ton) Ton = 1;
+        }
+    }
+}

F1-nolib/chronometer_v1/src_new/hardware.h

@@ -0,0 +1,104 @@
+/*
+ *                                                                                                  geany_encoding=koi8-r
+ * hardware.h
+ *
+ * Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ */
+#pragma once
+#ifndef __HARDWARE_H__
+#define __HARDWARE_H__
+
+#include "stm32f1.h"
+#include "time.h"
+
+// onboard LEDs - PB8/PB9
+#define LED0_port   GPIOB
+#define LED0_pin    (1<<8)
+#define LED1_port   GPIOB
+#define LED1_pin    (1<<9)
+
+// buzzer (1 - active) - PC13
+extern uint8_t buzzer_on;
+#define BUZZER_port GPIOC
+#define BUZZER_pin  (1<<13)
+#define BUZZER_ON() do{if(buzzer_on)pin_set(BUZZER_port, BUZZER_pin);}while(0)
+#define BUZZER_OFF() pin_clear(BUZZER_port, BUZZER_pin)
+#define BUZZER_GET() (pin_read(BUZZER_port, BUZZER_pin))
+// minimal time to buzzer to cheep (ms)
+#define BUZZER_CHEEP_TIME   500
+
+// PPS pin - PA1
+#define PPS_port    GPIOA
+#define PPS_pin     (1<<1)
+
+// PPS and triggers state
+// amount of triggers, should be less than 9; 5 - 0..2 - switches, 3 - LIDAR, 4 - ADC
+#define TRIGGERS_AMOUNT     5
+// number of LIDAR trigger
+#define LIDAR_TRIGGER       3
+// number of ADC trigger
+#define ADC_TRIGGER         4
+// amount of digital triggers (on interrupts)
+#define DIGTRIG_AMOUNT      3
+// max length of trigger event (ms)
+#define MAX_TRIG_LEN        1000
+
+#ifdef EBUG
+uint8_t gettrig(uint8_t N);
+#endif
+void fillshotms(int i);
+void fillunshotms();
+void savetrigtime();
+#define GET_PPS()       ((GPIOA->IDR & (1<<1)) ? 1 : 0)
+
+// USB pullup - PA15
+#define USBPU_port  GPIOA
+#define USBPU_pin   (1<<15)
+#define USBPU_ON()  pin_clear(USBPU_port, USBPU_pin)
+#define USBPU_OFF() pin_set(USBPU_port, USBPU_pin)
+
+#define LED_blink()    do{if(LEDSon)pin_toggle(LED0_port, LED0_pin);}while(0)
+#define LED_on()       do{if(LEDSon)pin_clear(LED0_port, LED0_pin);}while(0)
+#define LED_off()      do{pin_set(LED0_port, LED0_pin);}while(0)
+#define LED1_blink()   do{if(LEDSon)pin_toggle(LED1_port, LED1_pin);}while(0)
+#define LED1_on()      do{if(LEDSon)pin_clear(LED1_port, LED1_pin);}while(0)
+#define LED1_off()     do{pin_set(LED1_port, LED1_pin);}while(0)
+
+// GPS USART == USART2, LIDAR USART == USART3
+#define GPS_USART   (2)
+#define LIDAR_USART (3)
+
+typedef struct{
+    uint32_t millis;
+    curtime Time;
+} trigtime;
+
+// turn on/off LEDs:
+extern uint8_t LEDSon;
+// time of triggers shot
+extern trigtime shottime[TRIGGERS_AMOUNT];
+// length (in ms) of trigger event (-1 if > MAX_TRIG_LEN
+extern int16_t triglen[TRIGGERS_AMOUNT];
+// if trigger[N] shots, the bit N will be 1
+extern uint8_t trigger_shot;
+
+void chk_buzzer();
+void hw_setup();
+
+#endif // __HARDWARE_H__

F1-nolib/chronometer_v1/src_new/lidar.c

@@ -0,0 +1,81 @@
+/*
+ * This file is part of the chronometer project.
+ * Copyright 2019 Edward V. Emelianov <edward.emelianoff@gmail.com>.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "flash.h"
+#include "lidar.h"
+#include "usart.h"
+
+uint16_t last_lidar_dist = 0;
+uint16_t last_lidar_stren = 0;
+uint16_t lidar_triggered_dist = 0;
+
+extern uint32_t shotms[];
+
+/**
+ * @brief parse_lidar_data - parsing of string from lidar
+ * @param txt - the string or NULL (if you want just check trigger state)
+ * @return trigger state
+ */
+uint8_t parse_lidar_data(char *txt){
+    static uint8_t triggered = 0;
+    if(!txt){
+        // clear trigger state after timeout -> need to monitor lidar
+        uint32_t len = Tms - shotms[LIDAR_TRIGGER];
+        //if(len > MAX_TRIG_LEN || len > (uint32_t)the_conf.trigpause[LIDAR_TRIGGER]){
+        if(len > MAX_TRIG_LEN){
+            triggered = 0;
+            DBG("MAX time gone, untrigger!");
+        }
+        return triggered;
+    }
+    last_lidar_dist = txt[2] | (txt[3] << 8);
+    last_lidar_stren = txt[4] | (txt[5] << 8);
+    if(last_lidar_stren < LIDAR_LOWER_STREN) return 0; // weak signal
+    if(!lidar_triggered_dist){ // first run
+        lidar_triggered_dist = last_lidar_dist;
+        return 0;
+    }
+    IWDG->KR = IWDG_REFRESH;
+    if(triggered){ // check if body gone
+        if(last_lidar_dist < the_conf.dist_min || last_lidar_dist > the_conf.dist_max || last_lidar_dist > lidar_triggered_dist + LIDAR_DIST_THRES){
+            triggered = 0;
+#ifdef EBUG
+            SEND("Untriggered! distance=");
+            printu(1, last_lidar_dist);
+            SEND(" signal=");
+            printu(1, last_lidar_stren);
+            newline();
+#endif
+        }
+    }else{
+        if(last_lidar_dist > the_conf.dist_min && last_lidar_dist < the_conf.dist_max){
+            savetrigtime();
+            triggered = 1;
+            lidar_triggered_dist = last_lidar_dist;
+            fillshotms(LIDAR_TRIGGER);
+#ifdef EBUG
+            SEND("Triggered! distance=");
+            printu(1, last_lidar_dist);
+            SEND(" signal=");
+            printu(1, last_lidar_stren);
+            newline();
+#endif
+        }
+    }
+    return triggered;
+}

F1-nolib/chronometer_v1/src_new/lidar.h

@@ -0,0 +1,39 @@
+/*
+ * This file is part of the chronometer project.
+ * Copyright 2019 Edward V. Emelianov <edward.emelianoff@gmail.com>.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#ifndef LIDAR_H__
+#define LIDAR_H__
+#include <stm32f1.h>
+
+#define LIDAR_FRAME_LEN     (9)
+// frame header
+#define LIDAR_FRAME_HEADER  (0x59)
+// lower strength limit
+#define LIDAR_LOWER_STREN   (10)
+// triggered distance threshold - 1 meter
+#define LIDAR_DIST_THRES    (100)
+#define LIDAR_MIN_DIST      (50)
+#define LIDAR_MAX_DIST      (1000)
+
+extern uint16_t last_lidar_dist;
+extern uint16_t lidar_triggered_dist;
+extern uint16_t last_lidar_stren;
+
+uint8_t parse_lidar_data(char *txt);
+
+#endif // LIDAR_H__

F1-nolib/chronometer_v1/src_new/main.c

@@ -0,0 +1,374 @@
+/*
+ * main.c
+ *
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include "adc.h"
+#include "GPS.h"
+#include "flash.h"
+#include "hardware.h"
+#include "lidar.h"
+#include "str.h"
+#include "time.h"
+#include "usart.h"
+#include "usb.h"
+#include "usb_lib.h"
+
+#ifndef VERSION
+#define VERSION "0.0.0"
+#endif
+
+// global pseudo-milliseconds counter
+volatile uint32_t Tms = 0;
+
+/* Called when systick fires */
+void sys_tick_handler(void){
+    ++Tms; // increment pseudo-milliseconds counter
+    if(++Timer == 1000){ // increment milliseconds counter
+        time_increment();
+    }
+}
+
+void iwdg_setup(){
+    uint32_t tmout = 16000000;
+    /* Enable the peripheral clock RTC */
+    /* (1) Enable the LSI (40kHz) */
+    /* (2) Wait while it is not ready */
+    RCC->CSR |= RCC_CSR_LSION; /* (1) */
+    while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
+    /* Configure IWDG */
+    /* (1) Activate IWDG (not needed if done in option bytes) */
+    /* (2) Enable write access to IWDG registers */
+    /* (3) Set prescaler by 64 (1.6ms for each tick) */
+    /* (4) Set reload value to have a rollover each 2s */
+    /* (5) Check if flags are reset */
+    /* (6) Refresh counter */
+    IWDG->KR = IWDG_START; /* (1) */
+    IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
+    IWDG->PR = IWDG_PR_PR_1; /* (3) */
+    IWDG->RLR = 1250; /* (4) */
+    tmout = 16000000;
+    while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
+    IWDG->KR = IWDG_REFRESH; /* (6) */
+}
+
+#ifdef EBUG
+char *parse_cmd(char *buf){
+    int32_t N;
+    static char btns[] = "BTN0=0, BTN1=0, BTN2=0, PPS=0\n";
+    event_log l = {.elog_sz = sizeof(event_log), .trigno = 2};
+    switch(*buf){
+        case '0':
+            LED_off(); // LED0 off @dbg
+        break;
+        case '1':
+            LED_on(); // LED0 on @dbg
+        break;
+        case 'a':
+            l.shottime.Time = current_time;
+            l.shottime.millis = Timer;
+            l.triglen = getADCval(1);
+            if(store_log(&l)) SEND("Error storing");
+            else SEND("Store OK");
+            newline();
+        break;
+        case 'b':
+            btns[5] = gettrig(0) + '0';
+            btns[13] = gettrig(1) + '0';
+            btns[21] = gettrig(2) + '0';
+            btns[28] = GET_PPS() + '0';
+            return btns;
+        break;
+        case 'c':
+            DBG("Send cold start");
+            GPS_send_FullColdStart();
+        break;
+        case 'C':
+            if(getnum(&buf[1], &N)){
+                SEND("Need a number!\n");
+            }else{
+                addNrecs(N);
+            }
+        break;
+        case 'd':
+            dump_userconf();
+        break;
+        case 'D':
+            if(dump_log(0, -1)) DBG("Error dumping log: empty?");
+        break;
+        case 'p':
+            pin_toggle(USBPU_port, USBPU_pin);
+            SEND("USB pullup is ");
+            if(pin_read(USBPU_port, USBPU_pin)) SEND("off");
+            else SEND("on");
+            newline();
+        break;
+        case 'G':
+            SEND("LIDAR_DIST=");
+            printu(1, last_lidar_dist);
+            SEND(", LIDAR_STREN=");
+            printu(1, last_lidar_stren);
+            newline();
+        break;
+        case 'L':
+            USB_send("Very long test string for USB (it's length is more than 64 bytes).\n"
+                     "This is another part of the string! Can you see all of this?\n");
+            return "Long test sent\n";
+        break;
+        case 'R':
+            USB_send("Soft reset\n");
+            SEND("Soft reset\n");
+            NVIC_SystemReset();
+        break;
+        case 'S':
+            USB_send("Test string for USB\n");
+            return "Short test sent\n";
+        break;
+        case 'T':
+            SEND(get_time(&current_time, get_millis()));
+        break;
+        case 'W':
+            USB_send("Wait for reboot\n");
+            SEND("Wait for reboot\n");
+            while(1){nop();};
+        break;
+        default: // help
+            if(buf[1] != '\n') return buf;
+            return
+            "0/1 - turn on/off LED1\n"
+            "'a' - add test log record\n"
+            "'b' - get buttons's state\n"
+            "'c' - send cold start\n"
+            "'d' - dump current user conf\n"
+            "'D' - dump log\n"
+            "'p' - toggle USB pullup\n"
+            "'C' - store userconf for N times\n"
+            "'G' - get last LIDAR distance\n"
+            "'L' - send long string over USB\n"
+            "'R' - software reset\n"
+            "'S' - send short string over USB\n"
+            "'T' - show current GPS time\n"
+            "'W' - test watchdog\n"
+            ;
+        break;
+    }
+    return NULL;
+}
+#endif
+
+#define USBBUF 63
+// usb getline
+static char *get_USB(){
+    static char tmpbuf[USBBUF+1], *curptr = tmpbuf;
+    static int rest = USBBUF;
+    int x = USB_receive(curptr, rest);
+    if(!x) return NULL;
+    curptr[x] = 0;
+    USB_send(curptr); // echo
+    //USB_send("ENDOINPUT\n");
+//if(x == 1 && *curptr < 32){USB_send("\n"); USB_send(u2str(*curptr)); USB_send("\n");}
+    if(curptr[x-1] == '\n'){ // || curptr[x-1] == '\r'){
+        curptr = tmpbuf;
+        rest = USBBUF;
+        // omit empty lines
+        if(tmpbuf[0] == '\n') return NULL;
+        // and wrong empty lines
+        if(tmpbuf[0] == '\r' && tmpbuf[1] == '\n') return NULL;
+        return tmpbuf;
+    }
+    curptr += x; rest -= x;
+    if(rest <= 0){ // buffer overflow
+        //SEND("USB buffer overflow!\n");
+        curptr = tmpbuf;
+        rest = USBBUF;
+    }
+    return NULL;
+}
+
+void linecoding_handler(usb_LineCoding __attribute__((unused)) *lc){ // get/set line coding
+#ifdef EBUG
+    SEND("Change speed to");
+    printu(1, lc->dwDTERate);
+    newline();
+#endif
+}
+
+
+static volatile uint8_t USBconn = 0;
+void clstate_handler(uint16_t __attribute__((unused)) val){ // lesser bits of val: RTS|DTR
+    USBconn = 1;
+#ifdef EBUG
+    if(val & 2){
+        DBG("RTS set");
+        USB_send("RTS set\n");
+    }
+    if(val & 1){
+        DBG("DTR set");
+        USB_send("DTR set\n");
+    }
+#endif
+}
+
+void break_handler(){ // client disconnected
+    DBG("Disconnected");
+}
+
+#ifdef EBUG
+extern int32_t ticksdiff, timecntr, timerval, Tms1;
+#endif
+
+int main(void){
+    uint32_t lastT = 0;
+    sysreset();
+    StartHSE();
+    SysTick_Config(SYSTICK_DEFCONF); // function SysTick_Config decrements argument!
+    // !!! hw_setup() should be the first in setup stage
+    hw_setup();
+    USB_setup();
+    USBPU_ON();
+    usarts_setup();
+#ifdef EBUG
+    SEND("This is chronometer version " VERSION ".\n");
+    if(RCC->CSR & RCC_CSR_IWDGRSTF){ // watchdog reset occured
+        SEND("WDGRESET=1\n");
+    }
+    if(RCC->CSR & RCC_CSR_SFTRSTF){ // software reset occured
+        SEND("SOFTRESET=1\n");
+    }
+#endif
+    RCC->CSR |= RCC_CSR_RMVF; // remove reset flags
+    // read data stored in flash
+    flashstorage_init();
+    iwdg_setup();
+
+    while (1){
+        IWDG->KR = IWDG_REFRESH; // refresh watchdog
+        if(Timer > 499) LED_on(); // turn ON LED0 over 0.25s after PPS pulse
+        if(USBconn && Tms > 100){ // USB connection
+            USBconn = 0;
+            USB_send("Chronometer version " VERSION ".\n");
+        }
+        // check if triggers that was recently shot are off now
+        fillunshotms();
+        if(Tms - lastT > 499){
+            if(need2startseq) GPS_send_start_seq();
+            IWDG->KR = IWDG_REFRESH;
+            switch(GPS_status){
+                case GPS_VALID:
+                    LED1_blink(); // blink LED1 @ VALID time
+                break;
+                case GPS_NOT_VALID:
+                    LED1_on(); // shine LED1 @ NON-VALID time
+                break;
+                default:
+                    LED1_off(); // turn off LED1 if GPS not found or time unknown
+            }
+            lastT = Tms;
+            /*if(usartrx(LIDAR_USART)){
+                char *txt;
+                if(usart_getline(LIDAR_USART, &txt)){
+                    DBG("LIDAR:");
+                    DBG(txt);
+                }
+            }*/
+            IWDG->KR = IWDG_REFRESH;
+            transmit_tbuf(1); // non-blocking transmission of data from UART buffer every 0.5s
+            transmit_tbuf(GPS_USART);
+            transmit_tbuf(LIDAR_USART);
+#ifdef EBUG
+            static uint8_t x = 1;
+            if(timecntr){
+                if(x){
+                    SEND("ticksdiff=");
+                    if(ticksdiff < 0){
+                        SEND("-");
+                        printu(1, -ticksdiff);
+                    }else printu(1, ticksdiff);
+                    SEND(", timecntr=");
+                    printu(1, timecntr);
+                    SEND("\nlast_corr_time=");
+                    printu(1, last_corr_time);
+                    SEND(", Tms=");
+                    printu(1, Tms1);
+                    SEND("\nTimer=");
+                    printu(1, timerval);
+                    SEND(", LOAD=");
+                    printu(1, SysTick->LOAD);
+                    newline();
+                }
+                x = !x;
+            }
+#endif
+        }
+        IWDG->KR = IWDG_REFRESH;
+        usb_proc();
+        IWDG->KR = IWDG_REFRESH;
+        int r = 0;
+        char *txt = NULL;
+        if((txt = get_USB())){
+            DBG("Received data over USB:");
+            DBG(txt);
+            if(parse_USBCMD(txt)){
+                USB_send("Bad command: ");
+                USB_send(txt);
+                USB_send("\n");
+            }
+            IWDG->KR = IWDG_REFRESH;
+        }
+        if(usartrx(1)){ // usart1 received data, store in in buffer
+            r = usart_getline(1, &txt);
+            if(r){
+                txt[r] = 0;
+#ifdef EBUG
+                char *ans = parse_cmd(txt);
+                IWDG->KR = IWDG_REFRESH;
+                if(ans){
+                    transmit_tbuf(1);
+                    IWDG->KR = IWDG_REFRESH;
+                    usart_send(1, ans);
+                    transmit_tbuf(1);
+                    IWDG->KR = IWDG_REFRESH;
+                }
+#endif
+                if(the_conf.defflags & FLAG_GPSPROXY){
+                    usart_send(GPS_USART, txt);
+                    IWDG->KR = IWDG_REFRESH;
+                }
+            }
+        }
+        if(usartrx(GPS_USART)){
+            IWDG->KR = IWDG_REFRESH;
+            r = usart_getline(GPS_USART, &txt);
+            if(r){
+                txt[r] = 0;
+                if(the_conf.defflags & FLAG_GPSPROXY) usart_send(1, txt);
+                GPS_parse_answer(txt);
+            }
+        }
+        if(usartrx(LIDAR_USART)){
+            IWDG->KR = IWDG_REFRESH;
+            r = usart_getline(LIDAR_USART, &txt);
+            if(r){
+                parse_lidar_data(txt);
+            }
+        }
+        chk_buzzer(); // should we turn off buzzer?
+    }
+    return 0;
+}

F1-nolib/chronometer_v1/src_new/stm32F103xB.ld

@@ -0,0 +1,109 @@
+/*
+********************************************************************************
+*                                                                              *
+* Copyright (c) 2017 Andrea Loi                                                *
+*                                                                              *
+* Permission is hereby granted, free of charge, to any person obtaining a      *
+* copy of this software and associated documentation files (the "Software"),   *
+* to deal in the Software without restriction, including without limitation    *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,     *
+* and/or sell copies of the Software, and to permit persons to whom the        *
+* Software is furnished to do so, subject to the following conditions:         *
+*                                                                              *
+* The above copyright notice and this permission notice shall be included      *
+* in all copies or substantial portions of the Software.                       *
+*                                                                              *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR   *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,     *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL      *
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER   *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING      *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER          *
+* DEALINGS IN THE SOFTWARE.                                                    *
+*                                                                              *
+********************************************************************************
+*/
+
+MEMORY
+{
+    rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+    ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+/******************************************************************************/
+/*          DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING!           */
+/******************************************************************************/
+
+/* _isrvectors_tend =    0x00000150; - different for different series */
+
+ENTRY(reset_handler)
+
+SECTIONS {
+  .vector_table 0x08000000 :
+  {
+    _sisrvectors = .;
+    KEEP(*(.vector_table))
+    /* ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!"); */
+    _eisrvectors = .;
+  } >rom
+
+  .text :
+  {
+    . = ALIGN(4);
+    _stext = .;
+    *(.text*)
+    *(.rodata*)
+    . = ALIGN(4);
+    _etext = .;
+  } >rom
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >rom
+  
+  .ARM : {
+    *(.ARM.exidx*)
+  } >rom
+  
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;
+    *(.data*)
+    . = ALIGN(4);
+    _edata = .;
+  } >ram AT >rom
+
+  .myvars :
+  {
+    . = ALIGN(1024);
+    __varsstart = ABSOLUTE(.);
+    KEEP(*(.myvars));
+    . = . + 2000;
+    . = ALIGN(1024);
+    __varsend = ABSOLUTE(.);
+  } > rom
+
+  .logs :
+  {
+    . = ALIGN(1024);
+    __logsstart = ABSOLUTE(.);
+    KEEP(*(.logs))
+  } > rom
+
+  _ldata = LOADADDR(.data);
+
+  .bss :
+  {
+    . = ALIGN(4);
+    _sbss = .;
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    _ebss = .;
+  } >ram
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
+PROVIDE(_varslen = __varsend - __varsstart);

F1-nolib/chronometer_v1/src_new/str.c

@@ -0,0 +1,562 @@
+/*
+ * This file is part of the chronometer project.
+ * Copyright 2019 Edward V. Emelianov <edward.emelianoff@gmail.com>.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "adc.h"
+#include "GPS.h"
+#include "lidar.h"
+#include "str.h"
+#include "time.h"
+#include "usart.h"
+#include "usb.h"
+
+// flag to show new GPS message over USB
+uint8_t showGPSstr = 0;
+
+extern uint32_t shotms[];
+
+/**
+ * @brief cmpstr - the same as strncmp
+ * @param s1,s2 - strings to compare
+ * @param n - max symbols amount
+ * @return 0 if strings equal or 1/-1
+ */
+int cmpstr(const char *s1, const char *s2, int n){
+    int ret = 0;
+    while(--n){
+        ret = *s1 - *s2;
+        if(ret == 0 && *s1 && *s2){
+            ++s1; ++s2;
+            continue;
+        }
+        break;
+    }
+    return ret;
+}
+
+/**
+ * @brief getchr - analog of strchr
+ * @param str - string to search
+ * @param symbol - searching symbol
+ * @return pointer to symbol found or NULL
+ */
+char *getchr(const char *str, char symbol){
+    do{
+        if(*str == symbol) return (char*)str;
+    }while(*(++str));
+    return NULL;
+}
+
+#define sendu(x) do{USB_send(u2str(x));}while(0)
+
+static void sendi(int32_t I){
+    if(I < 0){
+        USB_send("-");
+        I = -I;
+    }
+    USB_send(u2str((uint32_t)I));
+}
+
+/**
+ * @brief showuserconf - show configuration over USB
+ */
+static void showuserconf(){
+    USB_send("DISTMIN="); sendu(the_conf.dist_min);
+    USB_send("\nDISTMAX="); sendu(the_conf.dist_max);
+    USB_send("\nADCMIN="); sendi(the_conf.ADC_min);
+    USB_send("\nADCMAX="); sendi(the_conf.ADC_max);
+    USB_send("\nTRIGLVL="); sendu(the_conf.trigstate);
+    USB_send("\nTRIGPAUSE={");
+    for(int i = 0; i < TRIGGERS_AMOUNT; ++i){
+        if(i) USB_send(", ");
+        sendu(the_conf.trigpause[i]);
+    }
+    USB_send("}");
+    USB_send("\nUSART1SPD="); sendu(the_conf.USART_speed);
+    USB_send("\nSTREND=");
+    if(the_conf.defflags & FLAG_STRENDRN) USB_send("RN");
+    else USB_send("N");
+    uint8_t f = the_conf.defflags;
+    USB_send("\nSAVE_EVENTS=");
+    if(f & FLAG_SAVE_EVENTS) USB_send("1");
+    else USB_send("0");
+    USB_send("\nGPSPROXY=");
+    if(f & FLAG_GPSPROXY) USB_send("1");
+    else USB_send("0");
+    USB_send("\nNFREE=");
+    sendu(the_conf.NLfreeWarn);
+    USB_send("\n");
+}
+
+/**
+ * @brief parse_USBCMD - parsing of string buffer got by USB
+ * @param cmd - buffer with commands
+ * @return 0 if got command, 1 if command not recognized
+ */
+int parse_USBCMD(char *cmd){
+#define CMP(a,b)  cmpstr(a, b, sizeof(b))
+#define GETNUM(x) if(getnum(cmd+sizeof(x)-1, &N)) goto bad_number;
+    static uint8_t conf_modified = 0;
+    uint8_t succeed = 0;
+    int32_t N;
+    if(!cmd || !*cmd) return 0;
+    IWDG->KR = IWDG_REFRESH;
+    if(*cmd == '?'){ // help
+        USB_send("Commands:\n"
+                 CMD_ADCMAX    " - max ADC value treshold for trigger\n"
+                 CMD_ADCMIN    " - min -//- (triggered when ADval>min & <max)\n"
+                 CMD_GETADCVAL " - get ADC value\n"
+                 CMD_BUZZER    "S - turn buzzer ON/OFF\n"
+                 CMD_CURDIST   " - show current LIDAR distance\n"
+                 CMD_DELLOGS   " - delete logs from flash memory\n"
+                 CMD_DISTMIN   " - min distance threshold (cm)\n"
+                 CMD_DISTMAX   " - max distance threshold (cm)\n"
+                 CMD_DUMP      "N - dump 20 last stored events (no x), all (x<1) or x\n"
+                 CMD_FLASH     " - FLASH info\n"
+                 CMD_GPSPROXY  "S - GPS proxy over USART1 on/off\n"
+                 CMD_GPSRESTART " - send Full Cold Restart to GPS\n"
+                 CMD_GPSSTAT   " - get GPS status\n"
+                 CMD_GPSSTR    " - current GPS data string\n"
+                 CMD_LEDS      "S - turn leds on/off (1/0)\n"
+                 CMD_GETMCUTEMP " - MCU temperature\n"
+                 CMD_NFREE     " - warn when free logs space less than this number (0 - not warn)"
+                 CMD_PRINTTIME " - print time\n"
+                 CMD_RESET     " - reset MCU\n"
+                 CMD_SAVEEVTS  "S - save/don't save (1/0) trigger events into flash\n"
+                 CMD_SHOWCONF  " - show current configuration\n"
+                 CMD_STORECONF " - store new configuration in flash\n"
+                 CMD_STREND    "C - string ends with \\n (C=n) or \\r\\n (C=r)\n"
+                 CMD_PRINTTIME " - print current time\n"
+                 CMD_TRIGLVL   "NS - working trigger N level S\n"
+                 CMD_TRGPAUSE  "NP - pause (P, ms) after trigger N shots\n"
+                 CMD_TRGTIME   "N - show last trigger N time\n"
+                 CMD_USARTSPD  "N - set USART1 speed to N\n"
+                 CMD_GETVDD    " - Vdd value\n"
+                 );
+    }else if(CMP(cmd, CMD_PRINTTIME) == 0){
+        USB_send(get_time(&current_time, get_millis()));
+        USB_send("\n");
+    }else if(CMP(cmd, CMD_DISTMIN) == 0){ // set low limit
+        DBG("CMD_DISTMIN");
+        GETNUM(CMD_DISTMIN);
+        if(N < 0 || N > 0xffff) goto bad_number;
+        if(the_conf.dist_min != (uint16_t)N){
+            conf_modified = 1;
+            the_conf.dist_min = (uint16_t) N;
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_DISTMAX) == 0){ // set low limit
+        DBG("CMD_DISTMAX");
+        GETNUM(CMD_DISTMAX);
+        if(N < 0 || N > 0xffff) goto bad_number;
+        if(the_conf.dist_max != (uint16_t)N){
+            conf_modified = 1;
+            the_conf.dist_max = (uint16_t) N;
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_STORECONF) == 0){ // store everything
+        DBG("Store");
+        if(conf_modified){
+            if(store_userconf()){
+                USB_send("Error: can't save data!\n");
+            }else{
+                conf_modified = 0;
+                succeed = 1;
+            }
+        }
+    }else if(CMP(cmd, CMD_GPSSTR) == 0){ // show GPS status string
+        showGPSstr = 1;
+    }else if(CMP(cmd, CMD_TRIGLVL) == 0){
+        DBG("Trig levels");
+        cmd += sizeof(CMD_TRIGLVL) - 1;
+        uint8_t Nt = *cmd++ - '0';
+        if(Nt > TRIGGERS_AMOUNT - 1) goto bad_number;
+        uint8_t state = *cmd -'0';
+        if(state > 1) goto bad_number;
+        uint8_t oldval = the_conf.trigstate;
+        if(!state) the_conf.trigstate = oldval & ~(1<<Nt);
+        else the_conf.trigstate = oldval | (1<<Nt);
+        if(oldval != the_conf.trigstate) conf_modified = 1;
+        succeed = 1;
+    }else if(CMP(cmd, CMD_SHOWCONF) == 0){
+        showuserconf();
+    }else if(CMP(cmd, CMD_TRGPAUSE) == 0){
+        DBG("Trigger pause");
+        cmd += sizeof(CMD_TRGPAUSE) - 1;
+        uint8_t Nt = *cmd++ - '0';
+        if(Nt > TRIGGERS_AMOUNT - 1) goto bad_number;
+        if(getnum(cmd, &N)) goto bad_number;
+        if(N < 0 || N > 10000) goto bad_number;
+        if(the_conf.trigpause[Nt] != N){
+            conf_modified = 1;
+            the_conf.trigpause[Nt] = N;
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_TRGTIME) == 0){
+        DBG("Trigger time");
+        cmd += sizeof(CMD_TRGTIME) - 1;
+        uint8_t Nt = *cmd++ - '0';
+        if(Nt > TRIGGERS_AMOUNT - 1) goto bad_number;
+        show_trigger_shot((uint8_t)1<<Nt);
+    }else if(CMP(cmd, CMD_GETVDD) == 0){
+        USB_send("VDD=");
+        uint32_t vdd = getVdd();
+        sendu(vdd/100);
+        vdd %= 100;
+        if(vdd < 10) USB_send(".0");
+        else USB_send(".");
+        sendu(vdd);
+        USB_send("\n");
+    }else if(CMP(cmd, CMD_GETMCUTEMP) == 0){
+        int32_t t = getMCUtemp();
+        USB_send("MCUTEMP=");
+        if(t < 0){
+            t = -t;
+            USB_send("-");
+        }
+        sendu(t/10);
+        USB_send(".");
+        sendu(t%10);
+        USB_send("\n");
+    }else if(CMP(cmd, CMD_GETADCVAL) == 0){
+        USB_send("ADCVAL=");
+        sendu(getADCval(0));
+        USB_send("\n");
+    }else if(CMP(cmd, CMD_LEDS) == 0){
+        uint8_t Nt = cmd[sizeof(CMD_LEDS) - 1] - '0';
+        if(Nt > 1) goto bad_number;
+        USB_send("LEDS=");
+        if(Nt){
+            LEDSon = 1;
+            USB_send("ON\n");
+        }else{
+            LED_off();  // turn off LEDS
+            LED1_off(); // by user request
+            LEDSon = 0;
+            USB_send("OFF\n");
+        }
+    }else if(CMP(cmd, CMD_ADCMAX) == 0){ // set low limit
+        GETNUM(CMD_ADCMAX);
+        if(N < -4096 || N > 4096) goto bad_number;
+        if(the_conf.ADC_max != (int16_t)N){
+            conf_modified = 1;
+            the_conf.ADC_max = (int16_t) N;
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_ADCMIN) == 0){ // set low limit
+        GETNUM(CMD_ADCMIN);
+        if(N < -4096 || N > 4096) goto bad_number;
+        if(the_conf.ADC_min != (int16_t)N){
+            conf_modified = 1;
+            the_conf.ADC_min = (int16_t) N;
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_GPSRESTART) == 0){
+        USB_send("Send full cold restart to GPS\n");
+        GPS_send_FullColdStart();
+    }else if(CMP(cmd, CMD_BUZZER) == 0){
+        uint8_t Nt = cmd[sizeof(CMD_BUZZER) - 1] - '0';
+        if(Nt > 1) goto bad_number;
+        USB_send("BUZZER=");
+        if(Nt){
+            buzzer_on = 1;
+            USB_send("ON\n");
+        }else{
+            buzzer_on = 0;
+            USB_send("OFF\n");
+        }
+    }else if(CMP(cmd, CMD_GPSSTAT) == 0){
+        USB_send("GPS status: ");
+        const char *str = "unknown";
+        switch(GPS_status){
+            case GPS_NOTFOUND:
+                str = "not found";
+            break;
+            case GPS_WAIT:
+                str = "waiting";
+            break;
+            case GPS_NOT_VALID:
+                str = "no satellites";
+            break;
+            case GPS_VALID:
+                str = "valid time";
+            break;
+        }
+        USB_send(str);
+        if(Tms - last_corr_time < 1500)
+            USB_send(", PPS working\n");
+        else
+            USB_send(", no PPS\n");
+    }else if(CMP(cmd, CMD_USARTSPD) == 0){
+        GETNUM(CMD_USARTSPD);
+        if(N < 400 || N > 3000000) goto bad_number;
+        if(the_conf.USART_speed != (uint32_t)N){
+            the_conf.USART_speed = (uint32_t)N;
+            conf_modified = 1;
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_RESET) == 0){
+        USB_send("Soft reset\n");
+        NVIC_SystemReset();
+    }else if(CMP(cmd, CMD_STREND) == 0){
+        char c = cmd[sizeof(CMD_STREND) - 1];
+        succeed = 1;
+        if(c == 'n' || c == 'N'){
+            if(the_conf.defflags & FLAG_STRENDRN){
+                conf_modified = 1;
+                the_conf.defflags &= ~FLAG_STRENDRN;
+            }
+        }else if(c == 'r' || c == 'R'){
+            if(!(the_conf.defflags & FLAG_STRENDRN)){
+                conf_modified = 1;
+                the_conf.defflags |= FLAG_STRENDRN;
+            }
+        }else{
+            succeed = 0;
+            USB_send("Bad letter, should be 'n' or 'r'\n");
+        }
+    }else if(CMP(cmd, CMD_FLASH) == 0){ // show flash size
+        USB_send("FLASHSIZE=");
+        sendu(FLASH_SIZE);
+        USB_send("kB\nFLASH_BASE=");
+        USB_send(u2hex(FLASH_BASE));
+        USB_send("\nFlash_Data=");
+        USB_send(u2hex((uint32_t)Flash_Data));
+        USB_send("\nvarslen=");
+        sendu((uint32_t)&_varslen);
+        USB_send("\nCONFsize=");
+        sendu(sizeof(user_conf));
+        USB_send("\nNconf_records=");
+        sendu(maxCnum - 1);
+        USB_send("\nlogsstart=");
+        USB_send(u2hex((uint32_t)logsstart));
+        USB_send("\nLOGsize=");
+        sendu(sizeof(event_log));
+        USB_send("\nNlogs_records=");
+        sendu(maxLnum - 1);
+        USB_send("\n");
+    }else if(CMP(cmd, CMD_SAVEEVTS) == 0){
+        if('0' == cmd[sizeof(CMD_SAVEEVTS) - 1]){
+            if(the_conf.defflags & FLAG_SAVE_EVENTS){
+                conf_modified = 1;
+                the_conf.defflags &= ~FLAG_SAVE_EVENTS;
+            }
+        }else{
+            if(!(the_conf.defflags & FLAG_SAVE_EVENTS)){
+                conf_modified = 1;
+                the_conf.defflags |= FLAG_SAVE_EVENTS;
+            }
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_DUMP) == 0){
+        if(getnum(cmd+sizeof(CMD_DUMP)-1, &N)) N = -20; // default - without N
+        else N = -N;
+        if(N > 0) N = 0;
+        if(dump_log(N, -1)) USB_send("Event log empty!\n");
+    }else if(CMP(cmd, CMD_NFREE) == 0){
+        GETNUM(CMD_NFREE);
+        if(N < 0 || N > 0xffff) goto bad_number;
+        if(the_conf.NLfreeWarn != (uint16_t)N){
+            conf_modified = 1;
+            the_conf.NLfreeWarn = (uint16_t)N;
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_DELLOGS) == 0){
+        if(store_log(NULL)) USB_send("Error during erasing flash\n");
+        else USB_send("All logs erased\n");
+    }else if(CMP(cmd, CMD_GPSPROXY) == 0){
+        if(cmd[sizeof(CMD_GPSPROXY) - 1] == '0'){
+            if(the_conf.defflags & FLAG_GPSPROXY){
+                conf_modified = 1;
+                the_conf.defflags &= ~FLAG_GPSPROXY;
+            }
+        }else{
+            if(!(the_conf.defflags & FLAG_GPSPROXY)){
+                conf_modified = 1;
+                the_conf.defflags |= FLAG_GPSPROXY;
+            }
+        }
+        succeed = 1;
+    }else if(CMP(cmd, CMD_CURDIST) == 0){
+        USB_send("DIST=");
+        sendu(last_lidar_dist);
+        USB_send("\nSTREN=");
+        sendu(last_lidar_stren);
+        USB_send("\nTRIGDIST=");
+        sendu(lidar_triggered_dist);
+        USB_send("\nTms=");
+        sendu(Tms);
+        USB_send("\nshotms=");
+        sendu(shotms[LIDAR_TRIGGER]);
+        USB_send("\n");
+    }else return 1;
+    /*else if(CMP(cmd, CMD_) == 0){
+        ;
+    }*/
+
+    IWDG->KR = IWDG_REFRESH;
+    if(succeed) USB_send("Success!\n");
+    return 0;
+  bad_number:
+    USB_send("Error: bad number!\n");
+    return 0;
+}
+
+/**
+ * @brief get_trigger_shot - print on USB message about last trigger shot time
+ * @param number  - number of event (if > -1)
+ * @param logdata - record from event log
+ * @return string with data
+ */
+char *get_trigger_shot(int number, const event_log *logdata){
+    static char buf[64];
+    char *bptr = buf;
+    if(number > -1){
+        bptr = strcp(bptr, u2str(number));
+        bptr = strcp(bptr, ": ");
+    }
+    if(logdata->trigno == LIDAR_TRIGGER){
+        bptr = strcp(bptr, "LIDAR, dist=");
+        bptr = strcp(bptr, u2str(logdata->lidar_dist));
+        bptr = strcp(bptr, ", TRIG" STR(LIDAR_TRIGGER));
+    }else{
+        bptr = strcp(bptr, "TRIG");
+        *bptr++ = '0' + logdata->trigno;
+    }
+    *bptr++ = '=';
+    IWDG->KR = IWDG_REFRESH;
+    bptr = strcp(bptr, get_time(&logdata->shottime.Time, logdata->shottime.millis));
+    bptr = strcp(bptr, ", len=");
+    if(logdata->triglen < 0) bptr = strcp(bptr, ">1s");
+    else bptr = strcp(bptr, u2str((uint32_t) logdata->triglen));
+    *bptr++ = '\n'; *bptr++ = 0;
+    return buf;
+}
+
+/**
+ * @brief show_trigger_shot printout @ USB data with all triggers shot recently (+ save it in flash)
+ * @param tshot - each bit consists information about trigger
+ */
+void show_trigger_shot(uint8_t tshot){
+    uint8_t X = 1;
+    for(int i = 0; i < TRIGGERS_AMOUNT && tshot; ++i, X <<= 1){
+        IWDG->KR = IWDG_REFRESH;
+        if(tshot & X) tshot &= ~X;
+        else continue;
+        event_log l;
+        l.elog_sz = sizeof(event_log);
+        l.trigno = i;
+        if(i == LIDAR_TRIGGER) l.lidar_dist = lidar_triggered_dist;
+        l.shottime = shottime[i];
+        l.triglen = triglen[i];
+        USB_send(get_trigger_shot(-1, &l));
+        if(the_conf.defflags & FLAG_SAVE_EVENTS){
+            if(store_log(&l)) USB_send("\n\nError saving event!\n\n");
+        }
+    }
+}
+
+/**
+ * @brief strln == strlen
+ * @param s - string
+ * @return length
+ */
+int strln(const char *s){
+    int i = 0;
+    while(*s++) ++i;
+    return i;
+}
+
+/**
+ * @brief strcp - strcpy (be carefull: it doesn't checks destination length!)
+ * @param dst - destination
+ * @param src - source
+ * @return pointer to '\0' @ dst`s end
+ */
+char *strcp(char* dst, const char *src){
+    int l = strln(src);
+    if(l < 1) return dst;
+    while((*dst++ = *src++));
+    return dst - 1;
+}
+
+
+// read `buf` and get first integer `N` in it
+// @return 0 if all OK or 1 if there's not a number; omit spaces and '='
+int getnum(const char *buf, int32_t *N){
+    char c;
+    int positive = -1;
+    int32_t val = 0;
+    while((c = *buf++)){
+        if(c == '\t' || c == ' ' || c == '='){
+            if(positive < 0) continue; // beginning spaces
+            else break; // spaces after number
+        }
+        if(c == '-'){
+            if(positive < 0){
+                positive = 0;
+                continue;
+            }else break; // there already was `-` or number
+        }
+        if(c < '0' || c > '9') break;
+        if(positive < 0) positive = 1;
+        val = val * 10 + (int32_t)(c - '0');
+    }
+    if(positive != -1){
+        if(positive == 0){
+            if(val == 0) return 1; // single '-'
+            val = -val;
+        }
+        *N = val;
+    }else return 1;
+    return 0;
+}
+
+static char strbuf[11];
+// return string buffer (strbuf) with val
+char *u2str(uint32_t val){
+    char *bufptr = &strbuf[10];
+    *bufptr = 0;
+    if(!val){
+        *(--bufptr) = '0';
+    }else{
+        while(val){
+            *(--bufptr) = val % 10 + '0';
+            val /= 10;
+        }
+    }
+    return bufptr;
+}
+
+// return strbuf filled with hex
+char *u2hex(uint32_t val){
+    char *bufptr = strbuf;
+    *bufptr++ = '0';
+    *bufptr++ = 'x';
+    uint8_t *ptr = (uint8_t*)&val + 3;
+    int i, j;
+    IWDG->KR = IWDG_REFRESH;
+    for(i = 0; i < 4; ++i, --ptr){
+        for(j = 1; j > -1; --j){
+            register uint8_t half = (*ptr >> (4*j)) & 0x0f;
+            if(half < 10) *bufptr++ = half + '0';
+            else *bufptr++ = half - 10 + 'a';
+        }
+    }
+    *bufptr = 0;
+    return strbuf;
+}

F1-nolib/chronometer_v1/src_new/str.h

@@ -0,0 +1,70 @@
+/*
+ * This file is part of the chronometer project.
+ * Copyright 2019 Edward V. Emelianov <edward.emelianoff@gmail.com>.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#pragma once
+#ifndef STR_H__
+#define STR_H__
+
+#include "stm32f1.h"
+#include "flash.h"
+#include "hardware.h"
+
+// usb commands
+// lower and upper limits to capture
+#define CMD_DISTMIN     "distmin"
+#define CMD_DISTMAX     "distmax"
+#define CMD_ADCMIN      "adcmin"
+#define CMD_ADCMAX      "adcmax"
+#define CMD_PRINTTIME   "time"
+#define CMD_STORECONF   "store"
+#define CMD_GPSSTR      "gpsstring"
+#define CMD_SHOWCONF    "showconf"
+#define CMD_TRIGLVL     "triglevel"
+#define CMD_TRGPAUSE    "trigpause"
+#define CMD_TRGTIME     "trigtime"
+#define CMD_GETVDD      "vdd"
+#define CMD_GETMCUTEMP  "mcutemp"
+#define CMD_GETADCVAL   "adcval"
+#define CMD_LEDS        "leds"
+#define CMD_GPSRESTART  "gpsrestart"
+#define CMD_BUZZER      "buzzer"
+#define CMD_GPSSTAT     "gpsstat"
+#define CMD_USARTSPD    "usartspd"
+#define CMD_RESET       "reset"
+#define CMD_STREND      "strend"
+#define CMD_FLASH       "flash"
+#define CMD_SAVEEVTS    "se"
+#define CMD_DUMP        "dump"
+#define CMD_NFREE       "nfree"
+#define CMD_DELLOGS     "deletelogs"
+#define CMD_GPSPROXY    "gpsproxy"
+#define CMD_CURDIST     "curdist"
+
+extern uint8_t showGPSstr;
+
+int getnum(const char *buf, int32_t *N);
+char *u2str(uint32_t val);
+char *u2hex(uint32_t val);
+
+int strln(const char *s);
+char *strcp(char* dst, const char *src);
+int cmpstr(const char *s1, const char *s2, int n);
+char *getchr(const char *str, char symbol);
+int parse_USBCMD(char *cmd);
+char *get_trigger_shot(int number, const event_log *logdata);
+void show_trigger_shot(uint8_t trigger_shot);
+#endif // STR_H__

F1-nolib/chronometer_v1/src_new/time.c

@@ -0,0 +1,199 @@
+/*
+ * This file is part of the chronometer project.
+ * Copyright 2019 Edward V. Emelianov <edward.emelianoff@gmail.com>.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "GPS.h"
+#include "time.h"
+#ifdef EBUG
+#include "usart.h"
+#endif
+#include "usb.h"
+#include <string.h>
+
+volatile uint32_t Timer; // milliseconds counter
+curtime current_time = TMNOTINI;
+
+static inline uint8_t atou(const char *b){
+    return (b[0]-'0')*10 + b[1]-'0';
+}
+
+/**
+ * @brief set_time - set current time from GPS data
+ * @param buf - buffer with time data (HHMMSS)
+ */
+void set_time(const char *buf){
+    uint8_t H = atou(buf);// + TIMEZONE_GMT_PLUS;
+    if(H > 23) H -= 24;
+    current_time.H = H;
+    current_time.M = atou(&buf[2]);
+    current_time.S = atou(&buf[4]);
+#ifdef EBUG
+    SEND("set_time, Tms: "); printu(1, Tms);
+    SEND("; Timer: "); printu(1, Timer);
+    newline();
+#endif
+}
+
+/**
+ * @brief time_increment - increment system timer by systick
+ */
+void time_increment(){
+    Timer = 0;
+    if(current_time.H == 25) return; // Time not initialized
+    if(++current_time.S == 60){
+        current_time.S = 0;
+        if(++current_time.M == 60){
+            current_time.M = 0;
+            if(++current_time.H == 24)
+                current_time.H = 0;
+        }
+    }
+    /*
+#ifdef EBUG
+    SEND("time_increment():  ");
+    SEND(get_time(&current_time, 0));
+#endif
+    */
+}
+
+static char *puttwo(uint8_t N, char *buf){
+    if(N < 10){
+        *buf++ = '0';
+    }else{
+        *buf++ = N/10 + '0';
+        N %= 10;
+    }
+    *buf++ = N + '0';
+    return buf;
+}
+
+/**
+ * @brief ms2str - fill buffer str with milliseconds ms
+ * @param str (io) - pointer to buffer
+ * @param T - milliseconds
+ */
+static void ms2str(char **str, uint32_t T){
+    char *bptr = *str;
+    *bptr++ = '.';
+    if(T > 99){
+        *bptr++ = T/100 + '0';
+        T %= 100;
+    }else *bptr++ = '0';
+    if(T > 9){
+        *bptr++ = T/10 + '0';
+        T %= 10;
+    }else *bptr++ = '0';
+    *bptr++ = T + '0';
+    *str = bptr;
+}
+
+/**
+ * print time: Tm - time structure, T - milliseconds
+ */
+char *get_time(const curtime *Tm, uint32_t T){
+    static char buf[64];
+    char *bstart = &buf[5], *bptr = bstart;
+    int S = 0;
+    if(T > 999) return "Wrong time";
+    if(Tm->S < 60 && Tm->M < 60 && Tm->H < 24)
+        S = Tm->S + Tm->H*3600 + Tm->M*60; // seconds from day beginning
+    if(!S) *(--bstart) = '0';
+    while(S){
+        *(--bstart) = S%10 + '0';
+        S /= 10;
+    }
+    // now bstart is buffer starting index; bptr points to decimal point
+    ms2str(&bptr, T);
+    // put current time in HH:MM:SS format into buf
+    *bptr++ = ' '; *bptr++ = '(';
+    bptr = puttwo(Tm->H, bptr); *bptr++ = ':';
+    bptr = puttwo(Tm->M, bptr); *bptr++ = ':';
+    bptr = puttwo(Tm->S, bptr);
+    ms2str(&bptr, T);
+    *bptr++ = ')';
+    if(GPS_status == GPS_NOTFOUND){
+        strcpy(bptr, " GPS not found");
+        bptr += 14;
+    }
+    *bptr = 0;
+    return bstart;
+}
+
+
+#ifdef EBUG
+int32_t timerval, Tms1;
+#endif
+int32_t timecntr=0, ticksdiff=0;
+
+uint32_t last_corr_time = 0;
+
+/**
+ * @brief systick_correction
+ * Makes correction of system timer
+ * The default frequency of timer is 1kHz - 72000 clocks per interrupt
+ * So we check how much ticks there was for last one second - between PPS interrupts
+ * Their amount equal to M = `Timer` value x (SysTick->LOAD+1) + (SysTick->LOAD+1 - SysTick->VAL)
+ *    if `Timer` is very small, add 1000 to its value.
+ * We need 1000xN ticks instead of M
+ * if L = LOAD+1, then
+ * M = Timer*L + L - VAL; newL = L + D = M/1000
+ * 1000*D = M - 1000*L = L(Timer+1-1000) - VAL ->
+ * D = [L*(Timer-999) - VAL]/1000
+ * So correction equal to
+ *      [ (SysTick->LOAD + 1) * (Timer - 999) - SysTick->VAL ] / 1000
+ */
+void systick_correction(){
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; // stop systick for a while
+    uint32_t systick_val = SysTick->VAL, L = SysTick->LOAD + 1;
+    int32_t timer_val = Timer;
+#ifdef EBUG
+    timerval = Timer;
+    Tms1 = Tms;
+#endif
+    Timer = 0;
+    SysTick->VAL = SysTick->LOAD;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; // start it again
+//    if(systick_val != SysTick->LOAD) ++Tms;
+    if(timer_val > 500) time_increment(); // counter greater than 500 -> need to increment time
+    if(last_corr_time){
+        if(Tms - last_corr_time < 1500){ // there was perevious PPS signal
+            int32_t D = L * (Tms - 1000 - last_corr_time) + (SysTick->LOAD - systick_val); // amount of spare ticks
+#ifdef EBUG
+            ++timecntr;
+#endif
+            ticksdiff += D;
+            uint32_t ticksabs = (ticksdiff < 0) ? -ticksdiff : ticksdiff;
+            // 10000 == 30 seconds * 1000 interrupts per second
+            if(ticksabs > 30000 && timecntr > 30){ // need correction (not more often than each 10s)
+                ticksdiff /= timecntr * 1000; // correction per one interrupt
+                SysTick->LOAD += ticksdiff;
+                timecntr = 0;
+                ticksdiff = 0;
+                last_corr_time = 0;
+#ifdef EBUG
+                SEND("Correction\n");
+#endif
+            }
+        }else{
+            timecntr = 0;
+            ticksdiff = 0;
+            last_corr_time = 0;
+        }
+    }
+    last_corr_time = Tms;
+}
+