add G431-blink

G4:G431/inc/Fx/common_macros.h

@@ -0,0 +1,61 @@
+/*
+ * common_macros.h - common usable things
+ *
+ * Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+#ifndef __COMMON_MACROS_H__
+#define __COMMON_MACROS_H__
+
+#include <stdint.h>
+
+#ifndef _U_
+#define _U_ __attribute__((__unused__))
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE_INLINE
+#define TRUE_INLINE  __attribute__((always_inline)) static inline
+#endif
+
+#ifndef NULL
+#define NULL (0)
+#endif
+
+// some good things from CMSIS
+#define nop()   __NOP()
+
+#define pin_toggle(gpioport, gpios)  do{  \
+    register uint32_t __port = gpioport->ODR;  \
+    gpioport->BSRR = ((__port & (gpios)) << 16) | (~__port & (gpios));}while(0)
+
+#define pin_set(gpioport, gpios)  do{gpioport->BSRR = gpios;}while(0)
+#define pin_clear(gpioport, gpios) do{gpioport->BSRR = ((gpios) << 16);}while(0)
+#define pin_read(gpioport, gpios) (gpioport->IDR & (gpios) ? 1 : 0)
+#define pin_write(gpioport, gpios)  do{gpioport->ODR = gpios;}while(0)
+
+
+
+#endif // __COMMON_MACROS_H__

G4:G431/inc/Fx/flash_size_reg.h

@@ -0,0 +1,12 @@
+#define STM32F0_FlashAddr   0x1FFFF7CC   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F0
+#define STM32F1_FlashAddr   0x1FFFF7E0   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F1
+#define STM32F2_FlashAddr   0x1FFF7A22   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F2
+#define STM32F3_FlashAddr   0x1FFFF7CC   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F3
+#define STM32F4_FlashAddr   0x1FFF7A22   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F4
+#define STM32F7_FlashAddr   0x1FF0F442   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F7
+#define STM32L0_FlashAddr   0x1FF8007C   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L0
+#define STM32L1_FlashAddr   0x1FF8004C   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L1
+#define STM32L4_FlashAddr   0x1FFF75E0   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L4
+#define STM32H7_FlashAddr   0x1FF0F442   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÆÌÜÛ-ÐÁÍÑÔÉ STM32H7
+
+blocksize=2k if memory>=128k

G4:G431/inc/Fx/stm32g4.h

@@ -0,0 +1,270 @@
+/*
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+
+#include "vector.h"
+#include "stm32g4xx.h"
+#include "common_macros.h"
+
+#define WAITWHILE(x)  do{register uint32_t StartUpCounter = 0; while((x) && (++StartUpCounter < 0xfffff)){nop();}}while(0)
+//#define WAITWHILE(x)  do{while(x){nop();}}while(0)
+TRUE_INLINE void StartHSE(){
+    // ----- 1. Turn off PLL -----
+    RCC->CR &= ~RCC_CR_PLLON;
+    WAITWHILE(RCC->CR & RCC_CR_PLLRDY);
+
+    // ----- 2. Turn on HSE -----
+    // ðÁÒÁÍÅÔÒ isHSE ÉÇÎÏÒÉÒÕÅÔÓÑ  ×ÓÅÇÄÁ ÉÓÐÏÌØÚÕÅÍ HSE ÐÏ ÕÓÌÏ×ÉÀ ÚÁÄÁÞÉ
+    RCC->CR |= RCC_CR_HSEON;
+    WAITWHILE(!(RCC->CR & RCC_CR_HSERDY));
+
+    // ----- 3. Turn on power block PWR and setup for max freq (VOS = 0) -----
+    RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
+    PWR->CR1 &= ~(PWR_CR1_VOS_0 | PWR_CR1_VOS_1);
+    WAITWHILE(PWR->SR2 & PWR_SR2_VOSF);
+
+    // ----- 4. PLL setup (SYSCLK = 170 MHz) -----
+    // HSE = 8 MHz, PLLM = 2, si PLL in = 4 MHz
+    // PLLN = 85, so VCO = 4 * 85 = 340 MHz
+    // PLLR = 2, so SYSCLK = 340 / 2 = 170 MHz
+    //
+    RCC->PLLCFGR =
+        ((2 - 1)   << RCC_PLLCFGR_PLLM_Pos) |    // PLLM = 2
+        (85        << RCC_PLLCFGR_PLLN_Pos) |    // PLLN = 85
+        (0         << RCC_PLLCFGR_PLLR_Pos) |    // PLLR = 2 (code 0)
+        RCC_PLLCFGR_PLLREN |                     // turn on Rclk for SYSCLK
+        RCC_PLLCFGR_PLLSRC_HSE;                  // source is HSE
+
+    // ----- 5. Turn PLL on -----
+    RCC->CR |= RCC_CR_PLLON;
+    WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
+
+    // ----- 6. Flash setup (4 wait cycles for 170 íçÃ) -----
+    FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_4WS;
+
+    // ----- 7. Switch from SYSCLK to PLL -----
+    RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_Msk) | RCC_CFGR_SW_PLL;
+
+    // ----- 8. Turn on HSI48 and wait until ready -----
+    RCC->CRRCR |= RCC_CRRCR_HSI48ON;
+    WAITWHILE(!(RCC->CRRCR & RCC_CRRCR_HSI48RDY));
+
+    // ----- 9. Turn on CRS (Clock Recovery System) -----
+    RCC->APB1ENR1 |= RCC_APB1ENR1_CRSEN;
+
+    // ----- 10. Setup CRS for USB SOF sync -----
+    CRS->CR &= ~(CRS_CR_CEN | CRS_CR_AUTOTRIMEN | CRS_CR_SWSYNC);
+    CRS->CFGR &= ~CRS_CFGR_SYNCDIV_Msk;
+    CRS->CFGR = (CRS->CFGR & ~CRS_CFGR_SYNCSRC_Msk) | (1 << CRS_CFGR_SYNCSRC_Pos);
+    CRS->CFGR &= ~CRS_CFGR_SYNCDIV_Msk;
+    CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
+
+    // ----- 11. Select HSI48 as USB clock -----
+    RCC->CCIPR &= ~RCC_CCIPR_CLK48SEL_Msk; // 00: HSI48 clock selected as 48 MHz clock
+
+    SysFreq = 170000000UL;
+}
+
+/************************* GPIO *************************/
+
+/*******************  Bit definition for GPIO_MODER register  *****************/
+// _AI - analog inpt, _O - general output, _AF - alternate function
+#define GPIO_MODER_MODER0_AI        ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_O         ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_AF        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1_AI        ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_O         ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_AF        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2_AI        ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_O         ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_AF        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3_AI        ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_O         ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_AF        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4_AI        ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_O         ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_AF        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5_AI        ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_O         ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_AF        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6_AI        ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_O         ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_AF        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7_AI        ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_O         ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_AF        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8_AI        ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_O         ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_AF        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9_AI        ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_O         ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_AF        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10_AI       ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_O        ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_AF       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11_AI       ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_O        ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_AF       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12_AI       ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_O        ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_AF       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13_AI       ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_O        ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_AF       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14_AI       ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_O        ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_AF       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15_AI       ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_O        ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_AF       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_PUPDR register  *****************/
+// no/pullup/pulldown/reserved
+// for n in $(seq 0 15); do echo "#define GPIO_PUPDR${n}_PU              ((uint32_t)(1<<$((n*2))))";
+// echo "#define GPIO_PUPDR${n}_PD              ((uint32_t)(1<<$((n*2+1))))"; done
+// alt+select column -> delete
+#define GPIO_PUPDR0_PU              ((uint32_t)(1<<0))
+#define GPIO_PUPDR0_PD              ((uint32_t)(1<<1))
+#define GPIO_PUPDR1_PU              ((uint32_t)(1<<2))
+#define GPIO_PUPDR1_PD              ((uint32_t)(1<<3))
+#define GPIO_PUPDR2_PU              ((uint32_t)(1<<4))
+#define GPIO_PUPDR2_PD              ((uint32_t)(1<<5))
+#define GPIO_PUPDR3_PU              ((uint32_t)(1<<6))
+#define GPIO_PUPDR3_PD              ((uint32_t)(1<<7))
+#define GPIO_PUPDR4_PU              ((uint32_t)(1<<8))
+#define GPIO_PUPDR4_PD              ((uint32_t)(1<<9))
+#define GPIO_PUPDR5_PU              ((uint32_t)(1<<10))
+#define GPIO_PUPDR5_PD              ((uint32_t)(1<<11))
+#define GPIO_PUPDR6_PU              ((uint32_t)(1<<12))
+#define GPIO_PUPDR6_PD              ((uint32_t)(1<<13))
+#define GPIO_PUPDR7_PU              ((uint32_t)(1<<14))
+#define GPIO_PUPDR7_PD              ((uint32_t)(1<<15))
+#define GPIO_PUPDR8_PU              ((uint32_t)(1<<16))
+#define GPIO_PUPDR8_PD              ((uint32_t)(1<<17))
+#define GPIO_PUPDR9_PU              ((uint32_t)(1<<18))
+#define GPIO_PUPDR9_PD              ((uint32_t)(1<<19))
+#define GPIO_PUPDR10_PU             ((uint32_t)(1<<20))
+#define GPIO_PUPDR10_PD             ((uint32_t)(1<<21))
+#define GPIO_PUPDR11_PU             ((uint32_t)(1<<22))
+#define GPIO_PUPDR11_PD             ((uint32_t)(1<<23))
+#define GPIO_PUPDR12_PU             ((uint32_t)(1<<24))
+#define GPIO_PUPDR12_PD             ((uint32_t)(1<<25))
+#define GPIO_PUPDR13_PU             ((uint32_t)(1<<26))
+#define GPIO_PUPDR13_PD             ((uint32_t)(1<<27))
+#define GPIO_PUPDR14_PU             ((uint32_t)(1<<28))
+#define GPIO_PUPDR14_PD             ((uint32_t)(1<<29))
+#define GPIO_PUPDR15_PU             ((uint32_t)(1<<30))
+#define GPIO_PUPDR15_PD             ((uint32_t)(1<<31))
+// OSPEEDR
+// for n in $(seq 0 15); do echo "#define GPIO_OSPEEDR${n}_MED           ((uint32_t)(1<<$((n*2))))";
+// echo "#define GPIO_OSPEEDR${n}_HIGH          ((uint32_t)(3<<$((2*n))))"; done
+#define GPIO_OSPEEDR0_MED           ((uint32_t)(1<<0))
+#define GPIO_OSPEEDR0_HIGH          ((uint32_t)(3<<0))
+#define GPIO_OSPEEDR1_MED           ((uint32_t)(1<<2))
+#define GPIO_OSPEEDR1_HIGH          ((uint32_t)(3<<2))
+#define GPIO_OSPEEDR2_MED           ((uint32_t)(1<<4))
+#define GPIO_OSPEEDR2_HIGH          ((uint32_t)(3<<4))
+#define GPIO_OSPEEDR3_MED           ((uint32_t)(1<<6))
+#define GPIO_OSPEEDR3_HIGH          ((uint32_t)(3<<6))
+#define GPIO_OSPEEDR4_MED           ((uint32_t)(1<<8))
+#define GPIO_OSPEEDR4_HIGH          ((uint32_t)(3<<8))
+#define GPIO_OSPEEDR5_MED           ((uint32_t)(1<<10))
+#define GPIO_OSPEEDR5_HIGH          ((uint32_t)(3<<10))
+#define GPIO_OSPEEDR6_MED           ((uint32_t)(1<<12))
+#define GPIO_OSPEEDR6_HIGH          ((uint32_t)(3<<12))
+#define GPIO_OSPEEDR7_MED           ((uint32_t)(1<<14))
+#define GPIO_OSPEEDR7_HIGH          ((uint32_t)(3<<14))
+#define GPIO_OSPEEDR8_MED           ((uint32_t)(1<<16))
+#define GPIO_OSPEEDR8_HIGH          ((uint32_t)(3<<16))
+#define GPIO_OSPEEDR9_MED           ((uint32_t)(1<<18))
+#define GPIO_OSPEEDR9_HIGH          ((uint32_t)(3<<18))
+#define GPIO_OSPEEDR10_MED          ((uint32_t)(1<<20))
+#define GPIO_OSPEEDR10_HIGH         ((uint32_t)(3<<20))
+#define GPIO_OSPEEDR11_MED          ((uint32_t)(1<<22))
+#define GPIO_OSPEEDR11_HIGH         ((uint32_t)(3<<22))
+#define GPIO_OSPEEDR12_MED          ((uint32_t)(1<<24))
+#define GPIO_OSPEEDR12_HIGH         ((uint32_t)(3<<24))
+#define GPIO_OSPEEDR13_MED          ((uint32_t)(1<<26))
+#define GPIO_OSPEEDR13_HIGH         ((uint32_t)(3<<26))
+#define GPIO_OSPEEDR14_MED          ((uint32_t)(1<<28))
+#define GPIO_OSPEEDR14_HIGH         ((uint32_t)(3<<28))
+#define GPIO_OSPEEDR15_MED          ((uint32_t)(1<<30))
+#define GPIO_OSPEEDR15_HIGH         ((uint32_t)(3<<30))
+
+// clear MODER: ~GPIO_MODER_MODERXX_Msk, you should AND these
+#define MODER_CLR(n)    (~(3<<(n*2)))
+// _AI - analog inpt, _O - general output, _AF - alternate function
+// these should be OR'ed
+#define MODER_I(n)      (0)
+#define MODER_O(n)      (1<<(n*2))
+#define MODER_AF(n)     (2<<(n*2))
+#define MODER_AI(n)     (3<<(n*2))
+// OSPEED: low, medium, high
+#define OSPEED_CLR(n)   (~(3<<(n*2)))
+#define OSPEED_VLO(n)   (0)
+#define OSPEED_LO(n)    (1<<(n*2))
+#define OSPEED_MED(n)   (2<<(n*2))
+#define OSPEED_HI(n)    (3<<(n*2))
+// PUPD: pull up/down
+#define PUPD_CLR(n)     (~(3<<(n*2)))
+#define PUPD_PU(n)      (1<<(n*2))
+#define PUPD_PD(n)      (2<<(n*2))
+// OTYPER: bit==1 for OD
+#define OTYPER_PP(n)    0
+#define OTYPER_OD(n)    (1<<n)
+
+// AFR field: afr - AFR number, pin - pin (0..15)
+TRUE_INLINE uint32_t AFRf(uint8_t afr, uint8_t pin){
+    if(pin > 7) pin -= 8;
+    return (afr << (pin * 4));
+}
+
+
+/******************  FLASH Keys  **********************************************/
+#define RDP_Key                 ((uint16_t)0x00A5)
+#define FLASH_KEY1              ((uint32_t)0x45670123)
+#define FLASH_KEY2              ((uint32_t)0xCDEF89AB)
+#define FLASH_SIZE_REG          ((uint32_t)0x1FFFF7CC)
+
+/************************* ADC *************************/
+/* inner termometer calibration values
+ *         Temp = (V30 - Vsense)/Avg_Slope + 30
+ *         Avg_Slope = (V30 - V110) / (110 - 30)
+ */
+#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
+#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
+// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
+#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
+#define VDD_CALIB ((uint16_t) (330))
+#define VDD_APPLI ((uint16_t) (300))
+
+/************************* USART *************************/
+
+#define USART_CR2_ADD_SHIFT     24
+// set address/character match value
+#define USART_CR2_ADD_VAL(x)        ((x) << USART_CR2_ADD_SHIFT)
+
+/************************* IWDG *************************/
+#define IWDG_REFRESH      (uint32_t)(0x0000AAAA)
+#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
+#define IWDG_START        (uint32_t)(0x0000CCCC)
+
+
+//#define  do{}while(0)
+

G4:G431/inc/Fx/stm32g4xx.h

@@ -0,0 +1,266 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32G4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32G4xx device used in the target application
+  *              - To use or not the peripherals drivers in application code(i.e.
+  *                code will be based on direct access to peripherals registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32g4xx
+  * @{
+  */
+
+#ifndef __STM32G4xx_H
+#define __STM32G4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32G4)
+#define STM32G4
+#endif /* STM32G4 */
+
+/* Uncomment the line below according to the target STM32G4 device used in your
+   application
+  */
+
+#if !defined (STM32G431xx) && !defined (STM32G441xx) && !defined (STM32G471xx) && \
+    !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && \
+    !defined (STM32GBK1CB) && !defined (STM32G491xx) && !defined (STM32G4A1xx) && \
+    !defined (STM32G411xB) && !defined (STM32G411xC) && !defined (STM32G414xx)
+  /* #define STM32G411xB */   /*!< STM32G411xB Devices */
+  /* #define STM32G411xC */   /*!< STM32G411xC Devices */
+  /* #define STM32G414xx */   /*!< STM32G414xx Devices */
+  /* #define STM32G431xx */   /*!< STM32G431xx Devices */
+  /* #define STM32G441xx */   /*!< STM32G441xx Devices */
+  /* #define STM32G471xx */   /*!< STM32G471xx Devices */
+  /* #define STM32G473xx */   /*!< STM32G473xx Devices */
+  /* #define STM32G483xx */   /*!< STM32G483xx Devices */
+  /* #define STM32G474xx */   /*!< STM32G474xx Devices */
+  /* #define STM32G484xx */   /*!< STM32G484xx Devices */
+  /* #define STM32G491xx */   /*!< STM32G491xx Devices */
+  /* #define STM32G4A1xx */   /*!< STM32G4A1xx Devices */
+  /* #define STM32GBK1CB */   /*!< STM32GBK1CB Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.2.5
+  */
+#define __STM32G4_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32G4_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32G4_CMSIS_VERSION_SUB2   (0x05U) /*!< [15:8]  sub2 version */
+#define __STM32G4_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32G4_CMSIS_VERSION        ((__STM32G4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32G4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32G4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32G431xx)
+  #include "stm32g431xx.h"
+#elif defined(STM32G441xx)
+  #include "stm32g441xx.h"
+#elif defined(STM32G471xx)
+  #include "stm32g471xx.h"
+#elif defined(STM32G473xx)
+  #include "stm32g473xx.h"
+#elif defined(STM32G483xx)
+  #include "stm32g483xx.h"
+#elif defined(STM32G474xx)
+  #include "stm32g474xx.h"
+#elif defined(STM32G484xx)
+  #include "stm32g484xx.h"
+#elif defined(STM32G491xx)
+  #include "stm32g491xx.h"
+#elif defined(STM32G4A1xx)
+  #include "stm32g4a1xx.h"
+#elif defined(STM32GBK1CB)
+  #include "stm32gbk1cb.h"
+#elif defined(STM32G411xB)
+  #include "stm32g411xb.h"
+#elif defined(STM32G411xC)
+  #include "stm32g411xc.h"
+#elif defined(STM32G414xx)
+  #include "stm32g414xx.h"
+#else
+  #error "Please select first the target STM32G4xx device used in your application (in stm32g4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
+
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32G4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+

G4:G431/inc/Fx/vector.h

@@ -0,0 +1,141 @@
+/*
+ * Copyright 2026 Edward V. Emelianov <edward.emelianoff@gmail.com>.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#ifndef WEAK
+#define WEAK __attribute__((weak))
+#endif
+
+#include <stdint.h>
+extern uint32_t SysFreq;
+
+void WEAK reset_handler(void);
+void WEAK nmi_handler(void);
+void WEAK hard_fault_handler(void);
+void WEAK sv_call_handler(void);
+void WEAK pend_sv_handler(void);
+void WEAK sys_tick_handler(void);
+
+#ifndef STM32G4
+#error "Not supported platform, should be STM32G4!"
+#endif
+
+void WEAK wwdg_isr();
+void WEAK pvd_isr();
+void WEAK rtc_tamp_css_isr();
+void WEAK rtc_wkup_isr();
+void WEAK flash_isr();
+void WEAK rcc_isr();
+void WEAK exti0_isr();
+void WEAK exti1_isr();
+void WEAK exti2_isr();
+void WEAK exti3_isr();
+void WEAK exti4_isr();
+void WEAK dma1_channel1_isr();
+void WEAK dma1_channel2_isr();
+void WEAK dma1_channel3_isr();
+void WEAK dma1_channel4_isr();
+void WEAK dma1_channel5_isr();
+void WEAK dma1_channel6_isr();
+void WEAK dma1_channel7_isr();
+void WEAK adc12_isr();
+void WEAK usb_hp_isr();
+void WEAK usb_lp_isr();
+void WEAK fdcan1_it0_isr();
+void WEAK fdcan1_it1_isr();
+void WEAK exti9_5_isr();
+void WEAK tim1_brk_tim15_isr();
+void WEAK tim1_up_tim16_isr();
+void WEAK tim1_trg_tim17_isr();
+void WEAK tim1_cc_isr();
+void WEAK tim2_isr();
+void WEAK tim3_isr();
+void WEAK tim4_isr();
+void WEAK i2c1_ev_isr();
+void WEAK i2c1_er_isr();
+void WEAK i2c2_ev_isr();
+void WEAK i2c2_er_isr();
+void WEAK spi1_isr();
+void WEAK spi2_isr();
+void WEAK usart1_isr();
+void WEAK usart2_isr();
+void WEAK usart3_isr();
+void WEAK exti15_10_isr();
+void WEAK rtc_alarm_isr();
+void WEAK usb_wakeup_isr();
+void WEAK tim8_brk_isr();
+void WEAK tim8_up_isr();
+void WEAK tim8_trg_isr();
+void WEAK tim8_cc_isr();
+void WEAK adc3_isr();
+void WEAK fsmc_isr();
+void WEAK lptim1_isr();
+void WEAK tim5_isr();
+void WEAK spi3_isr();
+void WEAK uart4_isr();
+void WEAK uart5_isr();
+void WEAK tim6_dac13under_isr();
+void WEAK tim7_dac24under_isr();
+void WEAK dma2_channel1_isr();
+void WEAK dma2_channel2_isr();
+void WEAK dma2_channel3_isr();
+void WEAK dma2_channel4_isr();
+void WEAK dma2_channel5_isr();
+void WEAK adc4_isr();
+void WEAK adc5_isr();
+void WEAK ucpd1_isr();
+void WEAK comp123_isr();
+void WEAK comp456_isr();
+void WEAK comp7_isr();
+void WEAK hrtim_master_isr();
+void WEAK hrtim_tima_isr();
+void WEAK hrtim_timb_isr();
+void WEAK hrtim_timc_isr();
+void WEAK hrtim_timd_isr();
+void WEAK hrtim_time_isr();
+void WEAK hrtim_fault_isr();
+void WEAK hrtim_timf_isr();
+void WEAK crs_isr();
+void WEAK sai_isr();
+void WEAK tim20_brk_isr();
+void WEAK tim20_up_isr();
+void WEAK tim20_trg_isr();
+void WEAK tim20_cc_isr();
+void WEAK fpu_isr();
+void WEAK i2c4_ev_isr();
+void WEAK i2c4_er_isr();
+void WEAK spi4_isr();
+void WEAK aes_isr();
+void WEAK fdcan2_it0_isr();
+void WEAK fdcan2_it1_isr();
+void WEAK fdcan3_it0_isr();
+void WEAK fdcan3_it1_isr();
+void WEAK rng_isr();
+void WEAK lpuart_isr();
+void WEAK i2c3_ev_isr();
+void WEAK i2c3_er_isr();
+void WEAK dmamux_ovr_isr();
+void WEAK quadspi_isr();
+void WEAK dma1_channel8_isr();
+void WEAK dma2_channel6_isr();
+void WEAK dma2_channel7_isr();
+void WEAK dma2_channel8_isr();
+void WEAK cordic_isr();
+void WEAK fmac_isr();
+
+