mirror of
https://github.com/eddyem/stm32samples.git
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271 lines
12 KiB
C
271 lines
12 KiB
C
/*
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* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#pragma once
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#include "vector.h"
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#include "stm32g4xx.h"
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#include "common_macros.h"
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#define WAITWHILE(x) do{register uint32_t StartUpCounter = 0; while((x) && (++StartUpCounter < 0xfffff)){nop();}}while(0)
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//#define WAITWHILE(x) do{while(x){nop();}}while(0)
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TRUE_INLINE void StartHSE(){
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// ----- 1. Turn off PLL -----
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RCC->CR &= ~RCC_CR_PLLON;
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WAITWHILE(RCC->CR & RCC_CR_PLLRDY);
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// ----- 2. Turn on HSE -----
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// ðÁÒÁÍÅÔÒ isHSE ÉÇÎÏÒÉÒÕÅÔÓÑ ×ÓÅÇÄÁ ÉÓÐÏÌØÚÕÅÍ HSE ÐÏ ÕÓÌÏ×ÉÀ ÚÁÄÁÞÉ
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RCC->CR |= RCC_CR_HSEON;
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WAITWHILE(!(RCC->CR & RCC_CR_HSERDY));
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// ----- 3. Turn on power block PWR and setup for max freq (VOS = 0) -----
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RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
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PWR->CR1 &= ~(PWR_CR1_VOS_0 | PWR_CR1_VOS_1);
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WAITWHILE(PWR->SR2 & PWR_SR2_VOSF);
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// ----- 4. PLL setup (SYSCLK = 170 MHz) -----
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// HSE = 8 MHz, PLLM = 2, si PLL in = 4 MHz
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// PLLN = 85, so VCO = 4 * 85 = 340 MHz
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// PLLR = 2, so SYSCLK = 340 / 2 = 170 MHz
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//
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RCC->PLLCFGR =
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((2 - 1) << RCC_PLLCFGR_PLLM_Pos) | // PLLM = 2
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(85 << RCC_PLLCFGR_PLLN_Pos) | // PLLN = 85
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(0 << RCC_PLLCFGR_PLLR_Pos) | // PLLR = 2 (code 0)
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RCC_PLLCFGR_PLLREN | // turn on Rclk for SYSCLK
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RCC_PLLCFGR_PLLSRC_HSE; // source is HSE
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// ----- 5. Turn PLL on -----
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RCC->CR |= RCC_CR_PLLON;
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WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
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// ----- 6. Flash setup (4 wait cycles for 170 íçÃ) -----
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FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_4WS;
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// ----- 7. Switch from SYSCLK to PLL -----
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RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_Msk) | RCC_CFGR_SW_PLL;
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// ----- 8. Turn on HSI48 and wait until ready -----
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RCC->CRRCR |= RCC_CRRCR_HSI48ON;
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WAITWHILE(!(RCC->CRRCR & RCC_CRRCR_HSI48RDY));
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// ----- 9. Turn on CRS (Clock Recovery System) -----
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RCC->APB1ENR1 |= RCC_APB1ENR1_CRSEN;
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// ----- 10. Setup CRS for USB SOF sync -----
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CRS->CR &= ~(CRS_CR_CEN | CRS_CR_AUTOTRIMEN | CRS_CR_SWSYNC);
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CRS->CFGR &= ~CRS_CFGR_SYNCDIV_Msk;
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CRS->CFGR = (CRS->CFGR & ~CRS_CFGR_SYNCSRC_Msk) | (1 << CRS_CFGR_SYNCSRC_Pos);
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CRS->CFGR &= ~CRS_CFGR_SYNCDIV_Msk;
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CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
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// ----- 11. Select HSI48 as USB clock -----
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RCC->CCIPR &= ~RCC_CCIPR_CLK48SEL_Msk; // 00: HSI48 clock selected as 48 MHz clock
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SysFreq = 170000000UL;
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}
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/************************* GPIO *************************/
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/******************* Bit definition for GPIO_MODER register *****************/
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// _AI - analog inpt, _O - general output, _AF - alternate function
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#define GPIO_MODER_MODER0_AI ((uint32_t)0x00000003)
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#define GPIO_MODER_MODER0_O ((uint32_t)0x00000001)
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#define GPIO_MODER_MODER0_AF ((uint32_t)0x00000002)
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#define GPIO_MODER_MODER1_AI ((uint32_t)0x0000000C)
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#define GPIO_MODER_MODER1_O ((uint32_t)0x00000004)
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#define GPIO_MODER_MODER1_AF ((uint32_t)0x00000008)
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#define GPIO_MODER_MODER2_AI ((uint32_t)0x00000030)
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#define GPIO_MODER_MODER2_O ((uint32_t)0x00000010)
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#define GPIO_MODER_MODER2_AF ((uint32_t)0x00000020)
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#define GPIO_MODER_MODER3_AI ((uint32_t)0x000000C0)
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#define GPIO_MODER_MODER3_O ((uint32_t)0x00000040)
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#define GPIO_MODER_MODER3_AF ((uint32_t)0x00000080)
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#define GPIO_MODER_MODER4_AI ((uint32_t)0x00000300)
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#define GPIO_MODER_MODER4_O ((uint32_t)0x00000100)
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#define GPIO_MODER_MODER4_AF ((uint32_t)0x00000200)
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#define GPIO_MODER_MODER5_AI ((uint32_t)0x00000C00)
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#define GPIO_MODER_MODER5_O ((uint32_t)0x00000400)
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#define GPIO_MODER_MODER5_AF ((uint32_t)0x00000800)
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#define GPIO_MODER_MODER6_AI ((uint32_t)0x00003000)
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#define GPIO_MODER_MODER6_O ((uint32_t)0x00001000)
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#define GPIO_MODER_MODER6_AF ((uint32_t)0x00002000)
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#define GPIO_MODER_MODER7_AI ((uint32_t)0x0000C000)
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#define GPIO_MODER_MODER7_O ((uint32_t)0x00004000)
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#define GPIO_MODER_MODER7_AF ((uint32_t)0x00008000)
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#define GPIO_MODER_MODER8_AI ((uint32_t)0x00030000)
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#define GPIO_MODER_MODER8_O ((uint32_t)0x00010000)
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#define GPIO_MODER_MODER8_AF ((uint32_t)0x00020000)
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#define GPIO_MODER_MODER9_AI ((uint32_t)0x000C0000)
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#define GPIO_MODER_MODER9_O ((uint32_t)0x00040000)
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#define GPIO_MODER_MODER9_AF ((uint32_t)0x00080000)
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#define GPIO_MODER_MODER10_AI ((uint32_t)0x00300000)
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#define GPIO_MODER_MODER10_O ((uint32_t)0x00100000)
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#define GPIO_MODER_MODER10_AF ((uint32_t)0x00200000)
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#define GPIO_MODER_MODER11_AI ((uint32_t)0x00C00000)
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#define GPIO_MODER_MODER11_O ((uint32_t)0x00400000)
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#define GPIO_MODER_MODER11_AF ((uint32_t)0x00800000)
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#define GPIO_MODER_MODER12_AI ((uint32_t)0x03000000)
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#define GPIO_MODER_MODER12_O ((uint32_t)0x01000000)
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#define GPIO_MODER_MODER12_AF ((uint32_t)0x02000000)
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#define GPIO_MODER_MODER13_AI ((uint32_t)0x0C000000)
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#define GPIO_MODER_MODER13_O ((uint32_t)0x04000000)
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#define GPIO_MODER_MODER13_AF ((uint32_t)0x08000000)
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#define GPIO_MODER_MODER14_AI ((uint32_t)0x30000000)
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#define GPIO_MODER_MODER14_O ((uint32_t)0x10000000)
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#define GPIO_MODER_MODER14_AF ((uint32_t)0x20000000)
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#define GPIO_MODER_MODER15_AI ((uint32_t)0xC0000000)
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#define GPIO_MODER_MODER15_O ((uint32_t)0x40000000)
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#define GPIO_MODER_MODER15_AF ((uint32_t)0x80000000)
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/******************* Bit definition for GPIO_PUPDR register *****************/
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// no/pullup/pulldown/reserved
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// for n in $(seq 0 15); do echo "#define GPIO_PUPDR${n}_PU ((uint32_t)(1<<$((n*2))))";
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// echo "#define GPIO_PUPDR${n}_PD ((uint32_t)(1<<$((n*2+1))))"; done
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// alt+select column -> delete
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#define GPIO_PUPDR0_PU ((uint32_t)(1<<0))
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#define GPIO_PUPDR0_PD ((uint32_t)(1<<1))
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#define GPIO_PUPDR1_PU ((uint32_t)(1<<2))
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#define GPIO_PUPDR1_PD ((uint32_t)(1<<3))
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#define GPIO_PUPDR2_PU ((uint32_t)(1<<4))
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#define GPIO_PUPDR2_PD ((uint32_t)(1<<5))
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#define GPIO_PUPDR3_PU ((uint32_t)(1<<6))
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#define GPIO_PUPDR3_PD ((uint32_t)(1<<7))
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#define GPIO_PUPDR4_PU ((uint32_t)(1<<8))
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#define GPIO_PUPDR4_PD ((uint32_t)(1<<9))
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#define GPIO_PUPDR5_PU ((uint32_t)(1<<10))
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#define GPIO_PUPDR5_PD ((uint32_t)(1<<11))
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#define GPIO_PUPDR6_PU ((uint32_t)(1<<12))
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#define GPIO_PUPDR6_PD ((uint32_t)(1<<13))
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#define GPIO_PUPDR7_PU ((uint32_t)(1<<14))
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#define GPIO_PUPDR7_PD ((uint32_t)(1<<15))
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#define GPIO_PUPDR8_PU ((uint32_t)(1<<16))
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#define GPIO_PUPDR8_PD ((uint32_t)(1<<17))
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#define GPIO_PUPDR9_PU ((uint32_t)(1<<18))
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#define GPIO_PUPDR9_PD ((uint32_t)(1<<19))
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#define GPIO_PUPDR10_PU ((uint32_t)(1<<20))
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#define GPIO_PUPDR10_PD ((uint32_t)(1<<21))
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#define GPIO_PUPDR11_PU ((uint32_t)(1<<22))
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#define GPIO_PUPDR11_PD ((uint32_t)(1<<23))
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#define GPIO_PUPDR12_PU ((uint32_t)(1<<24))
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#define GPIO_PUPDR12_PD ((uint32_t)(1<<25))
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#define GPIO_PUPDR13_PU ((uint32_t)(1<<26))
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#define GPIO_PUPDR13_PD ((uint32_t)(1<<27))
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#define GPIO_PUPDR14_PU ((uint32_t)(1<<28))
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#define GPIO_PUPDR14_PD ((uint32_t)(1<<29))
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#define GPIO_PUPDR15_PU ((uint32_t)(1<<30))
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#define GPIO_PUPDR15_PD ((uint32_t)(1<<31))
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// OSPEEDR
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// for n in $(seq 0 15); do echo "#define GPIO_OSPEEDR${n}_MED ((uint32_t)(1<<$((n*2))))";
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// echo "#define GPIO_OSPEEDR${n}_HIGH ((uint32_t)(3<<$((2*n))))"; done
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#define GPIO_OSPEEDR0_MED ((uint32_t)(1<<0))
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#define GPIO_OSPEEDR0_HIGH ((uint32_t)(3<<0))
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#define GPIO_OSPEEDR1_MED ((uint32_t)(1<<2))
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#define GPIO_OSPEEDR1_HIGH ((uint32_t)(3<<2))
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#define GPIO_OSPEEDR2_MED ((uint32_t)(1<<4))
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#define GPIO_OSPEEDR2_HIGH ((uint32_t)(3<<4))
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#define GPIO_OSPEEDR3_MED ((uint32_t)(1<<6))
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#define GPIO_OSPEEDR3_HIGH ((uint32_t)(3<<6))
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#define GPIO_OSPEEDR4_MED ((uint32_t)(1<<8))
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#define GPIO_OSPEEDR4_HIGH ((uint32_t)(3<<8))
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#define GPIO_OSPEEDR5_MED ((uint32_t)(1<<10))
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#define GPIO_OSPEEDR5_HIGH ((uint32_t)(3<<10))
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#define GPIO_OSPEEDR6_MED ((uint32_t)(1<<12))
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#define GPIO_OSPEEDR6_HIGH ((uint32_t)(3<<12))
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#define GPIO_OSPEEDR7_MED ((uint32_t)(1<<14))
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#define GPIO_OSPEEDR7_HIGH ((uint32_t)(3<<14))
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#define GPIO_OSPEEDR8_MED ((uint32_t)(1<<16))
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#define GPIO_OSPEEDR8_HIGH ((uint32_t)(3<<16))
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#define GPIO_OSPEEDR9_MED ((uint32_t)(1<<18))
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#define GPIO_OSPEEDR9_HIGH ((uint32_t)(3<<18))
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#define GPIO_OSPEEDR10_MED ((uint32_t)(1<<20))
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#define GPIO_OSPEEDR10_HIGH ((uint32_t)(3<<20))
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#define GPIO_OSPEEDR11_MED ((uint32_t)(1<<22))
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#define GPIO_OSPEEDR11_HIGH ((uint32_t)(3<<22))
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#define GPIO_OSPEEDR12_MED ((uint32_t)(1<<24))
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#define GPIO_OSPEEDR12_HIGH ((uint32_t)(3<<24))
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#define GPIO_OSPEEDR13_MED ((uint32_t)(1<<26))
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#define GPIO_OSPEEDR13_HIGH ((uint32_t)(3<<26))
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#define GPIO_OSPEEDR14_MED ((uint32_t)(1<<28))
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#define GPIO_OSPEEDR14_HIGH ((uint32_t)(3<<28))
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#define GPIO_OSPEEDR15_MED ((uint32_t)(1<<30))
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#define GPIO_OSPEEDR15_HIGH ((uint32_t)(3<<30))
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// clear MODER: ~GPIO_MODER_MODERXX_Msk, you should AND these
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#define MODER_CLR(n) (~(3<<(n*2)))
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// _AI - analog inpt, _O - general output, _AF - alternate function
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// these should be OR'ed
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#define MODER_I(n) (0)
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#define MODER_O(n) (1<<(n*2))
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#define MODER_AF(n) (2<<(n*2))
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#define MODER_AI(n) (3<<(n*2))
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// OSPEED: low, medium, high
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#define OSPEED_CLR(n) (~(3<<(n*2)))
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#define OSPEED_VLO(n) (0)
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#define OSPEED_LO(n) (1<<(n*2))
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#define OSPEED_MED(n) (2<<(n*2))
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#define OSPEED_HI(n) (3<<(n*2))
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// PUPD: pull up/down
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#define PUPD_CLR(n) (~(3<<(n*2)))
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#define PUPD_PU(n) (1<<(n*2))
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#define PUPD_PD(n) (2<<(n*2))
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// OTYPER: bit==1 for OD
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#define OTYPER_PP(n) 0
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#define OTYPER_OD(n) (1<<n)
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// AFR field: afr - AFR number, pin - pin (0..15)
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TRUE_INLINE uint32_t AFRf(uint8_t afr, uint8_t pin){
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if(pin > 7) pin -= 8;
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return (afr << (pin * 4));
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}
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/****************** FLASH Keys **********************************************/
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#define RDP_Key ((uint16_t)0x00A5)
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#define FLASH_KEY1 ((uint32_t)0x45670123)
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#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
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#define FLASH_SIZE_REG ((uint32_t)0x1FFFF7CC)
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/************************* ADC *************************/
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/* inner termometer calibration values
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* Temp = (V30 - Vsense)/Avg_Slope + 30
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* Avg_Slope = (V30 - V110) / (110 - 30)
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*/
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#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
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#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
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// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
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#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
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#define VDD_CALIB ((uint16_t) (330))
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#define VDD_APPLI ((uint16_t) (300))
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/************************* USART *************************/
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#define USART_CR2_ADD_SHIFT 24
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// set address/character match value
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#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
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/************************* IWDG *************************/
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#define IWDG_REFRESH (uint32_t)(0x0000AAAA)
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#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
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#define IWDG_START (uint32_t)(0x0000CCCC)
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//#define do{}while(0)
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