eddy/stm32samples
1
0
Fork 0
mirror of https://github.com/eddyem/stm32samples.git synced 2026-02-28 11:54:30 +03:00
Code Issues Packages Projects Releases Wiki Activity

Always working, but some of schematics was wrong

Browse Source
This commit is contained in:
Edward Emelianov
2024-06-03 20:25:53 +03:00
parent f127a3ce1a
commit 6cb98bb7ed
22 changed files with 273 additions and 90 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
F1:F103/FX3U/adc.c
View File

@@ -36,8 +36,9 @@ void adc_setup(){
// sampling time - 239.5 cycles for channels 0, 16 and 17
ADC1->SMPR2 = ADC_SMPR2_SMP0;
ADC1->SMPR1 = ADC_SMPR1_SMP16 | ADC_SMPR1_SMP17;
// sequence order: 0 -> 16 -> 17
ADC1->SQR3 = (0 << 0) | (16<<5) | (17 << 10);
// sequence order: 1[0]->3[1]->14[2]->15[3]->10[4]->11[5] -> 16[tsen] -> 17[vdd]
ADC1->SQR3 = (1 << 0) | (3<<5) | (14 << 10) | (15 << 15) | (10 << 20) | (11 < 25);
ADC1->SQR2 = (16 << 0) | (17 << 5);
ADC1->SQR1 = (ADC_CHANNELS - 1) << 20; // amount of conversions
ADC1->CR1 = ADC_CR1_SCAN; // scan mode
// DMA, continuous mode; enable vref & Tsens; enable SWSTART as trigger