mirror of
https://github.com/eddyem/stm32samples.git
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112 lines
4.1 KiB
C
112 lines
4.1 KiB
C
/*
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* This file is part of the fx3u project.
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* Copyright 2024 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adc.h"
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uint16_t ADC_array[ADC_CHANNELS*9];
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void adc_setup(){
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uint32_t ctr = 0;
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// Enable clocking
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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__DSB();
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// DMA configuration
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DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR));
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array);
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DMA1_Channel1->CNDTR = ADC_CHANNELS * 9;
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DMA1_Channel1->CCR = DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0
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| DMA_CCR_CIRC | DMA_CCR_PL | DMA_CCR_EN;
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RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_ADCPRE)) | RCC_CFGR_ADCPRE_DIV8; // ADC clock = RCC / 8
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// sampling time - 239.5 cycles for channels 0, 16 and 17
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ADC1->SMPR2 = ADC_SMPR2_SMP0;
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ADC1->SMPR1 = ADC_SMPR1_SMP16 | ADC_SMPR1_SMP17;
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// sequence order: 1[0]->3[1]->14[2]->15[3]->10[4]->11[5] -> 16[tsen] -> 17[vdd]
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ADC1->SQR3 = (1 << 0) | (3<<5) | (14 << 10) | (15 << 15) | (10 << 20) | (11 < 25);
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ADC1->SQR2 = (16 << 0) | (17 << 5);
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ADC1->SQR1 = (ADC_CHANNELS - 1) << 20; // amount of conversions
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ADC1->CR1 = ADC_CR1_SCAN; // scan mode
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// DMA, continuous mode; enable vref & Tsens; enable SWSTART as trigger
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ADC1->CR2 = ADC_CR2_DMA | ADC_CR2_TSVREFE | ADC_CR2_CONT | ADC_CR2_EXTSEL | ADC_CR2_EXTTRIG;
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// wake up ADC
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ADC1->CR2 |= ADC_CR2_ADON;
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__DSB();
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// wait for Tstab - at least 1us
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while(++ctr < 0xff) nop();
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// calibration
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ADC1->CR2 |= ADC_CR2_RSTCAL;
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ctr = 0; while((ADC1->CR2 & ADC_CR2_RSTCAL) && ++ctr < 0xfffff);
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ADC1->CR2 |= ADC_CR2_CAL;
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ctr = 0; while((ADC1->CR2 & ADC_CR2_CAL) && ++ctr < 0xfffff);
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// clear possible errors and start
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ADC1->SR = 0;
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ADC1->CR2 |= ADC_CR2_SWSTART;
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}
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/**
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* @brief getADCval - calculate median value for `nch` channel
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* @param nch - number of channel
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* @return
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*/
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uint16_t getADCval(int nch){
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int i, addr = nch;
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#define PIX_SORT(a,b) { if ((a)>(b)) PIX_SWAP((a),(b)); }
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#define PIX_SWAP(a,b) { register uint16_t temp=(a);(a)=(b);(b)=temp; }
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uint16_t p[9];
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for(i = 0; i < 9; ++i, addr += ADC_CHANNELS){ // first we should prepare array for optmed
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p[i] = ADC_array[addr];
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}
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PIX_SORT(p[1], p[2]) ; PIX_SORT(p[4], p[5]) ; PIX_SORT(p[7], p[8]) ;
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PIX_SORT(p[0], p[1]) ; PIX_SORT(p[3], p[4]) ; PIX_SORT(p[6], p[7]) ;
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PIX_SORT(p[1], p[2]) ; PIX_SORT(p[4], p[5]) ; PIX_SORT(p[7], p[8]) ;
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PIX_SORT(p[0], p[3]) ; PIX_SORT(p[5], p[8]) ; PIX_SORT(p[4], p[7]) ;
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PIX_SORT(p[3], p[6]) ; PIX_SORT(p[1], p[4]) ; PIX_SORT(p[2], p[5]) ;
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PIX_SORT(p[4], p[7]) ; PIX_SORT(p[4], p[2]) ; PIX_SORT(p[6], p[4]) ;
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PIX_SORT(p[4], p[2]) ;
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return p[4];
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#undef PIX_SORT
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#undef PIX_SWAP
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}
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// get voltage @input nch (1/100V)
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uint32_t getADCvoltage(int nch){
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uint32_t v = getADCval(nch);
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v *= getVdd();
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v /= 0xfff; // 12bit ADC
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return v;
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}
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// return MCU temperature (degrees of celsius * 10)
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int32_t getMCUtemp(){
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// Temp = (V25 - Vsense)/Avg_Slope + 25
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// V_25 = 1.45V, Slope = 4.3e-3
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int32_t Vsense = getVdd() * getADCval(ADC_CH_TSEN);
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int32_t temperature = 593920 - Vsense; // 593920 == 145*4096
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temperature /= 172; // == /(4096*10*4.3e-3), 10 - to convert from *100 to *10
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temperature += 250;
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return(temperature);
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}
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// return Vdd * 100 (V)
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uint32_t getVdd(){
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uint32_t vdd = 120 * 4096; // 1.2V
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vdd /= getADCval(ADC_CH_VDD);
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return vdd;
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}
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