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https://github.com/eddyem/stm32samples.git
synced 2026-03-21 17:21:04 +03:00
add simple blink for ST32F103-nolib (Makefile still under construction!)
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@@ -115,9 +115,8 @@ TRUE_INLINE void StartHSE()
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/* Enable PLL2 */
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RCC->CR |= RCC_CR_PLL2ON;
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/* Wait till PLL2 is ready */
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while((RCC->CR & RCC_CR_PLL2RDY) == 0)
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{
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}
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StartUpCounter = 0;
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while((RCC->CR & RCC_CR_PLL2RDY) == 0 && ++StartUpCounter < 1000){}
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/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
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RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
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@@ -134,18 +133,16 @@ TRUE_INLINE void StartHSE()
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0)
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{
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}
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StartUpCounter = 0;
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while((RCC->CR & RCC_CR_PLLRDY) == 0 && ++StartUpCounter < 1000){}
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/* Select PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
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{
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}
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StartUpCounter = 0;
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while(((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) && ++StartUpCounter < 1000){}
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}
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else // HSE fails to start-up
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{
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@@ -451,7 +451,7 @@ typedef enum IRQn
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*/
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#include "core_cm3.h"
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//#include "system_stm32f10x.h"
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#include <stdint.h>
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/** @addtogroup Exported_types
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@@ -22,14 +22,6 @@
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#ifndef VECTOR_H
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#define VECTOR_H
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typedef void (*vector_table_entry_t)(void);
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typedef void (*funcp_t) (void);
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/* Symbols exported by the linker script(s): */
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extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
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extern funcp_t __preinit_array_start, __preinit_array_end;
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extern funcp_t __init_array_start, __init_array_end;
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extern funcp_t __fini_array_start, __fini_array_end;
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#ifndef WEAK
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#define WEAK __attribute__((weak))
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#endif
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