From 4defefb860b6f2eb07a552546f2e82fd991ff7f4 Mon Sep 17 00:00:00 2001 From: eddyem Date: Mon, 5 Nov 2018 11:42:01 +0300 Subject: [PATCH] add simple blink for ST32F103-nolib (Makefile still under construction!) --- F0-nolib/Snippets/fallthru | 1 + F0-nolib/inc/startup/vector.c | 96 +- F0-nolib/morze/morze.bin | Bin 2216 -> 2288 bytes F1-nolib/STM32F103R_board.readme | 9 + F1-nolib/inc/Fx/stm32f1.h | 15 +- F1-nolib/inc/Fx/stm32f10x.h | 2 +- F1-nolib/inc/Fx/vector.h | 8 - F1-nolib/inc/README | 1 - F1-nolib/inc/ld/stm32f01234.ld | 169 +-- F1-nolib/inc/startup/vector.c | 1260 +++++++++++------ F1-nolib/led_blink/Makefile | 35 +- F1-nolib/led_blink/README | 6 +- F1-nolib/led_blink/blink.bin | Bin 732 -> 1516 bytes .../led_blink/{systick_blink.c_bkp => main.c} | 76 +- F1-nolib/led_blink/systick_blink.c | 31 - F1-nolib/led_blink/systick_blink.c_notwork | 30 - 16 files changed, 1024 insertions(+), 715 deletions(-) create mode 100644 F0-nolib/Snippets/fallthru create mode 100644 F1-nolib/STM32F103R_board.readme delete mode 100644 F1-nolib/inc/README rename F1-nolib/led_blink/{systick_blink.c_bkp => main.c} (55%) delete mode 100644 F1-nolib/led_blink/systick_blink.c delete mode 100644 F1-nolib/led_blink/systick_blink.c_notwork diff --git a/F0-nolib/Snippets/fallthru b/F0-nolib/Snippets/fallthru new file mode 100644 index 0000000..5db2140 --- /dev/null +++ b/F0-nolib/Snippets/fallthru @@ -0,0 +1 @@ +__attribute__((fallthrough)); diff --git a/F0-nolib/inc/startup/vector.c b/F0-nolib/inc/startup/vector.c index acba5c2..45a2cc5 100644 --- a/F0-nolib/inc/startup/vector.c +++ b/F0-nolib/inc/startup/vector.c @@ -23,41 +23,73 @@ * used by the startup code generator (vector.c) to set the initial values for * the interrupt handling routines to the chip family specific _isr weak * symbols. */ +#define NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_RTC_IRQ 2 +#define NVIC_FLASH_IRQ 3 +#define NVIC_RCC_IRQ 4 +#define NVIC_EXTI0_1_IRQ 5 +#define NVIC_EXTI2_3_IRQ 6 +#define NVIC_EXTI4_15_IRQ 7 +#define NVIC_TSC_IRQ 8 +#define NVIC_DMA1_CHANNEL1_IRQ 9 +#define NVIC_DMA1_CHANNEL2_3_IRQ 10 +#define NVIC_DMA1_CHANNEL4_5_IRQ 11 +#define NVIC_ADC_COMP_IRQ 12 +#define NVIC_TIM1_BRK_UP_TRG_COM_IRQ 13 +#define NVIC_TIM1_CC_IRQ 14 +#define NVIC_TIM2_IRQ 15 +#define NVIC_TIM3_IRQ 16 +#define NVIC_TIM6_DAC_IRQ 17 +#define NVIC_TIM7_IRQ 18 +#define NVIC_TIM14_IRQ 19 +#define NVIC_TIM15_IRQ 20 +#define NVIC_TIM16_IRQ 21 +#define NVIC_TIM17_IRQ 22 +#define NVIC_I2C1_IRQ 23 +#define NVIC_I2C2_IRQ 24 +#define NVIC_SPI1_IRQ 25 +#define NVIC_SPI2_IRQ 26 +#define NVIC_USART1_IRQ 27 +#define NVIC_USART2_IRQ 28 +#define NVIC_USART3_4_IRQ 29 +#define NVIC_CEC_CAN_IRQ 30 +#define NVIC_USB_IRQ 31 #define NVIC_IRQ_COUNT 32 #define F0_IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - rtc_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_1_isr, \ - exti2_3_isr, \ - exti4_15_isr, \ - tsc_isr, \ - dma1_channel1_isr, \ - dma1_channel2_3_isr, \ - dma1_channel4_5_isr, \ - adc_comp_isr, \ - tim1_brk_up_trg_com_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - tim14_isr, \ - tim15_isr, \ - tim16_isr, \ - tim17_isr, \ - i2c1_isr, \ - i2c2_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_4_isr, \ - cec_can_isr, \ - usb_isr + [NVIC_WWDG_IRQ] = wwdg_isr, \ + [NVIC_PVD_IRQ] = pvd_isr, \ + [NVIC_RTC_IRQ] = rtc_isr, \ + [NVIC_FLASH_IRQ] = flash_isr, \ + [NVIC_RCC_IRQ] = rcc_isr, \ + [NVIC_EXTI0_1_IRQ] = exti0_1_isr, \ + [NVIC_EXTI2_3_IRQ] = exti2_3_isr, \ + [NVIC_EXTI4_15_IRQ] = exti4_15_isr, \ + [NVIC_TSC_IRQ] = tsc_isr, \ + [NVIC_DMA1_CHANNEL1_IRQ] = dma1_channel1_isr, \ + [NVIC_DMA1_CHANNEL2_3_IRQ] = dma1_channel2_3_isr, \ + [NVIC_DMA1_CHANNEL4_5_IRQ] = dma1_channel4_5_isr, \ + [NVIC_ADC_COMP_IRQ] = adc_comp_isr, \ + [NVIC_TIM1_BRK_UP_TRG_COM_IRQ] = tim1_brk_up_trg_com_isr, \ + [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, \ + [NVIC_TIM2_IRQ] = tim2_isr, \ + [NVIC_TIM3_IRQ] = tim3_isr, \ + [NVIC_TIM6_DAC_IRQ] = tim6_dac_isr, \ + [NVIC_TIM7_IRQ] = tim7_isr, \ + [NVIC_TIM14_IRQ] = tim14_isr, \ + [NVIC_TIM15_IRQ] = tim15_isr, \ + [NVIC_TIM16_IRQ] = tim16_isr, \ + [NVIC_TIM17_IRQ] = tim17_isr, \ + [NVIC_I2C1_IRQ] = i2c1_isr, \ + [NVIC_I2C2_IRQ] = i2c2_isr, \ + [NVIC_SPI1_IRQ] = spi1_isr, \ + [NVIC_SPI2_IRQ] = spi2_isr, \ + [NVIC_USART1_IRQ] = usart1_isr, \ + [NVIC_USART2_IRQ] = usart2_isr, \ + [NVIC_USART3_4_IRQ] = usart3_4_isr, \ + [NVIC_CEC_CAN_IRQ] = cec_can_isr, \ + [NVIC_USB_IRQ] = usb_isr typedef void (*vector_table_entry_t)(void); typedef void (*funcp_t) (void); diff --git a/F0-nolib/morze/morze.bin b/F0-nolib/morze/morze.bin index a4051d86c69417efa6131150c76ed9689d232fb7..8db938e4cc0452a565baf0e57e127f44f5d8657b 100755 GIT binary patch delta 1273 zcmah}ZA@EL7=F*aZE0a$+g*_MwjFIR-GGjz&@mIr0^VEBXm5w>J`~0l53+>I)X1*| z6BnB34>$NRa+M62&KQg=%mlmC#5j`1#2-tHxtDE8S&74FR*k{buZ*f2-VT3gGTlj@ zocFxXd!Cc`IVWe%R> zIPpAw23Q!w;Kh;CU}(OGKenI4<*So^ac2U%lfB7H$&*F~Qv6oM(0pPL`}v=gN&nXx z`4aq-E~o-Vp<{5v-UkB_LwK^qofI*eW`+%`h%1j(3>!r@3BKthz0h{;Jf6bu;dxwG zq{Zo)syFWDGq}ooHWntZ~W@xq>bi2*-JZL@Jpgr0fAczJqLx;#U$RS z)2)Og=LnJ^(4?5X;Vvk=Ui>`Yi<@GMG$t?vR)Z4qLgAGn)D=}~e%Te2HtxOifSS*Z z1PKH(N-r+8?2jELj8swDF$00Le4nary_~0jp7Lp$-xPW55z$nLOdaXNdhhnGFo6Ot z3V05?p&sZ9P-uU6LMJ|>86hvwM@(7GjW*2jK#@v>66z(iRR8={0*e`TyHIuV>8l~I-0BqZ2K()XEXS{~CSMt6vXbZ%(I z;JM|G`Ma%BlLU26wYF;<^u3%|`?OQKh6f@L02Ofzaf&nJGpY8*Cstl|l_kc}EOy0n zsgsd`qve5WrLb5nx}S6l5`wEjfcT(HGxF8-7qv`C zTLWi@;l&KrX%4x7>R3VGd7xQ0yg!2*VgYfQXO?aX-`f2^b9K?Tg$nnY-3qX(3z;M; z|!D@J7$^<|Vp`abK4&8>&ayID6m#oSSZ0W8V_i?8YxH?7zbQ zp;pDK{*&9d*LdF&w>*-6U)!6(+PC2;z3}g}yY*0;b1D882DL;XZE1LN*$jGN3()Xk zS&Lc))_skp-Dt1fx_75kLk6Yi$OqCTl9#M|?htF}D*uaWsYNY~DC(%}=ycG#+{?gy v+4JK;UFa@L?=EI(PS>{CGTYJUFgfIfvPv^F{HFe%*Tc_wAFRvQ%kKOISY(83 delta 1259 zcmah}eP~-%6hAjFNngKg!s|+2lcq0uC2jY*YE9}N#?9=#dfVjL*sn=HHoWOJ`XUbc zhe`)ZB17oZLdTP`Ev{24I_NgET2Ne}DhOg_$?8T!JEkZ+h8sRN_YprDU%L61&|Ua( z&$;J!&$;KEd#`RkWw(J1xL2(}A2jfifg^Tj0tyP;9|gG+-7^*l55gJCgE^b~NC17= z{C_9<{5KfpCD%Kc8XL!+;Og8Sp(KlVHc~pu%GF8m9#0Z%J~xT=g{sI9tj=B9z3dnq zgJxG6d4PM-{mUE*?1zWsZR`Qq!%o%7^>z`Zf2!XHu4I4mWYX&Ip-+f6_>6?D+ou9e zN%!a_jq04Ob&cQB7IC==3T5Gzihx!p(On<-IB6x;AGb;Uv0?c*CVUq@6pP7+hNt); z_;bKMs$ywY^-@)dW<@s0AbgyrPJ#YxE{XFE<~3e%jv*C<@^rbUu>ivk$13G5;UkY6BbDJSVHG5?B*}lpsp@%iccMYo=U3w?D|fLzVppKC zCgY3xI$9K;JOOP3zGs}uIlQ+G1jrzsAvJR9t<>C;O^&q@S9|vaI*r|(t8@F?gk2?q zGp#SMvO{@Iw5=cx>ew(7rAdpzbQqqxvl{YL$}9n1>SoAQtt?t@M49j!L6$UBS0TGd zg#_=&}Pw7l21Tx|1P-g5VQLAYQN<^?mv7 z3&x7y(1HI|GaHq1fhn|xfLk|i;As0IZiqC7-w?|#T$BztD9?ms2cK+iz2-pQp)Y5| zzcM{6uU@r!63(bgo)$|k+>)T~y5kIuT4&&9KMEXeKP~1mRne+Vtob|5|5QY6n=lr! z@jY;b*YK{=|&{J%^QcFgZ z=g5c3NunvXz!hTipAc_mD)?#1_Soy}VU`I|LUq<%3;d@v3cL^J`+w^)`)9;IGgRFN mlE20q`qpvX0b4D`>ss1CR |= RCC_CR_PLL2ON; /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } + StartUpCounter = 0; + while((RCC->CR & RCC_CR_PLL2RDY) == 0 && ++StartUpCounter < 1000){} /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); @@ -134,18 +133,16 @@ TRUE_INLINE void StartHSE() RCC->CR |= RCC_CR_PLLON; /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } + StartUpCounter = 0; + while((RCC->CR & RCC_CR_PLLRDY) == 0 && ++StartUpCounter < 1000){} /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } + StartUpCounter = 0; + while(((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) && ++StartUpCounter < 1000){} } else // HSE fails to start-up { diff --git a/F1-nolib/inc/Fx/stm32f10x.h b/F1-nolib/inc/Fx/stm32f10x.h index 144fe94..7c9753d 100644 --- a/F1-nolib/inc/Fx/stm32f10x.h +++ b/F1-nolib/inc/Fx/stm32f10x.h @@ -451,7 +451,7 @@ typedef enum IRQn */ #include "core_cm3.h" -//#include "system_stm32f10x.h" + #include /** @addtogroup Exported_types diff --git a/F1-nolib/inc/Fx/vector.h b/F1-nolib/inc/Fx/vector.h index 8e8792f..2e59c8f 100644 --- a/F1-nolib/inc/Fx/vector.h +++ b/F1-nolib/inc/Fx/vector.h @@ -22,14 +22,6 @@ #ifndef VECTOR_H #define VECTOR_H -typedef void (*vector_table_entry_t)(void); -typedef void (*funcp_t) (void); -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; -extern funcp_t __preinit_array_start, __preinit_array_end; -extern funcp_t __init_array_start, __init_array_end; -extern funcp_t __fini_array_start, __fini_array_end; - #ifndef WEAK #define WEAK __attribute__((weak)) #endif diff --git a/F1-nolib/inc/README b/F1-nolib/inc/README deleted file mode 100644 index 5fffda6..0000000 --- a/F1-nolib/inc/README +++ /dev/null @@ -1 +0,0 @@ -including files \ No newline at end of file diff --git a/F1-nolib/inc/ld/stm32f01234.ld b/F1-nolib/inc/ld/stm32f01234.ld index 3fc2ccb..76abafe 100644 --- a/F1-nolib/inc/ld/stm32f01234.ld +++ b/F1-nolib/inc/ld/stm32f01234.ld @@ -1,106 +1,87 @@ /* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ +******************************************************************************** +* * +* Copyright (c) 2017 Andrea Loi * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included * +* in all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +******************************************************************************** +*/ -/* Generic linker script for STM32 targets using libopencm3. */ -/* Memory regions must be defined in the ld script which includes this one. */ -/* Enforce emmition of the vector table. */ -EXTERN (vector_table) +/******************************************************************************/ +/* DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING! */ +/******************************************************************************/ + +/* _isrvectors_tend = 0x00000150; - different for different series */ -/* Define the entry point of the output file. */ ENTRY(reset_handler) -/* Define sections. */ -SECTIONS -{ - .text : { - *(.vectors) /* Vector table */ - *(.text*) /* Program code */ - . = ALIGN(4); - *(.rodata*) /* Read-only data */ - . = ALIGN(4); - } >rom +SECTIONS { + .vector_table 0x08000000 : + { + _sisrvectors = .; + KEEP(*(.vector_table)) + /* ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!"); */ + _eisrvectors = .; + } >rom - /* C++ Static constructors/destructors, also used for __attribute__ - * ((constructor)) and the likes */ - .preinit_array : { - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - } >rom - .init_array : { - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - } >rom - .fini_array : { - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - } >rom + .text : + { + . = ALIGN(4); + _stext = .; + *(.text*) + *(.rodata*) + . = ALIGN(4); + _etext = .; + } >rom + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >rom + + .ARM : { + *(.ARM.exidx*) + } >rom + + .data : + { + . = ALIGN(4); + _sdata = .; + *(.data*) + . = ALIGN(4); + _edata = .; + } >ram AT >rom - /* - * Another section used by C++ stuff, appears when using newlib with - * 64bit (long long) printf support - */ - .ARM.extab : { - *(.ARM.extab*) - } >rom - .ARM.exidx : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >rom + _ldata = LOADADDR(.data); - . = ALIGN(4); - _etext = .; - - .data : { - _data = .; - *(.data*) /* Read-write initialized data */ - . = ALIGN(4); - _edata = .; - } >ram AT >rom - _data_loadaddr = LOADADDR(.data); - - .bss : { - *(.bss*) /* Read-write zero initialized data */ - *(COMMON) - . = ALIGN(4); - _ebss = .; - } >ram - - /* - * The .eh_frame section appears to be used for C++ exception handling. - * You may need to fix this if you're using C++. - */ - /DISCARD/ : { *(.eh_frame) } - - . = ALIGN(4); - end = .; + .bss : + { + . = ALIGN(4); + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram } -PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); - +PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); \ No newline at end of file diff --git a/F1-nolib/inc/startup/vector.c b/F1-nolib/inc/startup/vector.c index 197bf12..aa203cf 100644 --- a/F1-nolib/inc/startup/vector.c +++ b/F1-nolib/inc/startup/vector.c @@ -19,393 +19,855 @@ */ #include "vector.h" +typedef void (*vector_table_entry_t)(void); +typedef void (*funcp_t) (void); + +void main(void); +void blocking_handler(void); +void null_handler(void); + /* Initialization template for the interrupt vector table. This definition is * used by the startup code generator (vector.c) to set the initial values for * the interrupt handling routines to the chip family specific _isr weak * symbols. */ #if defined STM32F0 #include "stm32f0xx.h" + +#define NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_RTC_IRQ 2 +#define NVIC_FLASH_IRQ 3 +#define NVIC_RCC_IRQ 4 +#define NVIC_EXTI0_1_IRQ 5 +#define NVIC_EXTI2_3_IRQ 6 +#define NVIC_EXTI4_15_IRQ 7 +#define NVIC_TSC_IRQ 8 +#define NVIC_DMA1_CHANNEL1_IRQ 9 +#define NVIC_DMA1_CHANNEL2_3_IRQ 10 +#define NVIC_DMA1_CHANNEL4_5_IRQ 11 +#define NVIC_ADC_COMP_IRQ 12 +#define NVIC_TIM1_BRK_UP_TRG_COM_IRQ 13 +#define NVIC_TIM1_CC_IRQ 14 +#define NVIC_TIM2_IRQ 15 +#define NVIC_TIM3_IRQ 16 +#define NVIC_TIM6_DAC_IRQ 17 +#define NVIC_TIM7_IRQ 18 +#define NVIC_TIM14_IRQ 19 +#define NVIC_TIM15_IRQ 20 +#define NVIC_TIM16_IRQ 21 +#define NVIC_TIM17_IRQ 22 +#define NVIC_I2C1_IRQ 23 +#define NVIC_I2C2_IRQ 24 +#define NVIC_SPI1_IRQ 25 +#define NVIC_SPI2_IRQ 26 +#define NVIC_USART1_IRQ 27 +#define NVIC_USART2_IRQ 28 +#define NVIC_USART3_4_IRQ 29 +#define NVIC_CEC_CAN_IRQ 30 +#define NVIC_USB_IRQ 31 + #define NVIC_IRQ_COUNT 32 + #define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - rtc_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_1_isr, \ - exti2_3_isr, \ - exti4_15_isr, \ - tsc_isr, \ - dma1_channel1_isr, \ - dma1_channel2_3_isr, \ - dma1_channel4_5_isr, \ - adc_comp_isr, \ - tim1_brk_up_trg_com_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - tim14_isr, \ - tim15_isr, \ - tim16_isr, \ - tim17_isr, \ - i2c1_isr, \ - i2c2_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_4_isr, \ - cec_can_isr, \ - usb_isr + [NVIC_WWDG_IRQ] = wwdg_isr, \ + [NVIC_PVD_IRQ] = pvd_isr, \ + [NVIC_RTC_IRQ] = rtc_isr, \ + [NVIC_FLASH_IRQ] = flash_isr, \ + [NVIC_RCC_IRQ] = rcc_isr, \ + [NVIC_EXTI0_1_IRQ] = exti0_1_isr, \ + [NVIC_EXTI2_3_IRQ] = exti2_3_isr, \ + [NVIC_EXTI4_15_IRQ] = exti4_15_isr, \ + [NVIC_TSC_IRQ] = tsc_isr, \ + [NVIC_DMA1_CHANNEL1_IRQ] = dma1_channel1_isr, \ + [NVIC_DMA1_CHANNEL2_3_IRQ] = dma1_channel2_3_isr, \ + [NVIC_DMA1_CHANNEL4_5_IRQ] = dma1_channel4_5_isr, \ + [NVIC_ADC_COMP_IRQ] = adc_comp_isr, \ + [NVIC_TIM1_BRK_UP_TRG_COM_IRQ] = tim1_brk_up_trg_com_isr, \ + [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, \ + [NVIC_TIM2_IRQ] = tim2_isr, \ + [NVIC_TIM3_IRQ] = tim3_isr, \ + [NVIC_TIM6_DAC_IRQ] = tim6_dac_isr, \ + [NVIC_TIM7_IRQ] = tim7_isr, \ + [NVIC_TIM14_IRQ] = tim14_isr, \ + [NVIC_TIM15_IRQ] = tim15_isr, \ + [NVIC_TIM16_IRQ] = tim16_isr, \ + [NVIC_TIM17_IRQ] = tim17_isr, \ + [NVIC_I2C1_IRQ] = i2c1_isr, \ + [NVIC_I2C2_IRQ] = i2c2_isr, \ + [NVIC_SPI1_IRQ] = spi1_isr, \ + [NVIC_SPI2_IRQ] = spi2_isr, \ + [NVIC_USART1_IRQ] = usart1_isr, \ + [NVIC_USART2_IRQ] = usart2_isr, \ + [NVIC_USART3_4_IRQ] = usart3_4_isr, \ + [NVIC_CEC_CAN_IRQ] = cec_can_isr, \ + [NVIC_USB_IRQ] = usb_isr + #elif defined STM32F1 #include "stm32f10x.h" + +#define NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMPER_IRQ 2 +#define NVIC_RTC_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_CHANNEL1_IRQ 11 +#define NVIC_DMA1_CHANNEL2_IRQ 12 +#define NVIC_DMA1_CHANNEL3_IRQ 13 +#define NVIC_DMA1_CHANNEL4_IRQ 14 +#define NVIC_DMA1_CHANNEL5_IRQ 15 +#define NVIC_DMA1_CHANNEL6_IRQ 16 +#define NVIC_DMA1_CHANNEL7_IRQ 17 +#define NVIC_ADC1_2_IRQ 18 +#define NVIC_USB_HP_CAN_TX_IRQ 19 +#define NVIC_USB_LP_CAN_RX0_IRQ 20 +#define NVIC_CAN_RX1_IRQ 21 +#define NVIC_CAN_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_IRQ 24 +#define NVIC_TIM1_UP_IRQ 25 +#define NVIC_TIM1_TRG_COM_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_WAKEUP_IRQ 42 +#define NVIC_TIM8_BRK_IRQ 43 +#define NVIC_TIM8_UP_IRQ 44 +#define NVIC_TIM8_TRG_COM_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_ADC3_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_UART4_IRQ 52 +#define NVIC_UART5_IRQ 53 +#define NVIC_TIM6_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_CHANNEL1_IRQ 56 +#define NVIC_DMA2_CHANNEL2_IRQ 57 +#define NVIC_DMA2_CHANNEL3_IRQ 58 +#define NVIC_DMA2_CHANNEL4_5_IRQ 59 +#define NVIC_DMA2_CHANNEL5_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 + #define NVIC_IRQ_COUNT 68 + #define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamper_isr, \ - rtc_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_channel1_isr, \ - dma1_channel2_isr, \ - dma1_channel3_isr, \ - dma1_channel4_isr, \ - dma1_channel5_isr, \ - dma1_channel6_isr, \ - dma1_channel7_isr, \ - adc1_2_isr, \ - usb_hp_can_tx_isr, \ - usb_lp_can_rx0_isr, \ - can_rx1_isr, \ - can_sce_isr, \ - exti9_5_isr, \ - tim1_brk_isr, \ - tim1_up_isr, \ - tim1_trg_com_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_wakeup_isr, \ - tim8_brk_isr, \ - tim8_up_isr, \ - tim8_trg_com_isr, \ - tim8_cc_isr, \ - adc3_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_isr, \ - tim7_isr, \ - dma2_channel1_isr, \ - dma2_channel2_isr, \ - dma2_channel3_isr, \ - dma2_channel4_5_isr, \ - dma2_channel5_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr + [NVIC_WWDG_IRQ] = wwdg_isr, \ + [NVIC_PVD_IRQ] = pvd_isr, \ + [NVIC_TAMPER_IRQ] = tamper_isr, \ + [NVIC_RTC_IRQ] = rtc_isr, \ + [NVIC_FLASH_IRQ] = flash_isr, \ + [NVIC_RCC_IRQ] = rcc_isr, \ + [NVIC_EXTI0_IRQ] = exti0_isr, \ + [NVIC_EXTI1_IRQ] = exti1_isr, \ + [NVIC_EXTI2_IRQ] = exti2_isr, \ + [NVIC_EXTI3_IRQ] = exti3_isr, \ + [NVIC_EXTI4_IRQ] = exti4_isr, \ + [NVIC_DMA1_CHANNEL1_IRQ] = dma1_channel1_isr, \ + [NVIC_DMA1_CHANNEL2_IRQ] = dma1_channel2_isr, \ + [NVIC_DMA1_CHANNEL3_IRQ] = dma1_channel3_isr, \ + [NVIC_DMA1_CHANNEL4_IRQ] = dma1_channel4_isr, \ + [NVIC_DMA1_CHANNEL5_IRQ] = dma1_channel5_isr, \ + [NVIC_DMA1_CHANNEL6_IRQ] = dma1_channel6_isr, \ + [NVIC_DMA1_CHANNEL7_IRQ] = dma1_channel7_isr, \ + [NVIC_ADC1_2_IRQ] = adc1_2_isr, \ + [NVIC_USB_HP_CAN_TX_IRQ] = usb_hp_can_tx_isr, \ + [NVIC_USB_LP_CAN_RX0_IRQ] = usb_lp_can_rx0_isr, \ + [NVIC_CAN_RX1_IRQ] = can_rx1_isr, \ + [NVIC_CAN_SCE_IRQ] = can_sce_isr, \ + [NVIC_EXTI9_5_IRQ] = exti9_5_isr, \ + [NVIC_TIM1_BRK_IRQ] = tim1_brk_isr, \ + [NVIC_TIM1_UP_IRQ] = tim1_up_isr, \ + [NVIC_TIM1_TRG_COM_IRQ] = tim1_trg_com_isr, \ + [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, \ + [NVIC_TIM2_IRQ] = tim2_isr, \ + [NVIC_TIM3_IRQ] = tim3_isr, \ + [NVIC_TIM4_IRQ] = tim4_isr, \ + [NVIC_I2C1_EV_IRQ] = i2c1_ev_isr, \ + [NVIC_I2C1_ER_IRQ] = i2c1_er_isr, \ + [NVIC_I2C2_EV_IRQ] = i2c2_ev_isr, \ + [NVIC_I2C2_ER_IRQ] = i2c2_er_isr, \ + [NVIC_SPI1_IRQ] = spi1_isr, \ + [NVIC_SPI2_IRQ] = spi2_isr, \ + [NVIC_USART1_IRQ] = usart1_isr, \ + [NVIC_USART2_IRQ] = usart2_isr, \ + [NVIC_USART3_IRQ] = usart3_isr, \ + [NVIC_EXTI15_10_IRQ] = exti15_10_isr, \ + [NVIC_RTC_ALARM_IRQ] = rtc_alarm_isr, \ + [NVIC_USB_WAKEUP_IRQ] = usb_wakeup_isr, \ + [NVIC_TIM8_BRK_IRQ] = tim8_brk_isr, \ + [NVIC_TIM8_UP_IRQ] = tim8_up_isr, \ + [NVIC_TIM8_TRG_COM_IRQ] = tim8_trg_com_isr, \ + [NVIC_TIM8_CC_IRQ] = tim8_cc_isr, \ + [NVIC_ADC3_IRQ] = adc3_isr, \ + [NVIC_FSMC_IRQ] = fsmc_isr, \ + [NVIC_SDIO_IRQ] = sdio_isr, \ + [NVIC_TIM5_IRQ] = tim5_isr, \ + [NVIC_SPI3_IRQ] = spi3_isr, \ + [NVIC_UART4_IRQ] = uart4_isr, \ + [NVIC_UART5_IRQ] = uart5_isr, \ + [NVIC_TIM6_IRQ] = tim6_isr, \ + [NVIC_TIM7_IRQ] = tim7_isr, \ + [NVIC_DMA2_CHANNEL1_IRQ] = dma2_channel1_isr, \ + [NVIC_DMA2_CHANNEL2_IRQ] = dma2_channel2_isr, \ + [NVIC_DMA2_CHANNEL3_IRQ] = dma2_channel3_isr, \ + [NVIC_DMA2_CHANNEL4_5_IRQ] = dma2_channel4_5_isr, \ + [NVIC_DMA2_CHANNEL5_IRQ] = dma2_channel5_isr, \ + [NVIC_ETH_IRQ] = eth_isr, \ + [NVIC_ETH_WKUP_IRQ] = eth_wkup_isr, \ + [NVIC_CAN2_TX_IRQ] = can2_tx_isr, \ + [NVIC_CAN2_RX0_IRQ] = can2_rx0_isr, \ + [NVIC_CAN2_RX1_IRQ] = can2_rx1_isr, \ + [NVIC_CAN2_SCE_IRQ] = can2_sce_isr, \ + [NVIC_OTG_FS_IRQ] = otg_fs_isr + #elif defined STM32F2 - #define NVIC_IRQ_COUNT 81 + +#define NVIC_NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMP_STAMP_IRQ 2 +#define NVIC_RTC_WKUP_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_STREAM0_IRQ 11 +#define NVIC_DMA1_STREAM1_IRQ 12 +#define NVIC_DMA1_STREAM2_IRQ 13 +#define NVIC_DMA1_STREAM3_IRQ 14 +#define NVIC_DMA1_STREAM4_IRQ 15 +#define NVIC_DMA1_STREAM5_IRQ 16 +#define NVIC_DMA1_STREAM6_IRQ 17 +#define NVIC_ADC_IRQ 18 +#define NVIC_CAN1_TX_IRQ 19 +#define NVIC_CAN1_RX0_IRQ 20 +#define NVIC_CAN1_RX1_IRQ 21 +#define NVIC_CAN1_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_TIM9_IRQ 24 +#define NVIC_TIM1_UP_TIM10_IRQ 25 +#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_FS_WKUP_IRQ 42 +#define NVIC_TIM8_BRK_TIM12_IRQ 43 +#define NVIC_TIM8_UP_TIM13_IRQ 44 +#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_DMA1_STREAM7_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_UART4_IRQ 52 +#define NVIC_UART5_IRQ 53 +#define NVIC_TIM6_DAC_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_STREAM0_IRQ 56 +#define NVIC_DMA2_STREAM1_IRQ 57 +#define NVIC_DMA2_STREAM2_IRQ 58 +#define NVIC_DMA2_STREAM3_IRQ 59 +#define NVIC_DMA2_STREAM4_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 +#define NVIC_DMA2_STREAM5_IRQ 68 +#define NVIC_DMA2_STREAM6_IRQ 69 +#define NVIC_DMA2_STREAM7_IRQ 70 +#define NVIC_USART6_IRQ 71 +#define NVIC_I2C3_EV_IRQ 72 +#define NVIC_I2C3_ER_IRQ 73 +#define NVIC_OTG_HS_EP1_OUT_IRQ 74 +#define NVIC_OTG_HS_EP1_IN_IRQ 75 +#define NVIC_OTG_HS_WKUP_IRQ 76 +#define NVIC_OTG_HS_IRQ 77 +#define NVIC_DCMI_IRQ 78 +#define NVIC_CRYP_IRQ 79 +#define NVIC_HASH_RNG_IRQ 80 + +#define NVIC_IRQ_COUNT 81 + #define IRQ_HANDLERS \ - nvic_wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_stream0_isr, \ - dma1_stream1_isr, \ - dma1_stream2_isr, \ - dma1_stream3_isr, \ - dma1_stream4_isr, \ - dma1_stream5_isr, \ - dma1_stream6_isr, \ - adc_isr, \ - can1_tx_isr, \ - can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim9_isr, \ - tim1_up_tim10_isr, \ - tim1_trg_com_tim11_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_fs_wkup_isr, \ - tim8_brk_tim12_isr, \ - tim8_up_tim13_isr, \ - tim8_trg_com_tim14_isr, \ - tim8_cc_isr, \ - dma1_stream7_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_stream0_isr, \ - dma2_stream1_isr, \ - dma2_stream2_isr, \ - dma2_stream3_isr, \ - dma2_stream4_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - dma2_stream5_isr, \ - dma2_stream6_isr, \ - dma2_stream7_isr, \ - usart6_isr, \ - i2c3_ev_isr, \ - i2c3_er_isr, \ - otg_hs_ep1_out_isr, \ - otg_hs_ep1_in_isr, \ - otg_hs_wkup_isr, \ - otg_hs_isr, \ - dcmi_isr, \ - cryp_isr, \ - hash_rng_isr + [NVIC_NVIC_WWDG_IRQ] = nvic_wwdg_isr, \ + [NVIC_PVD_IRQ] = pvd_isr, \ + [NVIC_TAMP_STAMP_IRQ] = tamp_stamp_isr, \ + [NVIC_RTC_WKUP_IRQ] = rtc_wkup_isr, \ + [NVIC_FLASH_IRQ] = flash_isr, \ + [NVIC_RCC_IRQ] = rcc_isr, \ + [NVIC_EXTI0_IRQ] = exti0_isr, \ + [NVIC_EXTI1_IRQ] = exti1_isr, \ + [NVIC_EXTI2_IRQ] = exti2_isr, \ + [NVIC_EXTI3_IRQ] = exti3_isr, \ + [NVIC_EXTI4_IRQ] = exti4_isr, \ + [NVIC_DMA1_STREAM0_IRQ] = dma1_stream0_isr, \ + [NVIC_DMA1_STREAM1_IRQ] = dma1_stream1_isr, \ + [NVIC_DMA1_STREAM2_IRQ] = dma1_stream2_isr, \ + [NVIC_DMA1_STREAM3_IRQ] = dma1_stream3_isr, \ + [NVIC_DMA1_STREAM4_IRQ] = dma1_stream4_isr, \ + [NVIC_DMA1_STREAM5_IRQ] = dma1_stream5_isr, \ + [NVIC_DMA1_STREAM6_IRQ] = dma1_stream6_isr, \ + [NVIC_ADC_IRQ] = adc_isr, \ + [NVIC_CAN1_TX_IRQ] = can1_tx_isr, \ + [NVIC_CAN1_RX0_IRQ] = can1_rx0_isr, \ + [NVIC_CAN1_RX1_IRQ] = can1_rx1_isr, \ + [NVIC_CAN1_SCE_IRQ] = can1_sce_isr, \ + [NVIC_EXTI9_5_IRQ] = exti9_5_isr, \ + [NVIC_TIM1_BRK_TIM9_IRQ] = tim1_brk_tim9_isr, \ + [NVIC_TIM1_UP_TIM10_IRQ] = tim1_up_tim10_isr, \ + [NVIC_TIM1_TRG_COM_TIM11_IRQ] = tim1_trg_com_tim11_isr, \ + [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, \ + [NVIC_TIM2_IRQ] = tim2_isr, \ + [NVIC_TIM3_IRQ] = tim3_isr, \ + [NVIC_TIM4_IRQ] = tim4_isr, \ + [NVIC_I2C1_EV_IRQ] = i2c1_ev_isr, \ + [NVIC_I2C1_ER_IRQ] = i2c1_er_isr, \ + [NVIC_I2C2_EV_IRQ] = i2c2_ev_isr, \ + [NVIC_I2C2_ER_IRQ] = i2c2_er_isr, \ + [NVIC_SPI1_IRQ] = spi1_isr, \ + [NVIC_SPI2_IRQ] = spi2_isr, \ + [NVIC_USART1_IRQ] = usart1_isr, \ + [NVIC_USART2_IRQ] = usart2_isr, \ + [NVIC_USART3_IRQ] = usart3_isr, \ + [NVIC_EXTI15_10_IRQ] = exti15_10_isr, \ + [NVIC_RTC_ALARM_IRQ] = rtc_alarm_isr, \ + [NVIC_USB_FS_WKUP_IRQ] = usb_fs_wkup_isr, \ + [NVIC_TIM8_BRK_TIM12_IRQ] = tim8_brk_tim12_isr, \ + [NVIC_TIM8_UP_TIM13_IRQ] = tim8_up_tim13_isr, \ + [NVIC_TIM8_TRG_COM_TIM14_IRQ] = tim8_trg_com_tim14_isr, \ + [NVIC_TIM8_CC_IRQ] = tim8_cc_isr, \ + [NVIC_DMA1_STREAM7_IRQ] = dma1_stream7_isr, \ + [NVIC_FSMC_IRQ] = fsmc_isr, \ + [NVIC_SDIO_IRQ] = sdio_isr, \ + [NVIC_TIM5_IRQ] = tim5_isr, \ + [NVIC_SPI3_IRQ] = spi3_isr, \ + [NVIC_UART4_IRQ] = uart4_isr, \ + [NVIC_UART5_IRQ] = uart5_isr, \ + [NVIC_TIM6_DAC_IRQ] = tim6_dac_isr, \ + [NVIC_TIM7_IRQ] = tim7_isr, \ + [NVIC_DMA2_STREAM0_IRQ] = dma2_stream0_isr, \ + [NVIC_DMA2_STREAM1_IRQ] = dma2_stream1_isr, \ + [NVIC_DMA2_STREAM2_IRQ] = dma2_stream2_isr, \ + [NVIC_DMA2_STREAM3_IRQ] = dma2_stream3_isr, \ + [NVIC_DMA2_STREAM4_IRQ] = dma2_stream4_isr, \ + [NVIC_ETH_IRQ] = eth_isr, \ + [NVIC_ETH_WKUP_IRQ] = eth_wkup_isr, \ + [NVIC_CAN2_TX_IRQ] = can2_tx_isr, \ + [NVIC_CAN2_RX0_IRQ] = can2_rx0_isr, \ + [NVIC_CAN2_RX1_IRQ] = can2_rx1_isr, \ + [NVIC_CAN2_SCE_IRQ] = can2_sce_isr, \ + [NVIC_OTG_FS_IRQ] = otg_fs_isr, \ + [NVIC_DMA2_STREAM5_IRQ] = dma2_stream5_isr, \ + [NVIC_DMA2_STREAM6_IRQ] = dma2_stream6_isr, \ + [NVIC_DMA2_STREAM7_IRQ] = dma2_stream7_isr, \ + [NVIC_USART6_IRQ] = usart6_isr, \ + [NVIC_I2C3_EV_IRQ] = i2c3_ev_isr, \ + [NVIC_I2C3_ER_IRQ] = i2c3_er_isr, \ + [NVIC_OTG_HS_EP1_OUT_IRQ] = otg_hs_ep1_out_isr, \ + [NVIC_OTG_HS_EP1_IN_IRQ] = otg_hs_ep1_in_isr, \ + [NVIC_OTG_HS_WKUP_IRQ] = otg_hs_wkup_isr, \ + [NVIC_OTG_HS_IRQ] = otg_hs_isr, \ + [NVIC_DCMI_IRQ] = dcmi_isr, \ + [NVIC_CRYP_IRQ] = cryp_isr, \ + [NVIC_HASH_RNG_IRQ] = hash_rng_isr #elif defined STM32F3 + +#define NVIC_NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMP_STAMP_IRQ 2 +#define NVIC_RTC_WKUP_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_TSC_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_CHANNEL1_IRQ 11 +#define NVIC_DMA1_CHANNEL2_IRQ 12 +#define NVIC_DMA1_CHANNEL3_IRQ 13 +#define NVIC_DMA1_CHANNEL4_IRQ 14 +#define NVIC_DMA1_CHANNEL5_IRQ 15 +#define NVIC_DMA1_CHANNEL6_IRQ 16 +#define NVIC_DMA1_CHANNEL7_IRQ 17 +#define NVIC_ADC1_2_IRQ 18 +#define NVIC_USB_HP_CAN1_TX_IRQ 19 +#define NVIC_USB_LP_CAN1_RX0_IRQ 20 +#define NVIC_CAN1_RX1_IRQ 21 +#define NVIC_CAN1_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_TIM15_IRQ 24 +#define NVIC_TIM1_UP_TIM16_IRQ 25 +#define NVIC_TIM1_TRG_COM_TIM17_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_EXTI23_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_EXTI24_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_EXTI25_IRQ 37 +#define NVIC_USART2_EXTI26_IRQ 38 +#define NVIC_USART3_EXTI28_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_WKUP_A_IRQ 42 +#define NVIC_TIM8_BRK_IRQ 43 +#define NVIC_TIM8_UP_IRQ 44 +#define NVIC_TIM8_TRG_COM_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_ADC3_IRQ 47 +#define NVIC_RESERVED_1_IRQ 48 +#define NVIC_RESERVED_2_IRQ 49 +#define NVIC_RESERVED_3_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_UART4_EXTI34_IRQ 52 +#define NVIC_UART5_EXTI35_IRQ 53 +#define NVIC_TIM6_DAC_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_CHANNEL1_IRQ 56 +#define NVIC_DMA2_CHANNEL2_IRQ 57 +#define NVIC_DMA2_CHANNEL3_IRQ 58 +#define NVIC_DMA2_CHANNEL4_IRQ 59 +#define NVIC_DMA2_CHANNEL5_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_RESERVED_4_IRQ 62 +#define NVIC_RESERVED_5_IRQ 63 +#define NVIC_COMP123_IRQ 64 +#define NVIC_COMP456_IRQ 65 +#define NVIC_COMP7_IRQ 66 +#define NVIC_RESERVED_6_IRQ 67 +#define NVIC_RESERVED_7_IRQ 68 +#define NVIC_RESERVED_8_IRQ 69 +#define NVIC_RESERVED_9_IRQ 70 +#define NVIC_RESERVED_10_IRQ 71 +#define NVIC_RESERVED_11_IRQ 72 +#define NVIC_RESERVED_12_IRQ 73 +#define NVIC_USB_HP_IRQ 74 +#define NVIC_USB_LP_IRQ 75 +#define NVIC_USB_WKUP_IRQ 76 +#define NVIC_RESERVED_13_IRQ 77 +#define NVIC_RESERVED_14_IRQ 78 +#define NVIC_RESERVED_15_IRQ 79 +#define NVIC_RESERVED_16_IRQ 80 + #define NVIC_IRQ_COUNT 81 #define IRQ_HANDLERS \ - nvic_wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_tsc_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_channel1_isr, \ - dma1_channel2_isr, \ - dma1_channel3_isr, \ - dma1_channel4_isr, \ - dma1_channel5_isr, \ - dma1_channel6_isr, \ - dma1_channel7_isr, \ - adc1_2_isr, \ - usb_hp_can1_tx_isr, \ - usb_lp_can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim15_isr, \ - tim1_up_tim16_isr, \ - tim1_trg_com_tim17_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_exti23_isr, \ - i2c1_er_isr, \ - i2c2_ev_exti24_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_exti25_isr, \ - usart2_exti26_isr, \ - usart3_exti28_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_wkup_a_isr, \ - tim8_brk_isr, \ - tim8_up_isr, \ - tim8_trg_com_isr, \ - tim8_cc_isr, \ - adc3_isr, \ - reserved_1_isr, \ - reserved_2_isr, \ - reserved_3_isr, \ - spi3_isr, \ - uart4_exti34_isr, \ - uart5_exti35_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_channel1_isr, \ - dma2_channel2_isr, \ - dma2_channel3_isr, \ - dma2_channel4_isr, \ - dma2_channel5_isr, \ - eth_isr, \ - reserved_4_isr, \ - reserved_5_isr, \ - comp123_isr, \ - comp456_isr, \ - comp7_isr, \ - reserved_6_isr, \ - reserved_7_isr, \ - reserved_8_isr, \ - reserved_9_isr, \ - reserved_10_isr, \ - reserved_11_isr, \ - reserved_12_isr, \ - usb_hp_isr, \ - usb_lp_isr, \ - usb_wkup_isr, \ - reserved_13_isr, \ - reserved_14_isr, \ - reserved_15_isr, \ - reserved_16_isr + [NVIC_NVIC_WWDG_IRQ] = nvic_wwdg_isr, \ + [NVIC_PVD_IRQ] = pvd_isr, \ + [NVIC_TAMP_STAMP_IRQ] = tamp_stamp_isr, \ + [NVIC_RTC_WKUP_IRQ] = rtc_wkup_isr, \ + [NVIC_FLASH_IRQ] = flash_isr, \ + [NVIC_RCC_IRQ] = rcc_isr, \ + [NVIC_EXTI0_IRQ] = exti0_isr, \ + [NVIC_EXTI1_IRQ] = exti1_isr, \ + [NVIC_EXTI2_TSC_IRQ] = exti2_tsc_isr, \ + [NVIC_EXTI3_IRQ] = exti3_isr, \ + [NVIC_EXTI4_IRQ] = exti4_isr, \ + [NVIC_DMA1_CHANNEL1_IRQ] = dma1_channel1_isr, \ + [NVIC_DMA1_CHANNEL2_IRQ] = dma1_channel2_isr, \ + [NVIC_DMA1_CHANNEL3_IRQ] = dma1_channel3_isr, \ + [NVIC_DMA1_CHANNEL4_IRQ] = dma1_channel4_isr, \ + [NVIC_DMA1_CHANNEL5_IRQ] = dma1_channel5_isr, \ + [NVIC_DMA1_CHANNEL6_IRQ] = dma1_channel6_isr, \ + [NVIC_DMA1_CHANNEL7_IRQ] = dma1_channel7_isr, \ + [NVIC_ADC1_2_IRQ] = adc1_2_isr, \ + [NVIC_USB_HP_CAN1_TX_IRQ] = usb_hp_can1_tx_isr, \ + [NVIC_USB_LP_CAN1_RX0_IRQ] = usb_lp_can1_rx0_isr, \ + [NVIC_CAN1_RX1_IRQ] = can1_rx1_isr, \ + [NVIC_CAN1_SCE_IRQ] = can1_sce_isr, \ + [NVIC_EXTI9_5_IRQ] = exti9_5_isr, \ + [NVIC_TIM1_BRK_TIM15_IRQ] = tim1_brk_tim15_isr, \ + [NVIC_TIM1_UP_TIM16_IRQ] = tim1_up_tim16_isr, \ + [NVIC_TIM1_TRG_COM_TIM17_IRQ] = tim1_trg_com_tim17_isr, \ + [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, \ + [NVIC_TIM2_IRQ] = tim2_isr, \ + [NVIC_TIM3_IRQ] = tim3_isr, \ + [NVIC_TIM4_IRQ] = tim4_isr, \ + [NVIC_I2C1_EV_EXTI23_IRQ] = i2c1_ev_exti23_isr, \ + [NVIC_I2C1_ER_IRQ] = i2c1_er_isr, \ + [NVIC_I2C2_EV_EXTI24_IRQ] = i2c2_ev_exti24_isr, \ + [NVIC_I2C2_ER_IRQ] = i2c2_er_isr, \ + [NVIC_SPI1_IRQ] = spi1_isr, \ + [NVIC_SPI2_IRQ] = spi2_isr, \ + [NVIC_USART1_EXTI25_IRQ] = usart1_exti25_isr, \ + [NVIC_USART2_EXTI26_IRQ] = usart2_exti26_isr, \ + [NVIC_USART3_EXTI28_IRQ] = usart3_exti28_isr, \ + [NVIC_EXTI15_10_IRQ] = exti15_10_isr, \ + [NVIC_RTC_ALARM_IRQ] = rtc_alarm_isr, \ + [NVIC_USB_WKUP_A_IRQ] = usb_wkup_a_isr, \ + [NVIC_TIM8_BRK_IRQ] = tim8_brk_isr, \ + [NVIC_TIM8_UP_IRQ] = tim8_up_isr, \ + [NVIC_TIM8_TRG_COM_IRQ] = tim8_trg_com_isr, \ + [NVIC_TIM8_CC_IRQ] = tim8_cc_isr, \ + [NVIC_ADC3_IRQ] = adc3_isr, \ + [NVIC_RESERVED_1_IRQ] = reserved_1_isr, \ + [NVIC_RESERVED_2_IRQ] = reserved_2_isr, \ + [NVIC_RESERVED_3_IRQ] = reserved_3_isr, \ + [NVIC_SPI3_IRQ] = spi3_isr, \ + [NVIC_UART4_EXTI34_IRQ] = uart4_exti34_isr, \ + [NVIC_UART5_EXTI35_IRQ] = uart5_exti35_isr, \ + [NVIC_TIM6_DAC_IRQ] = tim6_dac_isr, \ + [NVIC_TIM7_IRQ] = tim7_isr, \ + [NVIC_DMA2_CHANNEL1_IRQ] = dma2_channel1_isr, \ + [NVIC_DMA2_CHANNEL2_IRQ] = dma2_channel2_isr, \ + [NVIC_DMA2_CHANNEL3_IRQ] = dma2_channel3_isr, \ + [NVIC_DMA2_CHANNEL4_IRQ] = dma2_channel4_isr, \ + [NVIC_DMA2_CHANNEL5_IRQ] = dma2_channel5_isr, \ + [NVIC_ETH_IRQ] = eth_isr, \ + [NVIC_RESERVED_4_IRQ] = reserved_4_isr, \ + [NVIC_RESERVED_5_IRQ] = reserved_5_isr, \ + [NVIC_COMP123_IRQ] = comp123_isr, \ + [NVIC_COMP456_IRQ] = comp456_isr, \ + [NVIC_COMP7_IRQ] = comp7_isr, \ + [NVIC_RESERVED_6_IRQ] = reserved_6_isr, \ + [NVIC_RESERVED_7_IRQ] = reserved_7_isr, \ + [NVIC_RESERVED_8_IRQ] = reserved_8_isr, \ + [NVIC_RESERVED_9_IRQ] = reserved_9_isr, \ + [NVIC_RESERVED_10_IRQ] = reserved_10_isr, \ + [NVIC_RESERVED_11_IRQ] = reserved_11_isr, \ + [NVIC_RESERVED_12_IRQ] = reserved_12_isr, \ + [NVIC_USB_HP_IRQ] = usb_hp_isr, \ + [NVIC_USB_LP_IRQ] = usb_lp_isr, \ + [NVIC_USB_WKUP_IRQ] = usb_wkup_isr, \ + [NVIC_RESERVED_13_IRQ] = reserved_13_isr, \ + [NVIC_RESERVED_14_IRQ] = reserved_14_isr, \ + [NVIC_RESERVED_15_IRQ] = reserved_15_isr, \ + [NVIC_RESERVED_16_IRQ] = reserved_16_isr #elif defined STM32F4 + +#define NVIC_NVIC_WWDG_IRQ 0 +#define NVIC_PVD_IRQ 1 +#define NVIC_TAMP_STAMP_IRQ 2 +#define NVIC_RTC_WKUP_IRQ 3 +#define NVIC_FLASH_IRQ 4 +#define NVIC_RCC_IRQ 5 +#define NVIC_EXTI0_IRQ 6 +#define NVIC_EXTI1_IRQ 7 +#define NVIC_EXTI2_IRQ 8 +#define NVIC_EXTI3_IRQ 9 +#define NVIC_EXTI4_IRQ 10 +#define NVIC_DMA1_STREAM0_IRQ 11 +#define NVIC_DMA1_STREAM1_IRQ 12 +#define NVIC_DMA1_STREAM2_IRQ 13 +#define NVIC_DMA1_STREAM3_IRQ 14 +#define NVIC_DMA1_STREAM4_IRQ 15 +#define NVIC_DMA1_STREAM5_IRQ 16 +#define NVIC_DMA1_STREAM6_IRQ 17 +#define NVIC_ADC_IRQ 18 +#define NVIC_CAN1_TX_IRQ 19 +#define NVIC_CAN1_RX0_IRQ 20 +#define NVIC_CAN1_RX1_IRQ 21 +#define NVIC_CAN1_SCE_IRQ 22 +#define NVIC_EXTI9_5_IRQ 23 +#define NVIC_TIM1_BRK_TIM9_IRQ 24 +#define NVIC_TIM1_UP_TIM10_IRQ 25 +#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 +#define NVIC_TIM1_CC_IRQ 27 +#define NVIC_TIM2_IRQ 28 +#define NVIC_TIM3_IRQ 29 +#define NVIC_TIM4_IRQ 30 +#define NVIC_I2C1_EV_IRQ 31 +#define NVIC_I2C1_ER_IRQ 32 +#define NVIC_I2C2_EV_IRQ 33 +#define NVIC_I2C2_ER_IRQ 34 +#define NVIC_SPI1_IRQ 35 +#define NVIC_SPI2_IRQ 36 +#define NVIC_USART1_IRQ 37 +#define NVIC_USART2_IRQ 38 +#define NVIC_USART3_IRQ 39 +#define NVIC_EXTI15_10_IRQ 40 +#define NVIC_RTC_ALARM_IRQ 41 +#define NVIC_USB_FS_WKUP_IRQ 42 +#define NVIC_TIM8_BRK_TIM12_IRQ 43 +#define NVIC_TIM8_UP_TIM13_IRQ 44 +#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 +#define NVIC_TIM8_CC_IRQ 46 +#define NVIC_DMA1_STREAM7_IRQ 47 +#define NVIC_FSMC_IRQ 48 +#define NVIC_SDIO_IRQ 49 +#define NVIC_TIM5_IRQ 50 +#define NVIC_SPI3_IRQ 51 +#define NVIC_UART4_IRQ 52 +#define NVIC_UART5_IRQ 53 +#define NVIC_TIM6_DAC_IRQ 54 +#define NVIC_TIM7_IRQ 55 +#define NVIC_DMA2_STREAM0_IRQ 56 +#define NVIC_DMA2_STREAM1_IRQ 57 +#define NVIC_DMA2_STREAM2_IRQ 58 +#define NVIC_DMA2_STREAM3_IRQ 59 +#define NVIC_DMA2_STREAM4_IRQ 60 +#define NVIC_ETH_IRQ 61 +#define NVIC_ETH_WKUP_IRQ 62 +#define NVIC_CAN2_TX_IRQ 63 +#define NVIC_CAN2_RX0_IRQ 64 +#define NVIC_CAN2_RX1_IRQ 65 +#define NVIC_CAN2_SCE_IRQ 66 +#define NVIC_OTG_FS_IRQ 67 +#define NVIC_DMA2_STREAM5_IRQ 68 +#define NVIC_DMA2_STREAM6_IRQ 69 +#define NVIC_DMA2_STREAM7_IRQ 70 +#define NVIC_USART6_IRQ 71 +#define NVIC_I2C3_EV_IRQ 72 +#define NVIC_I2C3_ER_IRQ 73 +#define NVIC_OTG_HS_EP1_OUT_IRQ 74 +#define NVIC_OTG_HS_EP1_IN_IRQ 75 +#define NVIC_OTG_HS_WKUP_IRQ 76 +#define NVIC_OTG_HS_IRQ 77 +#define NVIC_DCMI_IRQ 78 +#define NVIC_CRYP_IRQ 79 +#define NVIC_HASH_RNG_IRQ 80 +#define NVIC_FPU_IRQ 81 +#define NVIC_UART7_IRQ 82 +#define NVIC_UART8_IRQ 83 +#define NVIC_SPI4_IRQ 84 +#define NVIC_SPI5_IRQ 85 +#define NVIC_SPI6_IRQ 86 +#define NVIC_SAI1_IRQ 87 +#define NVIC_LCD_TFT_IRQ 88 +#define NVIC_LCD_TFT_ERR_IRQ 89 +#define NVIC_DMA2D_IRQ 90 + #define NVIC_IRQ_COUNT 91 #define IRQ_HANDLERS \ - nvic_wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_stream0_isr, \ - dma1_stream1_isr, \ - dma1_stream2_isr, \ - dma1_stream3_isr, \ - dma1_stream4_isr, \ - dma1_stream5_isr, \ - dma1_stream6_isr, \ - adc_isr, \ - can1_tx_isr, \ - can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim9_isr, \ - tim1_up_tim10_isr, \ - tim1_trg_com_tim11_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_fs_wkup_isr, \ - tim8_brk_tim12_isr, \ - tim8_up_tim13_isr, \ - tim8_trg_com_tim14_isr, \ - tim8_cc_isr, \ - dma1_stream7_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_stream0_isr, \ - dma2_stream1_isr, \ - dma2_stream2_isr, \ - dma2_stream3_isr, \ - dma2_stream4_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - dma2_stream5_isr, \ - dma2_stream6_isr, \ - dma2_stream7_isr, \ - usart6_isr, \ - i2c3_ev_isr, \ - i2c3_er_isr, \ - otg_hs_ep1_out_isr, \ - otg_hs_ep1_in_isr, \ - otg_hs_wkup_isr, \ - otg_hs_isr, \ - dcmi_isr, \ - cryp_isr, \ - hash_rng_isr, \ - fpu_isr, \ - uart7_isr, \ - uart8_isr, \ - spi4_isr, \ - spi5_isr, \ - spi6_isr, \ - sai1_isr, \ - lcd_tft_isr, \ - lcd_tft_err_isr, \ - dma2d_isr + [NVIC_NVIC_WWDG_IRQ] = nvic_wwdg_isr, \ + [NVIC_PVD_IRQ] = pvd_isr, \ + [NVIC_TAMP_STAMP_IRQ] = tamp_stamp_isr, \ + [NVIC_RTC_WKUP_IRQ] = rtc_wkup_isr, \ + [NVIC_FLASH_IRQ] = flash_isr, \ + [NVIC_RCC_IRQ] = rcc_isr, \ + [NVIC_EXTI0_IRQ] = exti0_isr, \ + [NVIC_EXTI1_IRQ] = exti1_isr, \ + [NVIC_EXTI2_IRQ] = exti2_isr, \ + [NVIC_EXTI3_IRQ] = exti3_isr, \ + [NVIC_EXTI4_IRQ] = exti4_isr, \ + [NVIC_DMA1_STREAM0_IRQ] = dma1_stream0_isr, \ + [NVIC_DMA1_STREAM1_IRQ] = dma1_stream1_isr, \ + [NVIC_DMA1_STREAM2_IRQ] = dma1_stream2_isr, \ + [NVIC_DMA1_STREAM3_IRQ] = dma1_stream3_isr, \ + [NVIC_DMA1_STREAM4_IRQ] = dma1_stream4_isr, \ + [NVIC_DMA1_STREAM5_IRQ] = dma1_stream5_isr, \ + [NVIC_DMA1_STREAM6_IRQ] = dma1_stream6_isr, \ + [NVIC_ADC_IRQ] = adc_isr, \ + [NVIC_CAN1_TX_IRQ] = can1_tx_isr, \ + [NVIC_CAN1_RX0_IRQ] = can1_rx0_isr, \ + [NVIC_CAN1_RX1_IRQ] = can1_rx1_isr, \ + [NVIC_CAN1_SCE_IRQ] = can1_sce_isr, \ + [NVIC_EXTI9_5_IRQ] = exti9_5_isr, \ + [NVIC_TIM1_BRK_TIM9_IRQ] = tim1_brk_tim9_isr, \ + [NVIC_TIM1_UP_TIM10_IRQ] = tim1_up_tim10_isr, \ + [NVIC_TIM1_TRG_COM_TIM11_IRQ] = tim1_trg_com_tim11_isr, \ + [NVIC_TIM1_CC_IRQ] = tim1_cc_isr, \ + [NVIC_TIM2_IRQ] = tim2_isr, \ + [NVIC_TIM3_IRQ] = tim3_isr, \ + [NVIC_TIM4_IRQ] = tim4_isr, \ + [NVIC_I2C1_EV_IRQ] = i2c1_ev_isr, \ + [NVIC_I2C1_ER_IRQ] = i2c1_er_isr, \ + [NVIC_I2C2_EV_IRQ] = i2c2_ev_isr, \ + [NVIC_I2C2_ER_IRQ] = i2c2_er_isr, \ + [NVIC_SPI1_IRQ] = spi1_isr, \ + [NVIC_SPI2_IRQ] = spi2_isr, \ + [NVIC_USART1_IRQ] = usart1_isr, \ + [NVIC_USART2_IRQ] = usart2_isr, \ + [NVIC_USART3_IRQ] = usart3_isr, \ + [NVIC_EXTI15_10_IRQ] = exti15_10_isr, \ + [NVIC_RTC_ALARM_IRQ] = rtc_alarm_isr, \ + [NVIC_USB_FS_WKUP_IRQ] = usb_fs_wkup_isr, \ + [NVIC_TIM8_BRK_TIM12_IRQ] = tim8_brk_tim12_isr, \ + [NVIC_TIM8_UP_TIM13_IRQ] = tim8_up_tim13_isr, \ + [NVIC_TIM8_TRG_COM_TIM14_IRQ] = tim8_trg_com_tim14_isr, \ + [NVIC_TIM8_CC_IRQ] = tim8_cc_isr, \ + [NVIC_DMA1_STREAM7_IRQ] = dma1_stream7_isr, \ + [NVIC_FSMC_IRQ] = fsmc_isr, \ + [NVIC_SDIO_IRQ] = sdio_isr, \ + [NVIC_TIM5_IRQ] = tim5_isr, \ + [NVIC_SPI3_IRQ] = spi3_isr, \ + [NVIC_UART4_IRQ] = uart4_isr, \ + [NVIC_UART5_IRQ] = uart5_isr, \ + [NVIC_TIM6_DAC_IRQ] = tim6_dac_isr, \ + [NVIC_TIM7_IRQ] = tim7_isr, \ + [NVIC_DMA2_STREAM0_IRQ] = dma2_stream0_isr, \ + [NVIC_DMA2_STREAM1_IRQ] = dma2_stream1_isr, \ + [NVIC_DMA2_STREAM2_IRQ] = dma2_stream2_isr, \ + [NVIC_DMA2_STREAM3_IRQ] = dma2_stream3_isr, \ + [NVIC_DMA2_STREAM4_IRQ] = dma2_stream4_isr, \ + [NVIC_ETH_IRQ] = eth_isr, \ + [NVIC_ETH_WKUP_IRQ] = eth_wkup_isr, \ + [NVIC_CAN2_TX_IRQ] = can2_tx_isr, \ + [NVIC_CAN2_RX0_IRQ] = can2_rx0_isr, \ + [NVIC_CAN2_RX1_IRQ] = can2_rx1_isr, \ + [NVIC_CAN2_SCE_IRQ] = can2_sce_isr, \ + [NVIC_OTG_FS_IRQ] = otg_fs_isr, \ + [NVIC_DMA2_STREAM5_IRQ] = dma2_stream5_isr, \ + [NVIC_DMA2_STREAM6_IRQ] = dma2_stream6_isr, \ + [NVIC_DMA2_STREAM7_IRQ] = dma2_stream7_isr, \ + [NVIC_USART6_IRQ] = usart6_isr, \ + [NVIC_I2C3_EV_IRQ] = i2c3_ev_isr, \ + [NVIC_I2C3_ER_IRQ] = i2c3_er_isr, \ + [NVIC_OTG_HS_EP1_OUT_IRQ] = otg_hs_ep1_out_isr, \ + [NVIC_OTG_HS_EP1_IN_IRQ] = otg_hs_ep1_in_isr, \ + [NVIC_OTG_HS_WKUP_IRQ] = otg_hs_wkup_isr, \ + [NVIC_OTG_HS_IRQ] = otg_hs_isr, \ + [NVIC_DCMI_IRQ] = dcmi_isr, \ + [NVIC_CRYP_IRQ] = cryp_isr, \ + [NVIC_HASH_RNG_IRQ] = hash_rng_isr, \ + [NVIC_FPU_IRQ] = fpu_isr, \ + [NVIC_UART7_IRQ] = uart7_isr, \ + [NVIC_UART8_IRQ] = uart8_isr, \ + [NVIC_SPI4_IRQ] = spi4_isr, \ + [NVIC_SPI5_IRQ] = spi5_isr, \ + [NVIC_SPI6_IRQ] = spi6_isr, \ + [NVIC_SAI1_IRQ] = sai1_isr, \ + [NVIC_LCD_TFT_IRQ] = lcd_tft_isr, \ + [NVIC_LCD_TFT_ERR_IRQ] = lcd_tft_err_isr, \ + [NVIC_DMA2D_IRQ] = dma2d_isr #else #error "Not supported STM32 family" #endif - #if defined STM32F0 + + +typedef struct { + unsigned int *initial_sp_value; /**< Initial stack pointer value. */ + vector_table_entry_t reset; + vector_table_entry_t nmi; + vector_table_entry_t hard_fault; + vector_table_entry_t memory_manage_fault; /* not in CM0 */ + vector_table_entry_t bus_fault; /* not in CM0 */ + vector_table_entry_t usage_fault; /* not in CM0 */ + vector_table_entry_t reserved_x001c[4]; + vector_table_entry_t sv_call; + vector_table_entry_t debug_monitor; /* not in CM0 */ + vector_table_entry_t reserved_x0034; + vector_table_entry_t pend_sv; + vector_table_entry_t systick; + vector_table_entry_t irq[NVIC_IRQ_COUNT]; +} vector_table_t; + +extern unsigned _stack; + +vector_table_t vector_table __attribute__ ((section(".vector_table"))) = { + .initial_sp_value = &_stack, + .reset = reset_handler, + .nmi = nmi_handler, + .hard_fault = hard_fault_handler, + +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + .memory_manage_fault = mem_manage_handler, + .bus_fault = bus_fault_handler, + .usage_fault = usage_fault_handler, + .debug_monitor = debug_monitor_handler, +#endif + + .sv_call = sv_call_handler, + .pend_sv = pend_sv_handler, + .systick = sys_tick_handler, + .irq = { + IRQ_HANDLERS + } +}; + +void WEAK __attribute__ ((naked)) __attribute__ ((noreturn)) reset_handler(void){ + extern char _sdata; // .data section start + extern char _edata; // .data section end + extern char _sbss; // .bss section start + extern char _ebss; // .bss section end + extern char _ldata; // .data load address + + char *dst = &_sdata; + char *src = &_ldata; + + // enable 8-byte stack alignment to comply with AAPCS + SCB->CCR |= 0x00000200; + + // copy initialized variables data + while ( dst < &_edata ) { *dst++ = *src++; } + + // clear uninitialized variables + for ( dst = &_sbss; dst < &_ebss; dst++ ) { *dst = 0; } + + // call main + main(); + + // halt + for(;;) {} +} + +void blocking_handler(void) +{ + while (1); +} + +void null_handler(void) +{ + /* Do nothing. */ +} + + #pragma weak nmi_handler = null_handler #pragma weak hard_fault_handler = blocking_handler #pragma weak sv_call_handler = null_handler #pragma weak pend_sv_handler = null_handler #pragma weak sys_tick_handler = null_handler +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak debug_monitor_handler = null_handler +#endif + +#if defined STM32F0 #pragma weak wwdg_isr = blocking_handler #pragma weak pvd_isr = blocking_handler #pragma weak rtc_isr = blocking_handler @@ -770,94 +1232,6 @@ #endif - -void main(void); -void blocking_handler(void); -void null_handler(void); - -typedef struct { - unsigned int *initial_sp_value; /**< Initial stack pointer value. */ - vector_table_entry_t reset; - vector_table_entry_t nmi; - vector_table_entry_t hard_fault; - vector_table_entry_t memory_manage_fault; /* not in CM0 */ - vector_table_entry_t bus_fault; /* not in CM0 */ - vector_table_entry_t usage_fault; /* not in CM0 */ - vector_table_entry_t reserved_x001c[4]; - vector_table_entry_t sv_call; - vector_table_entry_t debug_monitor; /* not in CM0 */ - vector_table_entry_t reserved_x0034; - vector_table_entry_t pend_sv; - vector_table_entry_t systick; - vector_table_entry_t irq[NVIC_IRQ_COUNT]; -} vector_table_t; - -__attribute__ ((section(".vectors"))) -vector_table_t vector_table = { - .initial_sp_value = &_stack, - .reset = reset_handler, - .nmi = nmi_handler, - .hard_fault = hard_fault_handler, - -/* Those are defined only on CM3 or CM4 */ -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) - .memory_manage_fault = mem_manage_handler, - .bus_fault = bus_fault_handler, - .usage_fault = usage_fault_handler, - .debug_monitor = debug_monitor_handler, -#endif - - .sv_call = sv_call_handler, - .pend_sv = pend_sv_handler, - .systick = sys_tick_handler, - .irq = { - IRQ_HANDLERS - } -}; - -void WEAK __attribute__ ((naked)) reset_handler(void) -{ - volatile unsigned *src, *dest; - funcp_t *fp; - - for (src = &_data_loadaddr, dest = &_data; - dest < &_edata; - src++, dest++) { - *dest = *src; - } - - while (dest < &_ebss) { - *dest++ = 0; - } - - /* Constructors. */ - for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) { - (*fp)(); - } - for (fp = &__init_array_start; fp < &__init_array_end; fp++) { - (*fp)(); - } - - /* Call the application's entry point. */ - main(); - - /* Destructors. */ - for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) { - (*fp)(); - } - -} - -void blocking_handler(void) -{ - while (1); -} - -void null_handler(void) -{ - /* Do nothing. */ -} - /* FOR f3/f4: static void pre_main(void) diff --git a/F1-nolib/led_blink/Makefile b/F1-nolib/led_blink/Makefile index d0ac0dc..7620c9b 100644 --- a/F1-nolib/led_blink/Makefile +++ b/F1-nolib/led_blink/Makefile @@ -11,11 +11,13 @@ DEFS = -DEBUG # change this linking script depending on particular MCU model, # for example, if you have STM32F103VBT6, you should write: LDSCRIPT ?= ld/stm32f103xB.ld +#LDSCRIPT = STM32F103C8.ld INDEPENDENT_HEADERS= FP_FLAGS ?= -msoft-float -ASM_FLAGS ?= -mthumb -mcpu=cortex-m3 -mfix-cortex-m3-ldrd +ASM_FLAGS ?= -mthumb -mcpu=cortex-m3 +#-mfix-cortex-m3-ldrd ARCH_FLAGS = $(ASM_FLAGS) $(FP_FLAGS) ############################################################################### @@ -25,9 +27,10 @@ PREFIX ?= arm-none-eabi RM := rm -f RMDIR := rmdir CC := $(PREFIX)-gcc -LD := $(PREFIX)-gcc +LD := $(PREFIX)-ld AR := $(PREFIX)-ar AS := $(PREFIX)-as +SIZE := $(PREFIX)-size OBJCOPY := $(PREFIX)-objcopy OBJDUMP := $(PREFIX)-objdump GDB := $(PREFIX)-gdb @@ -51,25 +54,28 @@ LIB_DIR := $(INC_DIR)/ld ############################################################################### # C flags -CFLAGS += -O2 -g -MD -D__thumb2__=1 -CFLAGS += -Wall -Werror -Wextra -Wshadow -Wimplicit-function-declaration -CFLAGS += -Wredundant-decls +CFLAGS += -O0 -g +# -MD -D__thumb2__=1 +#CFLAGS += -Wall -Werror -Wextra -Wshadow -Wimplicit-function-declaration +#CFLAGS += -Wredundant-decls # -Wmissing-prototypes -Wstrict-prototypes -CFLAGS += -fno-common -ffunction-sections -fdata-sections +CFLAGS += -fno-common +#-ffunction-sections -fdata-sections ############################################################################### # Linker flags -LDFLAGS += --static -nostartfiles +LDFLAGS += -nostartfiles +# --static #--specs=nano.specs LDFLAGS += -L$(LIB_DIR) LDFLAGS += -T$(LDSCRIPT) -LDFLAGS += -Wl,-Map=$(OBJDIR)/$(BINARY).map -LDFLAGS += -Wl,--gc-sections +#LDFLAGS += -Wl,-Map=$(OBJDIR)/$(BINARY).map +#LDFLAGS += -Wl,--gc-sections ############################################################################### # Used libraries -LDLIBS += -Wl,--start-group -lc -lgcc -Wl,--end-group -LDLIBS += $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) +#LDLIBS += -Wl,--start-group -lc -lgcc -Wl,--end-group +#LDLIBS += $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) DEFS += -DSTM32$(FAMILY) -DSTM32$(MCU) -DSTM32F10X_$(DENSITY) @@ -82,7 +88,7 @@ LIST := $(OBJDIR)/$(BINARY).list BIN := $(BINARY).bin HEX := $(BINARY).hex -all: bin list +all: bin list size elf: $(ELF) bin: $(BIN) @@ -120,7 +126,10 @@ $(LIST): $(ELF) $(ELF): $(OBJDIR) $(OBJS) @echo " LD $(ELF)" - $(LD) $(LDFLAGS) $(ARCH_FLAGS) $(OBJS) $(LDLIBS) -o $(ELF) + $(LD) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $(ELF) + +size: $(ELF) + $(SIZE) $(ELF) clean: @echo " CLEAN" diff --git a/F1-nolib/led_blink/README b/F1-nolib/led_blink/README index d2454f6..35bb182 100644 --- a/F1-nolib/led_blink/README +++ b/F1-nolib/led_blink/README @@ -1,3 +1,5 @@ Toggle LEDs (PB8/PB9) on STM32F103 development board depending on buttons PC0,PC1: -- no jumper == 'SOS' in Morze -- with jumper - blink with period of 4 seconds +- no buttons pressed == 'SOS' in Morze @ LED D1 +- Button S2 pressed - D1 blinks with period of 5s +- Button S1 pressed - D2 blinks with period of 1s + diff --git a/F1-nolib/led_blink/blink.bin b/F1-nolib/led_blink/blink.bin index 2f33cfd25f8bc1683c3215e24797853017e5ed98..c3a87dd83fe86afaf2cabe3c9f1d99d65b0ffb3e 100755 GIT binary patch literal 1516 zcmd^9&u<$=6n^Wqu@jrxbOR1fB#c)=6pJd5N>HUju5E4cj-aJ35;PKwOMne`)4*rjK--#FBOuJ8|5f>~&vuRf+t|K(`U+iEjlH~e{L-KP0ZIlJ zhpfe!P_A`CZG=_t&`xDxCYX)A-Q@_oKPOhL+fJ{NPSwz3*A4sYu>(}4-^ih#$g!`T zg623cTguSvEqhX_D|*=JHpMv4!}lL-xC3tU8`sAuQQ=|^C@pQQ|X&55kWsk#wociW9V0Bpnw$#oM}B^|1jt$^uiskeI#w>jtfF%vV&7Q7v* zZs@1(Rj3>OjlZFRI9+UdG+<^Lz3NoK&t6F!<$k6n7P*goBr@BKOA$|sLQ0AvO6tP3 z5AcnbSfBMdJQY>r7uiv3DmTTn6yu-5e!l#1HhOLjm+iISF z$PO;w=c$OkLB}enLYbe!+V{M{*d(mP+a(tm`DQ|VjZk8fI^uL=GR z@`xahx4_>-Y!$o+ejIiW_#5nXbJ)uB*Vw4+E#&d4i1SjOzYIQtoZi*){1|uv_FuqX zg#Qchw@auXavR22ZBU7lK4cBH`9 z`MAyf?nvBi_Peg$;!mOisbZ{ffK6kyqEd2CEi1VPe0MD)_jnC^T&(REyJ|hbzHE84 zF9Jd12MT6~sUDl-`{aJlS&y!21L6ey-k$5Id20ixH6eoPJS?gW_K4JM@tpI}X4Kfc z4>>KglQKrjs>fzm)+V)joc(C&UVMA;W(Ipv>d$GJU_tLFs7`N3J-V55Y+ixVSM9!k zDV?wH=qTAz$u4zErJWt6_m=K}l8x+6EXngm?y9_3@vXDB_x#Pr6MwnUdw??v(RVF3 zIs=>oEFcZ^K(EKFJlA80_uWR=JUqH1mqrE5g3sAyJk_5tj`Vkp-!*n8<}apK>LIz> z<4__ortImG*44V(Jlk$Bt>5j1H8<+Tzcd1b0MW$HRotQWl6Y_3m6J3=>$pMtz}Io3 XV-s^fQ=G&@@drEox1E1AY_k0W-uvO= literal 732 zcmZPwU{Kh~$iTrsCfEqnJBkru;QvLQ&Hn>KYMKgzf`GT6mt=#A4=qJXUmA?0fIJ|rB$W^ar2jERCCp3cO_-I*=IQi-gK1WxPr`|Wf6o~Nm>d`w z{{LWj%kY4KhtUBjvft3x$jivP)@4=1%ZM%~kxSQ{4ZQhWUPh>WU}oo*6>yVxVR*n| z%#*R(Nz%>X2aETQi$EDR7BeFkb#IUk-b>7e!m=l&6hAOCvKTTb2!hpjI|(F6x&68* z?&*#H0l diff --git a/F1-nolib/led_blink/systick_blink.c_bkp b/F1-nolib/led_blink/main.c similarity index 55% rename from F1-nolib/led_blink/systick_blink.c_bkp rename to F1-nolib/led_blink/main.c index 4f021bf..e3245f1 100644 --- a/F1-nolib/led_blink/systick_blink.c_bkp +++ b/F1-nolib/led_blink/main.c @@ -1,7 +1,7 @@ /* - * systick_blink.c + * main.c * - * Copyright 2017 Edward V. Emelianoff + * Copyright 2018 Edward V. Emelianov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,30 +21,24 @@ #include "stm32f1.h" -static volatile uint8_t blink_ctr = 0; +static volatile uint32_t blink_ctr = 0; /* Called when systick fires */ void sys_tick_handler(void){ ++blink_ctr; } -/* - * Set up timer to fire every x milliseconds - */ +// SysTick is 24 bit counter, so 16777215 - max value!!! +// After HSE is ON it works @9MHz (????) static void systick_setup(uint32_t xms){ static uint32_t curms = 0; if(curms == xms) return; - // 6MHz - HCLK/8 (due to HPRE=1 HCLK=SYSCLK) // this function also clears counter so it starts right away - SysTick_Config(6000 * xms); + SysTick_Config(72000 * xms); curms = xms; } - -/* set STM32 to clock by 48MHz from HSI oscillator */ -//static void clock_setup(void){ - //StartHSE(RCC_CR_CSSON | RCC_CR_HSEBYP); -//} +static const uint16_t L[] = {125,100,125,100,125,200, 60,100,60,100,60,200, 125,100,125,100,125, 230}; static void gpio_setup(void){ /* Enable clocks to the GPIO subsystems (A&B) */ @@ -56,42 +50,13 @@ static void gpio_setup(void){ GPIOC->CRL = CRL(0, CNF_PUDINPUT|MODE_INPUT) | CRL(1, CNF_PUDINPUT|MODE_INPUT); } -static const uint16_t L[] = {125,100,125,100,125,200, 350,100,350,100,350,200, 125,100,125,100,125, 1000}; - -int main(void){ +int main(){ sysreset(); - // AFIO->MAPR = AFIO_MAPR_SWJ_CFG_DISABLE; // turn off jtag and swim - // StartHSE(); - -RCC->CFGR &= ~RCC_CFGR_SW; // Change System Clock to HSI - while ((RCC->CFGR & RCC_CFGR_SWS) != 0x00) { - __NOP(); - }; - RCC->CR &= ~RCC_CR_PLLON; // Disable Pll - while ((RCC->CR & RCC_CR_PLLON)) { - __NOP(); - }; - RCC->CFGR &= ~0x3C0000; - RCC->CFGR |= RCC_CFGR_PLLMULL4; // Set Pll Mul to 4 - RCC->CFGR |= RCC_CFGR_USBPRE; - RCC->CFGR |= RCC_CFGR_PLLSRC; - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLON)) { - __NOP(); - }; - RCC->CFGR |= RCC_CFGR_SW_1; // Change System Clock to PLL - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1) { - __NOP(); - }; - + StartHSE(); gpio_setup(); - - /* 500ms ticks => 1000ms period => 1Hz blinks */ systick_setup(100); - uint8_t oldctr = blink_ctr+1; - pin_clear(GPIOB, 1<<8); - pin_clear(GPIOB, 1<<9); - for(int i = 0; i < 1000000; ++i) nop(); + uint32_t oldctr = 0xff; + pin_clear(GPIOB, 3<<8); /* Do nothing in main loop */ while (1){ if(pin_read(GPIOC, 1) && pin_read(GPIOC, 2)){ // no buttons present - morze @ LED1 (PB9) @@ -103,13 +68,22 @@ RCC->CFGR &= ~RCC_CFGR_SW; // Change System Clock to HSI oldctr = blink_ctr; } }else{ // button pressed: turn ON given LED - if(pin_read(GPIOC, 1)){ // PC0 pressed (button S2) - pin_clear(GPIOB, 1<<8); - }else pin_set(GPIOB, 1<<8); - if(pin_read(GPIOC, 2)){ // PC1 pressed (button S3) - pin_clear(GPIOB, 1<<9); + if(pin_read(GPIOC, 1) == 0){ // PC0 pressed (button S2) + systick_setup(5); + if(blink_ctr - oldctr > 499){ + pin_toggle(GPIOB, 1<<9); + oldctr = blink_ctr; + } + }else pin_set(GPIOB, 1<<9); + if(pin_read(GPIOC, 2) == 0){ // PC1 pressed (button S3) + systick_setup(1); + if(blink_ctr - oldctr > 499){ + pin_toggle(GPIOB, 1<<8); + oldctr = blink_ctr; + } }else pin_set(GPIOB, 1<<8); } } } + diff --git a/F1-nolib/led_blink/systick_blink.c b/F1-nolib/led_blink/systick_blink.c deleted file mode 100644 index 72c34cb..0000000 --- a/F1-nolib/led_blink/systick_blink.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * systick_blink.c - * - * Copyright 2017 Edward V. Emelianoff - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include "stm32f1.h" - -int main(void){ - sysreset(); - RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; - GPIOB->CRH = 0x00000066; // PB8/9 - 2MHz opendrain - GPIOB->ODR = 0; - while(1){} - return 0; -} diff --git a/F1-nolib/led_blink/systick_blink.c_notwork b/F1-nolib/led_blink/systick_blink.c_notwork deleted file mode 100644 index ea33a5a..0000000 --- a/F1-nolib/led_blink/systick_blink.c_notwork +++ /dev/null @@ -1,30 +0,0 @@ -/* - * systick_blink.c - * - * Copyright 2017 Edward V. Emelianoff - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include "stm32f1.h" - -int main(void){ - RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; - GPIOB->CRH = 0x00000066; // PB8/9 - 2MHz opendrain - GPIOB->ODR = 0; - while(1){} - return 0; -}