mirror of
https://github.com/eddyem/scorpio.git
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add code for STM8-based 2stepper management board
This commit is contained in:
eddyem
40
STM8/2stepper4reductor/Makefile
Normal file
40
STM8/2stepper4reductor/Makefile
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@@ -0,0 +1,40 @@
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NAME=twosteppers
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SDCC=sdcc
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||||
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CCFLAGS=-DSTM8S105 -I../ -I/usr/share/sdcc/include -mstm8 --out-fmt-ihx
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||||
LDFLAGS= -mstm8 --out-fmt-ihx -lstm8
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||||
FLASHFLAGS=-cstlinkv2 -pstm8s105?4
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SRC=$(wildcard *.c)
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OBJ=$(SRC:%.c=%.rel)
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TRASH=$(OBJ) $(SRC:%.c=%.rst) $(SRC:%.c=%.asm) $(SRC:%.c=%.lst)
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TRASH+=$(SRC:%.c=%.sym) $(NAME).lk $(NAME).map $(NAME).cdb
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INDEPENDENT_HEADERS=../stm8l.h ports_definition.h Makefile
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all: $(NAME).ihx
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#$(SRC) : %.c : %.h $(INDEPENDENT_HEADERS)
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# @touch $@
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#
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#%.h: ;
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clean:
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rm -f $(TRASH)
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load: $(NAME).ihx
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stm8flash $(FLASHFLAGS) -w $(NAME).ihx
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gentags:
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CFLAGS="$(CFLAGS) $(DEFS)" geany -g $(NAME).c.tags *[hc] 2>/dev/null
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%.rel: %.c
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$(SDCC) $(CCFLAGS) -c $<
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bin: $(NAME).ihx
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objcopy -I ihex -O binary $< $(NAME).bin
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$(NAME).ihx: $(OBJ)
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$(SDCC) $(LDFLAGS) $(OBJ) -o $(NAME).ihx
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.PHONY: clean load gentags
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0
STM8/2stepper4reductor/Readme
Normal file
0
STM8/2stepper4reductor/Readme
Normal file
92
STM8/2stepper4reductor/hardware.c
Normal file
92
STM8/2stepper4reductor/hardware.c
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@@ -0,0 +1,92 @@
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/*
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* geany_encoding=koi8-r
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* hardware.c
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*
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* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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||||
* MA 02110-1301, USA.
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||||
*
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*/
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#include "hardware.h"
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volatile unsigned long Global_time = 0L; // global time in ms
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U8 MCU_no = 0; // unit number read from onboard jumpers
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void hw_init(){
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CFG_GCR |= 1; // disable SWIM
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// Configure clocking
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CLK_CKDIVR = 0; // F_HSI = 16MHz, f_CPU = 16MHz
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// Timer 4 (8 bit) used as system tick timer
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// prescaler == 128 (2^7), Tfreq = 125kHz
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// period = 1ms, so ARR = 125
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TIM4_PSCR = 7;
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TIM4_ARR = 125;
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// interrupts: update
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TIM4_IER = TIM_IER_UIE;
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// auto-reload + interrupt on overflow + enable
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TIM4_CR1 = TIM_CR1_APRE | TIM_CR1_URS | TIM_CR1_CEN;
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// GPIO; ODR-write, IDR-read, DDR-direction, CR1-pullup/pushpull, CR2-exti/speed
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PB_DDR = 0x0f; // motor0
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PB_CR1 = 0x0f;
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PC_DDR = LED_PIN | PWM_PINS; // LED, PWM
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PC_CR1 = LED_PIN | PWM_PINS;
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PC_CR2 = PWM_PINS;
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PD_DDR = 0x0f; // motor 1
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PD_CR1 = 0x0f;
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// end-switches
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PORT(M0E1_PORT, CR1) |= M0E1_PIN;
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PORT(M0E2_PORT, CR1) |= M0E2_PIN;
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PORT(M1E1_PORT, CR1) |= M1E1_PIN;
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PORT(M1E2_PORT, CR1) |= M1E2_PIN;
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// default state setters
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LED_OFF();
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// Setup watchdog
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IWDG_KR = KEY_ENABLE; // start watchdog
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IWDG_KR = KEY_ACCESS; // enable access to protected registers
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IWDG_PR = 6; // /256
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IWDG_RLR = 0xff; // max time for watchdog (1.02s)
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IWDG_KR = KEY_REFRESH;
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// get board address
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MCU_no = GET_ADDR();
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// Configure timer 1 - PWM outputs
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// prescaler = f_{in}/f_{tim1} - 1
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// set Timer1 to 0.2MHz: 16/.2 - 1 = 79 (p-channel mosfet is too slow!)
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TIM1_PSCRH = 0;
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TIM1_PSCRL = 79; // LSB should be written last as it updates prescaler
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// auto-reload each 256ticks:
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TIM1_ARRH = 0x0;
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TIM1_ARRL = 0xFF;
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// P-channel opendrain mosfets are closed
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TIM1_CCR1H = 0;
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TIM1_CCR1L = 0;
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TIM1_CCR2H = 0;
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TIM1_CCR2L = 0;
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TIM1_CCR3H = 0;
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TIM1_CCR3L = 0;
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// interrupts: none
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// PWM mode 2 - OC1M = 111
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TIM1_CCMR1 = 0x70; TIM1_CCMR2 = 0x70; TIM1_CCMR3 = 0x70;
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TIM1_CCER1 = 0x11; // CC1E, CC2E
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TIM1_CCER2 = 0x01; // CC3E
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// auto-reload
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TIM1_CR1 = TIM_CR1_APRE | TIM_CR1_CEN;
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TIM1_BKR |= 1<<7; // MOE - enable main output
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}
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97
STM8/2stepper4reductor/hardware.h
Normal file
97
STM8/2stepper4reductor/hardware.h
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@@ -0,0 +1,97 @@
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/*
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* hardware.h - definition of ports pins & so on
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*
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* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
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||||
*/
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#pragma once
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#ifndef __HARDWARE_H__
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#define __HARDWARE_H__
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#include "stm8s.h"
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extern volatile unsigned long Global_time; // global time in ms
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extern U8 MCU_no;
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// macro for using in port constructions like PORT(LED_PORT, ODR) = xx
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#define FORMPORT(a, b) a ## _ ## b
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#define PORT(a, b) FORMPORT(a , b)
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#define CONCAT(a, b) a ## b
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/**
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* HW:
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* PB0-3 motor0 push-pull output
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* PB4 M0E1 pullup input
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* PB5 M0E2 pullup input
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* PC1-3 PWM push-pull output
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* PC4 - LED push-pull output
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* PC5-7 Addr floating input (externall pull-down)
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* PD0-3 motor1 push-pull output
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* PD4 M1E1 pullup input
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* PD5 - Tx open-drain output \ UART
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* PD6 - Rx floating input /
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* PD7 M1E2 pullup input
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*/
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// PWM
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#define PWM_PINS (7<<1)
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// LED
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#define LED_PORT PC
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#define LED_PIN GPIO_PIN4
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// Address
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#define ADDR_MASK (7<<5)
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#define GET_ADDR() ((PC_IDR & ADDR_MASK)>>5)
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// UART2_TX
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#define UART_PORT PD
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#define UART_TX_PIN GPIO_PIN5
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// steppers
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#define STP0_PORT PB
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#define STP1_PORT PD
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#define STP_PINS (0x0f)
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// end-switches
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#define M0E1_PORT PB
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#define M0E2_PORT PB
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#define M1E1_PORT PD
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#define M1E2_PORT PD
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#define M0E1_PIN (1<<4)
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#define M0E2_PIN (1<<5)
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#define M1E1_PIN (1<<7)
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#define M1E2_PIN (1<<4)
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// getters: 1 active, 0 inactive
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// inverse state of LED
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#define LED_NSTATE() (PORT(LED_PORT, ODR) & LED_PIN)
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// end-switches (0 - shuttered)
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#define CHK_M0E1() (0 == (PORT(M0E1_PORT, IDR) & M0E1_PIN))
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#define CHK_M0E2() (0 == (PORT(M0E2_PORT, IDR) & M0E2_PIN))
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#define CHK_M1E1() (0 == (PORT(M1E1_PORT, IDR) & M1E1_PIN))
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#define CHK_M1E2() (0 == (PORT(M1E2_PORT, IDR) & M1E2_PIN))
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// setters
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#define LED_OFF() (PORT(LED_PORT, ODR) |= LED_PIN)
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#define LED_ON() (PORT(LED_PORT, ODR) &= ~LED_PIN)
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// getters
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void hw_init();
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#endif // __HARDWARE_H__
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203
STM8/2stepper4reductor/interrupts.c
Normal file
203
STM8/2stepper4reductor/interrupts.c
Normal file
@@ -0,0 +1,203 @@
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/*
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* interrupts.c
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||||
*
|
||||
* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
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||||
#include "hardware.h"
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#include "uart.h"
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#include "motors.h"
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// Top Level Interrupt
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INTERRUPT_HANDLER(TLI_IRQHandler, 0){}
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// Auto Wake Up Interrupt
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INTERRUPT_HANDLER(AWU_IRQHandler, 1){}
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||||
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// Clock Controller Interrupt
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INTERRUPT_HANDLER(CLK_IRQHandler, 2){}
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||||
// External Interrupt PORTA
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INTERRUPT_HANDLER(EXTI_PORTA_IRQHandler, 3){}
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// External Interrupt PORTB
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INTERRUPT_HANDLER(EXTI_PORTB_IRQHandler, 4){}
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||||
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||||
// External Interrupt PORTC
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||||
INTERRUPT_HANDLER(EXTI_PORTC_IRQHandler, 5){
|
||||
}
|
||||
|
||||
// External Interrupt PORTD
|
||||
INTERRUPT_HANDLER(EXTI_PORTD_IRQHandler, 6){
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||||
}
|
||||
|
||||
// External Interrupt PORTE
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||||
INTERRUPT_HANDLER(EXTI_PORTE_IRQHandler, 7){}
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||||
|
||||
#ifdef STM8S903
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||||
// External Interrupt PORTF
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||||
INTERRUPT_HANDLER(EXTI_PORTF_IRQHandler, 8){}
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||||
#endif // STM8S903
|
||||
|
||||
#if defined (STM8S208) || defined (STM8AF52Ax)
|
||||
// CAN RX Interrupt routine.
|
||||
INTERRUPT_HANDLER(CAN_RX_IRQHandler, 8){}
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||||
|
||||
// CAN TX Interrupt routine.
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||||
INTERRUPT_HANDLER(CAN_TX_IRQHandler, 9){}
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||||
#endif // STM8S208 || STM8AF52Ax
|
||||
|
||||
// SPI Interrupt routine.
|
||||
INTERRUPT_HANDLER(SPI_IRQHandler, 10){}
|
||||
|
||||
// Timer1 Update/Overflow/Trigger/Break Interrupt
|
||||
INTERRUPT_HANDLER(TIM1_UPD_OVF_TRG_BRK_IRQHandler, 11){
|
||||
}
|
||||
|
||||
// Timer1 Capture/Compare Interrupt routine.
|
||||
INTERRUPT_HANDLER(TIM1_CAP_COM_IRQHandler, 12){}
|
||||
|
||||
#ifdef STM8S903
|
||||
// Timer5 Update/Overflow/Break/Trigger Interrupt
|
||||
INTERRUPT_HANDLER(TIM5_UPD_OVF_BRK_TRG_IRQHandler, 13){}
|
||||
|
||||
// Timer5 Capture/Compare Interrupt
|
||||
INTERRUPT_HANDLER(TIM5_CAP_COM_IRQHandler, 14){}
|
||||
|
||||
#else // STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF62Ax or STM8AF52Ax or STM8AF626x
|
||||
|
||||
// Timer2 Update/Overflow/Break Interrupt
|
||||
INTERRUPT_HANDLER(TIM2_UPD_OVF_BRK_IRQHandler, 13){
|
||||
if(TIM2_SR1 & TIM_SR1_UIF){
|
||||
TIM2_SR1 &= ~TIM_SR1_UIF; // take off flag
|
||||
//irq_flag |= 1;
|
||||
stepper_interrupt(0);
|
||||
}
|
||||
}
|
||||
|
||||
// Timer2 Capture/Compare Interrupt
|
||||
INTERRUPT_HANDLER(TIM2_CAP_COM_IRQHandler, 14){
|
||||
}
|
||||
#endif // STM8S903
|
||||
|
||||
#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
|
||||
defined(STM8S005) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8AF626x)
|
||||
// Timer3 Update/Overflow/Break Interrupt
|
||||
INTERRUPT_HANDLER(TIM3_UPD_OVF_BRK_IRQHandler, 15){
|
||||
if(TIM3_SR1 & TIM_SR1_UIF){
|
||||
TIM3_SR1 &= ~TIM_SR1_UIF;
|
||||
//irq_flag |= 2;
|
||||
stepper_interrupt(1);
|
||||
}
|
||||
}
|
||||
|
||||
// Timer3 Capture/Compare Interrupt
|
||||
INTERRUPT_HANDLER(TIM3_CAP_COM_IRQHandler, 16){}
|
||||
#endif // STM8S208, STM8S207 or STM8S105 or STM8AF62Ax or STM8AF52Ax or STM8AF626x
|
||||
|
||||
#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S103) || \
|
||||
defined(STM8S003) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8S903)
|
||||
// UART1 TX Interrupt
|
||||
INTERRUPT_HANDLER(UART1_TX_IRQHandler, 17){}
|
||||
|
||||
// UART1 RX Interrupt
|
||||
INTERRUPT_HANDLER(UART1_RX_IRQHandler, 18){}
|
||||
#endif // STM8S208 or STM8S207 or STM8S103 or STM8S903 or STM8AF62Ax or STM8AF52Ax
|
||||
|
||||
// I2C Interrupt
|
||||
INTERRUPT_HANDLER(I2C_IRQHandler, 19){}
|
||||
|
||||
#if defined(STM8S105) || defined(STM8S005) || defined (STM8AF626x)
|
||||
// UART2 TX interrupt
|
||||
INTERRUPT_HANDLER(UART2_TX_IRQHandler, 20){
|
||||
if(UART2_SR & UART_SR_TXE){
|
||||
if(tx_len == 0){
|
||||
UART2_CR2 &= ~UART_CR2_TIEN; // disable TXE interrupt
|
||||
tx_idx = 0;
|
||||
return;
|
||||
}
|
||||
if(tx_idx < tx_len){
|
||||
UART2_DR = UART_tx[tx_idx++];
|
||||
}else{
|
||||
UART2_CR2 &= ~UART_CR2_TIEN;
|
||||
tx_idx = 0;
|
||||
tx_len = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// UART2 RX interrupt
|
||||
INTERRUPT_HANDLER(UART2_RX_IRQHandler, 21){
|
||||
U8 rb;
|
||||
static U8 msg_begin = 0;
|
||||
if(UART2_SR & UART_SR_RXNE){ // data received
|
||||
rb = UART2_DR; // read received byte & clear RXNE flag
|
||||
if(uart_rdy) return; // forget new data while old didn't managed
|
||||
if(rb == ' ' || rb == '\t' || rb == '\r' || rb == '\n') return; // omit spaces
|
||||
if(rb == '['){
|
||||
msg_begin = 1;
|
||||
rx_idx = 0; // start of message
|
||||
return;
|
||||
}
|
||||
if(!msg_begin) return; // no message data
|
||||
if(rx_idx == UART_BUF_LEN-1 && rb != ']'){ // Oops: buffer overflow! Just forget old data
|
||||
rx_idx = 0;
|
||||
return;
|
||||
}
|
||||
if(rb == ']'){
|
||||
msg_begin = 0;
|
||||
if(rx_idx) uart_rdy = 1; // don't set ready flag for empty messages
|
||||
UART_rx[rx_idx] = 0;
|
||||
}else UART_rx[rx_idx++] = rb; // put received byte into cycled buffer
|
||||
}
|
||||
}
|
||||
|
||||
#endif // STM8S105 or STM8AF626x
|
||||
|
||||
#if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
|
||||
// UART3 TX interrupt
|
||||
INTERRUPT_HANDLER(UART3_TX_IRQHandler, 20){}
|
||||
|
||||
// UART3 RX interrupt
|
||||
INTERRUPT_HANDLER(UART3_RX_IRQHandler, 21){}
|
||||
#endif // STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax
|
||||
|
||||
#if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
|
||||
// ADC2 interrupt
|
||||
INTERRUPT_HANDLER(ADC2_IRQHandler, 22){}
|
||||
#else
|
||||
// ADC1 interrupt
|
||||
INTERRUPT_HANDLER(ADC1_IRQHandler, 22){
|
||||
}
|
||||
#endif // STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax
|
||||
|
||||
#ifdef STM8S903
|
||||
// Timer6 Update/Overflow/Trigger Interrupt
|
||||
INTERRUPT_HANDLER(TIM6_UPD_OVF_TRG_IRQHandler, 23){}
|
||||
#else // STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF52Ax or STM8AF62Ax or STM8AF626x
|
||||
// Timer4 Update/Overflow Interrupt
|
||||
INTERRUPT_HANDLER(TIM4_UPD_OVF_IRQHandler, 23){
|
||||
if(TIM4_SR & TIM_SR1_UIF){ // update interrupt
|
||||
Global_time++; // increase timer
|
||||
}
|
||||
TIM4_SR = 0; // clear all interrupt flags
|
||||
}
|
||||
#endif // STM8S903
|
||||
|
||||
// Eeprom EEC Interrupt
|
||||
INTERRUPT_HANDLER(EEPROM_EEC_IRQHandler, 24){}
|
||||
55
STM8/2stepper4reductor/main.c
Normal file
55
STM8/2stepper4reductor/main.c
Normal file
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* main.c
|
||||
*
|
||||
* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
#include "hardware.h"
|
||||
#include "interrupts.h"
|
||||
#include "uart.h"
|
||||
#include "proto.h"
|
||||
#include "motors.h"
|
||||
|
||||
int main() {
|
||||
char A[3] = {'x', '\n', 0};
|
||||
unsigned long T = 0L;
|
||||
|
||||
if(RST_SR) RST_SR = 0x1f; // clear reset flags writing 1
|
||||
hw_init();
|
||||
motors_init();
|
||||
uart_init();
|
||||
// enable all interrupts
|
||||
enableInterrupts();
|
||||
// remove this code if nesessary
|
||||
uart_write("\n\nHello! My address is ");
|
||||
A[0] = MCU_no + '0';
|
||||
uart_write(A);
|
||||
show_help(); // show protocol help @start
|
||||
// Loop
|
||||
do{
|
||||
/*if(Global_time - T > paused_val){
|
||||
}*/
|
||||
IWDG_KR = KEY_REFRESH; // refresh watchdog
|
||||
if(uart_rdy){
|
||||
process_string();
|
||||
}
|
||||
process_stepper(0);
|
||||
process_stepper(1);
|
||||
}while(1);
|
||||
}
|
||||
|
||||
|
||||
423
STM8/2stepper4reductor/motors.c
Normal file
423
STM8/2stepper4reductor/motors.c
Normal file
@@ -0,0 +1,423 @@
|
||||
/*
|
||||
* geany_encoding=koi8-r
|
||||
* motors.c
|
||||
*
|
||||
* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
#include "motors.h"
|
||||
#include "uart.h"
|
||||
#include "hardware.h"
|
||||
|
||||
//U8 irq_flag = 0; // |1 - 1st motor, |2 - second
|
||||
|
||||
// motor states
|
||||
typedef enum{
|
||||
MOTOR_RELAX, // do nothing
|
||||
MOTOR_INFMOVE, // infinite moving
|
||||
MOTOR_STOP, // stop
|
||||
MOTOR_ZEROSTOP, // stop and set current position to zero
|
||||
MOTOR_MOVENSTEPS, // move for N steps
|
||||
MOTOR_OFFSWITCH, // try to pull off the positive switch (for turrets and to return from switch back)
|
||||
} motor_state;
|
||||
|
||||
// direction of rotation
|
||||
typedef enum{
|
||||
DIR_CW, // clockwise
|
||||
DIR_CCW, // counter-clockwise
|
||||
DIR_STOP // stopped
|
||||
} motor_direction;
|
||||
|
||||
static U16 Stepper_speed[2] = {DEFAULT_USTEP_PERIOD, DEFAULT_USTEP_PERIOD}; // length of one MICROstep in us
|
||||
static volatile motor_direction Dir[2] = {DIR_STOP, DIR_STOP}; // direction of moving
|
||||
static volatile motor_state state[2] = {MOTOR_RELAX, MOTOR_RELAX};
|
||||
static long Steps_left[2] = {0,0}; // steppers left (when moving for given steps amount)
|
||||
static long Current_pos[2] = {0,0}; // current position
|
||||
static long Steps_left_at_esw[2] = {0,0}; // amount of `Steps_left` when MOTOR_OFFSWITCH activated
|
||||
static U16 Acceleration[2] = {0, 0}; // current acceleration (to reach target speed by ACCEL_STEPS microsteps)
|
||||
|
||||
// microsteps profile
|
||||
// microsteps: DCBA = 1000, 1010, 0010, 0110, 0100, 0101, 0001, 1001 - half-step
|
||||
// 1010, 0110, 0101, 1001 - full step
|
||||
static const U8 usteps[8] = {0b1000, 0b1010, 0b0010, 0b0110, 0b0100, 0b0101, 0b0001, 0b1001};
|
||||
static U8 Ustep[2] = {0, 0}; // microstep counter
|
||||
|
||||
// init timers & GPIO for motors
|
||||
void motors_init(){
|
||||
// Configure timer 2 to generate signals for CLK of motor 0
|
||||
TIM2_PSCR = 4; // 1MHz
|
||||
TIM2_ARRH = DEFAULT_USTEP_PERIOD >> 8; // set speed
|
||||
TIM2_ARRL = DEFAULT_USTEP_PERIOD & 0xff;
|
||||
TIM2_IER = TIM_IER_UIE; // update interrupt enable
|
||||
TIM2_CR1 |= TIM_CR1_APRE | TIM_CR1_URS; // auto reload + interrupt on overflow
|
||||
// timer 3 for motor 1
|
||||
TIM3_PSCR = 4;
|
||||
TIM3_ARRH = DEFAULT_USTEP_PERIOD >> 8;
|
||||
TIM3_ARRL = DEFAULT_USTEP_PERIOD & 0xff;
|
||||
TIM3_IER = TIM_IER_UIE;
|
||||
TIM3_CR1 |= TIM_CR1_APRE | TIM_CR1_URS;
|
||||
}
|
||||
|
||||
void show_motors_help(){
|
||||
// "start end"
|
||||
uart_write("\tE - get end-switches\n");
|
||||
uart_write("\tL - move CCW\n");
|
||||
uart_write("\tM - get motor state\n");
|
||||
uart_write("\tN - go for N st./get rest\n");
|
||||
uart_write("\tO - pull off the switch\n");
|
||||
uart_write("\tP - get current position\n");
|
||||
uart_write("\tR - move CW\n");
|
||||
uart_write("\tS - get/set speed\n");
|
||||
uart_write("\tX - stop motor\n");
|
||||
uart_write("\tZ - stop and zero position\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* Check endswitches
|
||||
* @return 0 if none pressed, 1 if "-", 2 if "+", 3 if both!
|
||||
*/
|
||||
static U8 check_endsw(U8 motor){
|
||||
U8 ret = 0;
|
||||
switch(motor){
|
||||
case 0:
|
||||
if(CHK_M0E1()) ++ret;
|
||||
if(CHK_M0E2()) ret += 2;
|
||||
break;
|
||||
case 1:
|
||||
if(CHK_M1E1()) ++ret;
|
||||
if(CHK_M1E2()) ret += 2;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void stop_motor(U8 motorNum){
|
||||
// stop timers & turn off power
|
||||
switch(motorNum){
|
||||
case 0:
|
||||
PORT(STP0_PORT, ODR) &= ~STP_PINS;
|
||||
TIM2_CR1 &= ~TIM_CR1_CEN;
|
||||
break;
|
||||
case 1:
|
||||
PORT(STP1_PORT, ODR) &= ~STP_PINS;
|
||||
TIM3_CR1 &= ~TIM_CR1_CEN;
|
||||
break;
|
||||
default: return;
|
||||
}
|
||||
Steps_left[motorNum] = 0;
|
||||
Ustep[motorNum] = 0;
|
||||
Dir[motorNum] = DIR_STOP;
|
||||
}
|
||||
|
||||
static void strtobuf(const char *str, char **buff){
|
||||
while(*str) *((*buff)++) = *str++;
|
||||
}
|
||||
|
||||
static void get_motor_state(U8 nmotor, char **buff){
|
||||
char sig = '+';
|
||||
if(nmotor > 1) return;
|
||||
if(Dir[nmotor] == DIR_CCW) sig = '-';
|
||||
switch(state[nmotor]){
|
||||
case MOTOR_RELAX:
|
||||
strtobuf("RELAX", buff);
|
||||
break;
|
||||
case MOTOR_INFMOVE:
|
||||
strtobuf("INFMV", buff); // INVMV+ or INFMV-
|
||||
*((*buff)++) = sig;
|
||||
break;
|
||||
break;
|
||||
case MOTOR_STOP:
|
||||
strtobuf("STOP", buff);
|
||||
break;
|
||||
case MOTOR_MOVENSTEPS:
|
||||
strtobuf("MVSTP", buff); // MVSTP+ or MVSTP-
|
||||
*((*buff)++) = sig;
|
||||
break;
|
||||
case MOTOR_OFFSWITCH:
|
||||
strtobuf("OFFSW", buff); // OFFSW+ or OFFSW-
|
||||
*((*buff)++) = sig;
|
||||
break;
|
||||
default:
|
||||
strtobuf("UNDEF", buff);
|
||||
}
|
||||
}
|
||||
|
||||
// turn on motor's timer starting from the lowest speed
|
||||
static void turnontimer(U8 motorNum){
|
||||
switch(motorNum){
|
||||
case 0:
|
||||
TIM2_ARRH = MAX_USTEP_PERIOD >> 8;
|
||||
TIM2_ARRL = MAX_USTEP_PERIOD & 0xff;
|
||||
TIM2_CR1 |= TIM_CR1_CEN;
|
||||
break;
|
||||
case 1:
|
||||
TIM3_ARRH = MAX_USTEP_PERIOD >> 8;
|
||||
TIM3_ARRL = MAX_USTEP_PERIOD & 0xff;
|
||||
TIM3_CR1 |= TIM_CR1_CEN;
|
||||
break;
|
||||
default: return;
|
||||
}
|
||||
Acceleration[motorNum] = 1 + (MAX_USTEP_PERIOD - Stepper_speed[motorNum]) / ACCEL_USTEPS;
|
||||
}
|
||||
|
||||
/**
|
||||
* try to move motor motorNum for nsteps
|
||||
* @return 1 if all OK; 0 if still moving or on end-switch
|
||||
*/
|
||||
static int moveNsteps(U8 motorNum, long nsteps){
|
||||
U8 sw;
|
||||
if(Dir[motorNum] != DIR_STOP) return 0;
|
||||
sw = check_endsw(motorNum);
|
||||
if(nsteps < 0){
|
||||
if(sw) return 0; // on zero end-switch: no moving backward, on positive - no moving at all!
|
||||
Dir[motorNum] = DIR_CCW;
|
||||
nsteps = -nsteps;
|
||||
Ustep[motorNum] = 7;
|
||||
state[motorNum] = MOTOR_MOVENSTEPS;
|
||||
}else{
|
||||
if(sw & 2) return 0; // for positive direction no moving to any side when on end-switch 2!
|
||||
else if(sw & 1) state[motorNum] = MOTOR_OFFSWITCH;
|
||||
else state[motorNum] = MOTOR_MOVENSTEPS;
|
||||
Dir[motorNum] = DIR_CW;
|
||||
}
|
||||
Steps_left[motorNum] = nsteps;
|
||||
// turn On timer
|
||||
turnontimer(motorNum);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* try to move motor motorNum off the end-switch for nsteps
|
||||
* @return 1 if all OK; 0 if still moving, motor is @ zero endswitch
|
||||
*/
|
||||
static int pullofftheswitch(U8 motorNum, long nsteps){
|
||||
U8 sw;
|
||||
if(Dir[motorNum] != DIR_STOP) return 0;
|
||||
sw = check_endsw(motorNum);
|
||||
if(sw == 0) return moveNsteps(motorNum, nsteps);
|
||||
if(nsteps < 0){
|
||||
if(sw & 1) return 0; // on zero end-switch: no moving backward
|
||||
Dir[motorNum] = DIR_CCW;
|
||||
nsteps = -nsteps;
|
||||
Ustep[motorNum] = 7;
|
||||
}else{
|
||||
Dir[motorNum] = DIR_CW;
|
||||
}
|
||||
Steps_left[motorNum] = nsteps;
|
||||
Steps_left_at_esw[motorNum] = nsteps;
|
||||
state[motorNum] = MOTOR_OFFSWITCH;
|
||||
turnontimer(motorNum);
|
||||
return 1;
|
||||
}
|
||||
|
||||
void motor_command(const char *cmd, char **buff){
|
||||
U8 motorNum = *cmd++ - '0';
|
||||
U16 spd;
|
||||
long l;
|
||||
char c;
|
||||
if(motorNum > 1) goto someerr;
|
||||
*((*buff)++) = '0' + motorNum;
|
||||
*((*buff)++) = ' ';
|
||||
c = *cmd++;
|
||||
*((*buff)++) = c; *((*buff)++) = ' ';
|
||||
switch(c){
|
||||
case 'E': // check endswitches state
|
||||
*((*buff)++) = '0' + check_endsw(motorNum);
|
||||
break;
|
||||
case 'L': // infinite move left
|
||||
if(1 == check_endsw(motorNum)){
|
||||
*((*buff)++) = 'E'; *((*buff)++) = ' ';
|
||||
*((*buff)++) = '1';
|
||||
}else{
|
||||
state[motorNum] = MOTOR_INFMOVE;
|
||||
Dir[motorNum] = DIR_CCW;
|
||||
Ustep[motorNum] = 7;
|
||||
turnontimer(motorNum);
|
||||
}
|
||||
break;
|
||||
case 'M': // get motor state
|
||||
get_motor_state(motorNum, buff);
|
||||
break;
|
||||
case 'N': // go for N steps or get steps left
|
||||
if(!readLong(cmd, &l)){ // get
|
||||
long2buf(Steps_left[motorNum], buff);
|
||||
}else{
|
||||
if(!moveNsteps(motorNum, l)) goto someerr;
|
||||
else long2buf(l, buff);
|
||||
}
|
||||
break;
|
||||
case 'O': // pull off the switch (if no steps given, go for PULLOFFTHESW_STEPS)
|
||||
if(!readLong(cmd, &l)){ // get
|
||||
l = PULLOFFTHESW_STEPS;
|
||||
}
|
||||
if(!pullofftheswitch(motorNum, l)) goto someerr;
|
||||
else long2buf(l, buff);
|
||||
break;
|
||||
case 'P': // get current position
|
||||
long2buf(Current_pos[motorNum], buff);
|
||||
break;
|
||||
case 'R': // infinite move right
|
||||
if(2 == check_endsw(motorNum)){
|
||||
*((*buff)++) = 'E'; *((*buff)++) = ' ';
|
||||
*((*buff)++) = '2';
|
||||
}else{
|
||||
state[motorNum] = MOTOR_INFMOVE;
|
||||
Dir[motorNum] = DIR_CW;
|
||||
turnontimer(motorNum);
|
||||
}
|
||||
break;
|
||||
case 'S': // change speed
|
||||
if(!readLong(cmd, &l) || l < MIN_USTEP_PERIOD || l > MAX_USTEP_PERIOD){ // get speed
|
||||
if(motorNum == 0) spd = TIM2_ARRH << 8 | TIM2_ARRL;
|
||||
else spd = TIM3_ARRH << 8 | TIM3_ARRL;
|
||||
long2buf(spd, buff);
|
||||
}else{
|
||||
long2buf(l, buff);
|
||||
spd = (U16)l;
|
||||
Stepper_speed[motorNum] = spd;
|
||||
Acceleration[motorNum] = 0;
|
||||
if(motorNum == 0){
|
||||
TIM2_ARRH = spd >> 8;
|
||||
TIM2_ARRL = spd & 0xff;
|
||||
}else{
|
||||
TIM3_ARRH = spd >> 8;
|
||||
TIM3_ARRL = spd & 0xff;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 'X': // stop
|
||||
state[motorNum] = MOTOR_STOP;
|
||||
break;
|
||||
case 'Z':
|
||||
state[motorNum] = MOTOR_ZEROSTOP;
|
||||
break;
|
||||
default: // return err
|
||||
goto someerr;
|
||||
}
|
||||
return;
|
||||
someerr:
|
||||
*((*buff)++) = 'e';
|
||||
*((*buff)++) = 'r';
|
||||
*((*buff)++) = 'r';
|
||||
}
|
||||
|
||||
/**
|
||||
* this function calls from timer interrupt (TIM2 or TIM3 - motors 0/1)
|
||||
*/
|
||||
void stepper_interrupt(U8 motor_num){
|
||||
U8 tmp;
|
||||
U16 spd;
|
||||
//irq_flag ^= 1 << motor_num;
|
||||
switch(motor_num){
|
||||
case 0:
|
||||
if(Acceleration[0]){
|
||||
spd = (TIM2_ARRH << 8 | TIM2_ARRL) - Acceleration[0];
|
||||
if(spd < Stepper_speed[0]){
|
||||
spd = Stepper_speed[0];
|
||||
Acceleration[0] = 0;
|
||||
}
|
||||
//printUint((U8*)&spd, 2);
|
||||
//uart_write(" - speed0\n");
|
||||
TIM2_ARRH = spd >> 8;
|
||||
TIM2_ARRL = spd & 0xff;
|
||||
}
|
||||
tmp = PORT(STP0_PORT, ODR) & ~STP_PINS;
|
||||
PORT(STP0_PORT, ODR) = tmp | usteps[Ustep[0]];
|
||||
break;
|
||||
case 1:
|
||||
if(Acceleration[1]){
|
||||
spd = (TIM3_ARRH << 8 | TIM3_ARRL) - Acceleration[1];
|
||||
if(spd < Stepper_speed[1]){
|
||||
spd = Stepper_speed[1];
|
||||
Acceleration[1] = 0;
|
||||
}
|
||||
//printUint((U8*)&spd, 2);
|
||||
//uart_write(" - speed1\n");
|
||||
TIM3_ARRH = spd >> 8;
|
||||
TIM3_ARRL = spd & 0xff;
|
||||
}
|
||||
tmp = PORT(STP1_PORT, ODR) & ~STP_PINS;
|
||||
PORT(STP1_PORT, ODR) = tmp | usteps[Ustep[1]];
|
||||
break;
|
||||
default: return;
|
||||
}
|
||||
if(Dir[motor_num] == DIR_CCW){ // counter-clockwise
|
||||
if(Ustep[motor_num] == 0){
|
||||
--Steps_left[motor_num];
|
||||
--Current_pos[motor_num];
|
||||
if(state[motor_num] == MOTOR_STOP || state[motor_num] == MOTOR_ZEROSTOP){
|
||||
stop_motor(motor_num);
|
||||
return;
|
||||
}
|
||||
Ustep[motor_num] = 7;
|
||||
}else --Ustep[motor_num];
|
||||
}else{ // clockwise
|
||||
if(++Ustep[motor_num] > 7){
|
||||
--Steps_left[motor_num];
|
||||
++Current_pos[motor_num];
|
||||
if(state[motor_num] == MOTOR_STOP || state[motor_num] == MOTOR_ZEROSTOP){
|
||||
stop_motor(motor_num);
|
||||
return;
|
||||
}
|
||||
Ustep[motor_num] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Main state-machine process
|
||||
*/
|
||||
void process_stepper(U8 motor_num){
|
||||
U8 sw = check_endsw(motor_num);
|
||||
U8 ccw = (Dir[motor_num] == DIR_CCW) ? 1 : 0;
|
||||
switch(state[motor_num]){
|
||||
case MOTOR_OFFSWITCH: // don't care about endswitch for first PULLOFFTHESW_STEPS steps
|
||||
if(Steps_left[motor_num] < 2) state[motor_num] = MOTOR_STOP;
|
||||
else if(Steps_left_at_esw[motor_num] - Steps_left[motor_num] >= PULLOFFTHESW_STEPS)
|
||||
state[motor_num] = MOTOR_MOVENSTEPS;
|
||||
break;
|
||||
case MOTOR_MOVENSTEPS:
|
||||
if(Steps_left[motor_num] < 2) state[motor_num] = MOTOR_STOP; // stop @given position
|
||||
case MOTOR_INFMOVE: // set curpos to zero only in this state (after reaching ESW1)
|
||||
if(sw){
|
||||
if(ccw){
|
||||
if(state[motor_num] == MOTOR_INFMOVE){
|
||||
if(sw & 1) state[motor_num] = MOTOR_ZEROSTOP; // esw1 - stop @ zero when inf. left move
|
||||
}else state[motor_num] = MOTOR_STOP; // just stop at any esw in steps move
|
||||
}else{ // +switch when move CW
|
||||
if(sw & 2) state[motor_num] = MOTOR_STOP; // stop in CW only on esw2 !!!
|
||||
}
|
||||
}
|
||||
break;
|
||||
case MOTOR_STOP:
|
||||
if(Dir[motor_num] == DIR_STOP){
|
||||
state[motor_num] = MOTOR_RELAX;
|
||||
}
|
||||
break;
|
||||
case MOTOR_ZEROSTOP:
|
||||
if(Dir[motor_num] == DIR_STOP){
|
||||
Current_pos[motor_num] = 0;
|
||||
state[motor_num] = MOTOR_RELAX;
|
||||
}
|
||||
break;
|
||||
default: return; // MOTOR_RELAX
|
||||
}
|
||||
//if(irq_flag & (1<<motor_num)) stepper_interrupt(motor_num);
|
||||
}
|
||||
49
STM8/2stepper4reductor/motors.h
Normal file
49
STM8/2stepper4reductor/motors.h
Normal file
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* geany_encoding=koi8-r
|
||||
* motors.h
|
||||
*
|
||||
* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
#pragma once
|
||||
#ifndef __MOTORS_H__
|
||||
#define __MOTORS_H__
|
||||
|
||||
// default speed @ start - 50 steps per second
|
||||
#define DEFAULT_USTEP_PERIOD (2500)
|
||||
// max speed == 1/(625us*8) = 200 steps per second
|
||||
#define MIN_USTEP_PERIOD (625)
|
||||
// min speed as 16-bit timer can - 65535 - near 1.9 steps per second
|
||||
// default min speed - 10 steps per second
|
||||
#define MAX_USTEP_PERIOD (12500)
|
||||
// amount of steps to pull off the switch
|
||||
#define PULLOFFTHESW_STEPS (100)
|
||||
// amount of microsteps for acceleration calculation
|
||||
#define ACCEL_USTEPS (200)
|
||||
|
||||
//extern unsigned char irq_flag;
|
||||
|
||||
void motors_init();
|
||||
void show_motors_help();
|
||||
void motor_command(const char *cmd, char **bufptr);
|
||||
|
||||
void stepper_interrupt(unsigned char motor_num);
|
||||
|
||||
void process_stepper(unsigned char stepno);
|
||||
|
||||
#endif // __MOTORS_H__
|
||||
166
STM8/2stepper4reductor/proto.c
Normal file
166
STM8/2stepper4reductor/proto.c
Normal file
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
* geany_encoding=koi8-r
|
||||
* proto.c - base protocol definitions
|
||||
*
|
||||
* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
#include "proto.h"
|
||||
#include "hardware.h"
|
||||
#include "uart.h"
|
||||
#include "motors.h"
|
||||
|
||||
// input command buffer
|
||||
static char ibuf[UART_BUF_LEN];
|
||||
// buffer for output data
|
||||
static char obuf[UART_BUF_LEN] = "[ X "; // constant initializer
|
||||
|
||||
void show_help(){
|
||||
// uart_write transfer not more than UART_BUF_LEN bytes!
|
||||
// "start end"
|
||||
uart_write("\n\n");
|
||||
uart_write("Command protocol: [ addr command");
|
||||
uart_write(" data ]\n\t broadcast addr: " BROADCAST_CHAR "\n");
|
||||
uart_write("commands:\n");
|
||||
uart_write("0/1 - command for given motor:\n");
|
||||
show_motors_help();
|
||||
uart_write("r - reset MCU\n");
|
||||
uart_write("G - get board address\n");
|
||||
uart_write("L 0/1 - LED on/off\n");
|
||||
uart_write("P ch val - PWM on channel ch\n");
|
||||
uart_write("T - time counter value\n");
|
||||
uart_write("\n\n");
|
||||
}
|
||||
|
||||
static void set_PWM(char *cmd, char **buff){
|
||||
U8 s = 0;
|
||||
long l;
|
||||
U8 N = *cmd++ - '0';
|
||||
if(N > 2){
|
||||
long2buf(-1, buff); // error: answer with Nch = -1
|
||||
return;
|
||||
}
|
||||
*((*buff)++) = '0' + N;
|
||||
*((*buff)++) = ' ';
|
||||
if(*cmd == 0){ // check PWM value
|
||||
switch (N){
|
||||
case 0:
|
||||
s = TIM1_CCR1L;
|
||||
break;
|
||||
case 1:
|
||||
s = TIM1_CCR2L;
|
||||
break;
|
||||
case 2:
|
||||
s = TIM1_CCR3L;
|
||||
break;
|
||||
}
|
||||
}else{
|
||||
if(!readLong(cmd, &l) || l < 0 || l > 255){
|
||||
long2buf(-1, buff); // error: answer with PWM = -1
|
||||
return;
|
||||
}
|
||||
s = (U8) l;
|
||||
switch (N){
|
||||
case 0:
|
||||
TIM1_CCR1L = s;
|
||||
break;
|
||||
case 1:
|
||||
TIM1_CCR2L = s;
|
||||
break;
|
||||
case 2:
|
||||
TIM1_CCR3L = s;
|
||||
break;
|
||||
}
|
||||
}
|
||||
long2buf(s, buff);
|
||||
}
|
||||
|
||||
// @return 0 in case of error
|
||||
// @param cmd - string with command sequence
|
||||
static U8 process_commands(char *cmd){
|
||||
char s, *bufptr = &obuf[4];
|
||||
static const char* const endline = " ]\n";
|
||||
IWDG_KR = KEY_REFRESH; // refresh watchdog
|
||||
// uart_write("got command: ");
|
||||
// uart_write(cmd);
|
||||
s = *cmd;
|
||||
obuf[2] = MCU_no + '0';
|
||||
if(s == '0' || s == '1'){
|
||||
motor_command(cmd, &bufptr);
|
||||
goto eof;
|
||||
}
|
||||
*bufptr++ = s;
|
||||
*bufptr++ = ' ';
|
||||
++cmd;
|
||||
switch(s){
|
||||
case 'r':
|
||||
IWDG_KR = KEY_ACCESS;
|
||||
IWDG_PR = 0;
|
||||
IWDG_RLR = 0x1;
|
||||
IWDG_KR = KEY_REFRESH;
|
||||
while(1);
|
||||
break;
|
||||
case 'G':
|
||||
*bufptr++ = '0' + MCU_no;
|
||||
break;
|
||||
case 'L': // LED on/off
|
||||
if(*cmd){ // if there's no number after LED command - just check its state
|
||||
if(*cmd == '0'){
|
||||
LED_OFF();
|
||||
}else{
|
||||
LED_ON();
|
||||
}
|
||||
}
|
||||
*bufptr++ = LED_NSTATE() ? '0' : '1';
|
||||
break;
|
||||
case 'P':
|
||||
set_PWM(cmd, &bufptr);
|
||||
break;
|
||||
case 'T':
|
||||
*bufptr = 0;
|
||||
uart_write(obuf);
|
||||
printUint((U8*)&Global_time, 4);
|
||||
uart_write(endline);
|
||||
return 1;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
eof:
|
||||
*bufptr = 0;
|
||||
uart_write(obuf);
|
||||
uart_write(endline);
|
||||
return 1;
|
||||
}
|
||||
|
||||
void process_string(){
|
||||
U8 ctr;
|
||||
char *iptr = ibuf, *optr = &UART_rx[1];
|
||||
U8 mcuno = (U8)UART_rx[0] - '0';
|
||||
if(uart_rdy == 0) return;
|
||||
if(mcuno != MCU_no && mcuno != BROADCAST_ADDR){ // alien message
|
||||
uart_rdy = 0;
|
||||
rx_idx = 0;
|
||||
return;
|
||||
}
|
||||
// rx_idx is length of incoming message; next char is '\0', copy it too
|
||||
for(ctr = 0; ctr < rx_idx; ++ctr) *iptr++ = *optr++;
|
||||
rx_idx = 0; uart_rdy = 0; // command read, buffer ready to get more data
|
||||
if(!process_commands(ibuf)) show_help();
|
||||
}
|
||||
|
||||
35
STM8/2stepper4reductor/proto.h
Normal file
35
STM8/2stepper4reductor/proto.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* geany_encoding=koi8-r
|
||||
* proto.h
|
||||
*
|
||||
* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#ifndef __PROTO_H__
|
||||
#define __PROTO_H__
|
||||
|
||||
// broadcast commands should be sent to this address
|
||||
#define BROADCAST_CHAR "b"
|
||||
#define BROADCAST_ADDR ((U8)('b' - '0'))
|
||||
|
||||
void process_string();
|
||||
void show_help();
|
||||
|
||||
#endif // __PROTO_H__
|
||||
568
STM8/2stepper4reductor/stm8s.h
Normal file
568
STM8/2stepper4reductor/stm8s.h
Normal file
@@ -0,0 +1,568 @@
|
||||
/*
|
||||
* stm8s.h
|
||||
*
|
||||
* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
|
||||
#pragma once
|
||||
#ifndef __STM8L_H__
|
||||
#define __STM8L_H__
|
||||
|
||||
typedef unsigned char U8;
|
||||
typedef unsigned int U16;
|
||||
typedef unsigned long U32;
|
||||
#define NULL (void*)0
|
||||
|
||||
/* functions */
|
||||
#define enableInterrupts() {__asm__("rim\n");} // enable interrupts
|
||||
#define disableInterrupts() {__asm__("sim\n");} // disable interrupts
|
||||
#define iret() {__asm__("iret\n");} // Interrupt routine return
|
||||
#define pop_ccr() {__asm__("pop cc\n");} // Pop CCR from the stack
|
||||
#define push_ccr() {__asm__("push cc\n");}// Push CCR on the stack
|
||||
#define rim() {__asm__("rim\n");} // enable interrupts
|
||||
#define sim() {__asm__("sim\n");} // disable interrupts
|
||||
#define nop() {__asm__("nop\n");} // No Operation
|
||||
#define trap() {__asm__("trap\n");} // Trap (soft IT)
|
||||
#define wfi() {__asm__("wfi\n");} // Wait For Interrupt
|
||||
#define halt() {__asm__("halt\n");} // Halt
|
||||
|
||||
/*
|
||||
* Registers map is shown in short datasheet, page 26
|
||||
*/
|
||||
/* GPIO */
|
||||
#define PA_ODR *(unsigned char*)0x5000
|
||||
#define PA_IDR *(unsigned char*)0x5001
|
||||
#define PA_DDR *(unsigned char*)0x5002
|
||||
#define PA_CR1 *(unsigned char*)0x5003
|
||||
#define PA_CR2 *(unsigned char*)0x5004
|
||||
|
||||
#define PB_ODR *(unsigned char*)0x5005
|
||||
#define PB_IDR *(unsigned char*)0x5006
|
||||
#define PB_DDR *(unsigned char*)0x5007
|
||||
#define PB_CR1 *(unsigned char*)0x5008
|
||||
#define PB_CR2 *(unsigned char*)0x5009
|
||||
|
||||
#define PC_ODR *(unsigned char*)0x500A
|
||||
#define PC_IDR *(unsigned char*)0x500B
|
||||
#define PC_DDR *(unsigned char*)0x500C
|
||||
#define PC_CR1 *(unsigned char*)0x500D
|
||||
#define PC_CR2 *(unsigned char*)0x500E
|
||||
|
||||
#define PD_ODR *(unsigned char*)0x500F
|
||||
#define PD_IDR *(unsigned char*)0x5010
|
||||
#define PD_DDR *(unsigned char*)0x5011
|
||||
#define PD_CR1 *(unsigned char*)0x5012
|
||||
#define PD_CR2 *(unsigned char*)0x5013
|
||||
|
||||
#define PE_ODR *(unsigned char*)0x5014
|
||||
#define PE_IDR *(unsigned char*)0x5015
|
||||
#define PE_DDR *(unsigned char*)0x5016
|
||||
#define PE_CR1 *(unsigned char*)0x5017
|
||||
#define PE_CR2 *(unsigned char*)0x5018
|
||||
|
||||
#define PF_ODR *(unsigned char*)0x5019
|
||||
#define PF_IDR *(unsigned char*)0x501A
|
||||
#define PF_DDR *(unsigned char*)0x501B
|
||||
#define PF_CR1 *(unsigned char*)0x501C
|
||||
#define PF_CR2 *(unsigned char*)0x501D
|
||||
|
||||
#ifdef STM8S105
|
||||
#define PG_ODR *(unsigned char*)0x501E
|
||||
#define PG_IDR *(unsigned char*)0x501F
|
||||
#define PG_DDR *(unsigned char*)0x5020
|
||||
#define PG_CR1 *(unsigned char*)0x5021
|
||||
#define PG_CR2 *(unsigned char*)0x5022
|
||||
|
||||
#define PH_ODR *(unsigned char*)0x5023
|
||||
#define PH_IDR *(unsigned char*)0x5024
|
||||
#define PH_DDR *(unsigned char*)0x5025
|
||||
#define PH_CR1 *(unsigned char*)0x5026
|
||||
#define PH_CR2 *(unsigned char*)0x5027
|
||||
|
||||
#define PI_ODR *(unsigned char*)0x5028
|
||||
#define PI_IDR *(unsigned char*)0x5029
|
||||
#define PI_DDR *(unsigned char*)0x502A
|
||||
#define PI_CR1 *(unsigned char*)0x502B
|
||||
#define PI_CR2 *(unsigned char*)0x502C
|
||||
#endif // STM8S105
|
||||
|
||||
/* GPIO bits */
|
||||
#define GPIO_PIN0 (1 << 0)
|
||||
#define GPIO_PIN1 (1 << 1)
|
||||
#define GPIO_PIN2 (1 << 2)
|
||||
#define GPIO_PIN3 (1 << 3)
|
||||
#define GPIO_PIN4 (1 << 4)
|
||||
#define GPIO_PIN5 (1 << 5)
|
||||
#define GPIO_PIN6 (1 << 6)
|
||||
#define GPIO_PIN7 (1 << 7)
|
||||
|
||||
/* -------------------- FLASH/EEPROM -------------------- */
|
||||
#define FLASH_CR1 *(unsigned char*)0x505A
|
||||
#define FLASH_CR2 *(unsigned char*)0x505B
|
||||
#define FLASH_NCR2 *(unsigned char*)0x505C
|
||||
#define FLASH_FPR *(unsigned char*)0x505D
|
||||
#define FLASH_NFPR *(unsigned char*)0x505E
|
||||
#define FLASH_IAPSR *(unsigned char*)0x505F
|
||||
#define FLASH_PUKR *(unsigned char*)0x5062 // progmem unprotection
|
||||
#define FLASH_DUKR *(unsigned char*)0x5064 // EEPROM unprotection
|
||||
|
||||
#define EEPROM_KEY1 0xAE // keys to manage EEPROM's write access
|
||||
#define EEPROM_KEY2 0x56
|
||||
#define EEPROM_START_ADDR (unsigned char*)0x4000
|
||||
|
||||
/* ------------------- interrupts ------------------- */
|
||||
#define EXTI_CR1 *(unsigned char*)0x50A0
|
||||
#define EXTI_CR2 *(unsigned char*)0x50A1
|
||||
#define INTERRUPT_HANDLER(fn, num) void fn() __interrupt(num)
|
||||
#define INTERRUPT_DEFINITION(fn, num) extern void fn() __interrupt(num)
|
||||
|
||||
// Reset status register
|
||||
#define RST_SR *(unsigned char*)0x50B3
|
||||
|
||||
/* ------------------- CLOCK ------------------- */
|
||||
#define CLK_ICKR *(unsigned char*)0x50C0
|
||||
#define CLK_ECKR *(unsigned char*)0x50C1
|
||||
#define CLK_CMSR *(unsigned char*)0x50C3
|
||||
#define CLK_SWR *(unsigned char*)0x50C4
|
||||
#define CLK_SWCR *(unsigned char*)0x50C5
|
||||
#define CLK_CKDIVR *(unsigned char*)0x50C6
|
||||
#define CLK_SPCKENR1 *(unsigned char*)0x50C7
|
||||
#define CLK_CSSR *(unsigned char*)0x50C8
|
||||
#define CLK_CCOR *(unsigned char*)0x50C9
|
||||
#define CLK_PCKENR2 *(unsigned char*)0x50CA
|
||||
#define CLK_HSITRIMR *(unsigned char*)0x50CC
|
||||
#define CLK_SWIMCCR *(unsigned char*)0x50CD
|
||||
|
||||
/* ------------------- Watchdog ------------------ */
|
||||
#define WWDG_CR *(unsigned char*)0x50D1
|
||||
#define WWDG_WR *(unsigned char*)0x50D2
|
||||
#define IWDG_KR *(unsigned char*)0x50E0
|
||||
#define IWDG_PR *(unsigned char*)0x50E1
|
||||
#define IWDG_RLR *(unsigned char*)0x50E2
|
||||
// enable Watchdog
|
||||
#define KEY_ENABLE (0xCC)
|
||||
// refresh Watchdog from IWDG_RLR
|
||||
#define KEY_REFRESH (0xAA)
|
||||
// modify IWDG_PR and IWDG_RLR
|
||||
#define KEY_ACCESS (0x55)
|
||||
|
||||
|
||||
/* ------------------- AWU, BEEP ------------------- */
|
||||
#define AWU_CSR1 *(unsigned char*)0x50F0
|
||||
#define AWU_APR *(unsigned char*)0x50F1
|
||||
#define AWU_TBR *(unsigned char*)0x50F2
|
||||
#define BEEP_CSR *(unsigned char*)0x50F3
|
||||
|
||||
/* ------------------- SPI ------------------- */
|
||||
#define SPI_CR1 *(unsigned char*)0x5200
|
||||
#define SPI_CR2 *(unsigned char*)0x5201
|
||||
#define SPI_ICR *(unsigned char*)0x5202
|
||||
#define SPI_SR *(unsigned char*)0x5203
|
||||
#define SPI_DR *(unsigned char*)0x5204
|
||||
#define SPI_CRCPR *(unsigned char*)0x5205
|
||||
#define SPI_RXCRCR *(unsigned char*)0x5206
|
||||
#define SPI_TXCRCR *(unsigned char*)0x5207
|
||||
// SPI_CR1 (page 271): | LSBFIRST | SPE | BR[2:0] | MSTR | CPOL | CPHA |
|
||||
#define SPI_CR1_LSBFIRST (1<<7)
|
||||
#define SPI_CR1_SPE (1<<6)
|
||||
#define SPI_CR1_BRMASK (0x38)
|
||||
#define SPI_CR1_MSTR (1<<2)
|
||||
#define SPI_CR1_CPOL (1<<1)
|
||||
#define SPI_CR1_CPHA (1)
|
||||
// SPI_CR2 (page 272): | BDM | BDOE | CRCEN | CRCNEXT | - | RXONLY | SSM | SSI |
|
||||
#define SPI_CR2_BDM (1<<7)
|
||||
#define SPI_CR2_BDOE (1<<6)
|
||||
#define SPI_CR2_CRCEN (1<<5)
|
||||
#define SPI_CR2_CRCNEXT (1<<4)
|
||||
#define SPI_CR2_RXONLY (1<<2)
|
||||
#define SPI_CR2_SSM (1<<1)
|
||||
#define SPI_CR2_SSI (1)
|
||||
// SPI_ICR (page 273): | TXIE | RXIE | ERRIE | WKIE | - | - | - | - |
|
||||
#define SPI_ICR_TXIE (1<<7)
|
||||
#define SPI_ICR_RXIE (1<<6)
|
||||
#define SPI_ICR_ERRIE (1<<5)
|
||||
#define SPI_ICR_WKIE (1<<4)
|
||||
// SPI_SR (page 274): | BSY | OVR | MODF | CRCERR | WKUP | - | TXE | RXNE |
|
||||
#define SPI_SR_BSY (1<<7)
|
||||
#define SPI_SR_OVR (1<<6)
|
||||
#define SPI_SR_MODF (1<<5)
|
||||
#define SPI_SR_CRCERR (1<<4)
|
||||
#define SPI_SR_WKUP (1<<3)
|
||||
#define SPI_SR_TXE (1<<1)
|
||||
#define SPI_SR_RXNE (1)
|
||||
|
||||
/* ------------------- I2C ------------------- */
|
||||
#define I2C_CR1 *(unsigned char*)0x5210
|
||||
#define I2C_CR2 *(unsigned char*)0x5211
|
||||
#define I2C_FREQR *(unsigned char*)0x5212
|
||||
#define I2C_OARL *(unsigned char*)0x5213
|
||||
#define I2C_OARH *(unsigned char*)0x5214
|
||||
#define I2C_DR *(unsigned char*)0x5216
|
||||
#define I2C_SR1 *(unsigned char*)0x5217
|
||||
#define I2C_SR2 *(unsigned char*)0x5218
|
||||
#define I2C_SR3 *(unsigned char*)0x5219
|
||||
#define I2C_ITR *(unsigned char*)0x521A
|
||||
#define I2C_CCRL *(unsigned char*)0x521B
|
||||
#define I2C_CCRH *(unsigned char*)0x521C
|
||||
#define I2C_TRISER *(unsigned char*)0x521D
|
||||
#define I2C_PECR *(unsigned char*)0x521E
|
||||
|
||||
/* ------------------- UART ------------------- */
|
||||
#if defined STM8S003 || defined STM8S103
|
||||
#define UART1_SR *(unsigned char*)0x5230
|
||||
#define UART1_DR *(unsigned char*)0x5231
|
||||
#define UART1_BRR1 *(unsigned char*)0x5232
|
||||
#define UART1_BRR2 *(unsigned char*)0x5233
|
||||
#define UART1_CR1 *(unsigned char*)0x5234
|
||||
#define UART1_CR2 *(unsigned char*)0x5235
|
||||
#define UART1_CR3 *(unsigned char*)0x5236
|
||||
#define UART1_CR4 *(unsigned char*)0x5237
|
||||
#define UART1_CR5 *(unsigned char*)0x5238
|
||||
#define UART1_GTR *(unsigned char*)0x5239
|
||||
#define UART1_PSCR *(unsigned char*)0x523A
|
||||
#endif // STM8S003
|
||||
#ifdef STM8S105
|
||||
#define UART2_SR *(unsigned char*)0x5240
|
||||
#define UART2_DR *(unsigned char*)0x5241
|
||||
#define UART2_BRR1 *(unsigned char*)0x5242
|
||||
#define UART2_BRR2 *(unsigned char*)0x5243
|
||||
#define UART2_CR1 *(unsigned char*)0x5244
|
||||
#define UART2_CR2 *(unsigned char*)0x5245
|
||||
#define UART2_CR3 *(unsigned char*)0x5246
|
||||
#define UART2_CR4 *(unsigned char*)0x5247
|
||||
#define UART2_CR5 *(unsigned char*)0x5248
|
||||
#define UART2_CR6 *(unsigned char*)0x5249
|
||||
#define UART2_GTR *(unsigned char*)0x524A
|
||||
#define UART2_PSCR *(unsigned char*)0x524B
|
||||
#endif // STM8S105
|
||||
|
||||
/* UART_CR1 bits */
|
||||
#define UART_CR1_R8 (1 << 7)
|
||||
#define UART_CR1_T8 (1 << 6)
|
||||
#define UART_CR1_UARTD (1 << 5)
|
||||
#define UART_CR1_M (1 << 4)
|
||||
#define UART_CR1_WAKE (1 << 3)
|
||||
#define UART_CR1_PCEN (1 << 2)
|
||||
#define UART_CR1_PS (1 << 1)
|
||||
#define UART_CR1_PIEN (1 << 0)
|
||||
|
||||
/* UART_CR2 bits */
|
||||
#define UART_CR2_TIEN (1 << 7)
|
||||
#define UART_CR2_TCIEN (1 << 6)
|
||||
#define UART_CR2_RIEN (1 << 5)
|
||||
#define UART_CR2_ILIEN (1 << 4)
|
||||
#define UART_CR2_TEN (1 << 3)
|
||||
#define UART_CR2_REN (1 << 2)
|
||||
#define UART_CR2_RWU (1 << 1)
|
||||
#define UART_CR2_SBK (1 << 0)
|
||||
|
||||
/* USART_CR3 bits */
|
||||
#define UART_CR3_LINEN (1 << 6)
|
||||
#define UART_CR3_STOP2 (1 << 5)
|
||||
#define UART_CR3_STOP1 (1 << 4)
|
||||
#define UART_CR3_CLKEN (1 << 3)
|
||||
#define UART_CR3_CPOL (1 << 2)
|
||||
#define UART_CR3_CPHA (1 << 1)
|
||||
#define UART_CR3_LBCL (1 << 0)
|
||||
|
||||
/* UART_SR bits */
|
||||
#define UART_SR_TXE (1 << 7)
|
||||
#define UART_SR_TC (1 << 6)
|
||||
#define UART_SR_RXNE (1 << 5)
|
||||
#define UART_SR_IDLE (1 << 4)
|
||||
#define UART_SR_OR (1 << 3)
|
||||
#define UART_SR_NF (1 << 2)
|
||||
#define UART_SR_FE (1 << 1)
|
||||
#define UART_SR_PE (1 << 0)
|
||||
|
||||
|
||||
/* ------------------- TIMERS ------------------- */
|
||||
/* TIM1 */
|
||||
#define TIM1_CR1 *(unsigned char*)0x5250
|
||||
#define TIM1_CR2 *(unsigned char*)0x5251
|
||||
#define TIM1_SMCR *(unsigned char*)0x5252
|
||||
#define TIM1_ETR *(unsigned char*)0x5253
|
||||
#define TIM1_IER *(unsigned char*)0x5254
|
||||
#define TIM1_SR1 *(unsigned char*)0x5255
|
||||
#define TIM1_SR2 *(unsigned char*)0x5256
|
||||
#define TIM1_EGR *(unsigned char*)0x5257
|
||||
#define TIM1_CCMR1 *(unsigned char*)0x5258
|
||||
#define TIM1_CCMR2 *(unsigned char*)0x5259
|
||||
#define TIM1_CCMR3 *(unsigned char*)0x525A
|
||||
#define TIM1_CCMR4 *(unsigned char*)0x525B
|
||||
#define TIM1_CCER1 *(unsigned char*)0x525C
|
||||
#define TIM1_CCER2 *(unsigned char*)0x525D
|
||||
#define TIM1_CNTRH *(unsigned char*)0x525E
|
||||
#define TIM1_CNTRL *(unsigned char*)0x525F
|
||||
#define TIM1_PSCRH *(unsigned char*)0x5260
|
||||
#define TIM1_PSCRL *(unsigned char*)0x5261
|
||||
#define TIM1_ARRH *(unsigned char*)0x5262
|
||||
#define TIM1_ARRL *(unsigned char*)0x5263
|
||||
#define TIM1_RCR *(unsigned char*)0x5264
|
||||
#define TIM1_CCR1H *(unsigned char*)0x5265
|
||||
#define TIM1_CCR1L *(unsigned char*)0x5266
|
||||
#define TIM1_CCR2H *(unsigned char*)0x5267
|
||||
#define TIM1_CCR2L *(unsigned char*)0x5268
|
||||
#define TIM1_CCR3H *(unsigned char*)0x5269
|
||||
#define TIM1_CCR3L *(unsigned char*)0x526A
|
||||
#define TIM1_CCR4H *(unsigned char*)0x526B
|
||||
#define TIM1_CCR4L *(unsigned char*)0x526C
|
||||
#define TIM1_BKR *(unsigned char*)0x526D
|
||||
#define TIM1_DTR *(unsigned char*)0x526E
|
||||
#define TIM1_OISR *(unsigned char*)0x526F
|
||||
|
||||
|
||||
/* TIM_IER bits */
|
||||
#define TIM_IER_BIE (1 << 7)
|
||||
#define TIM_IER_TIE (1 << 6)
|
||||
#define TIM_IER_COMIE (1 << 5)
|
||||
#define TIM_IER_CC4IE (1 << 4)
|
||||
#define TIM_IER_CC3IE (1 << 3)
|
||||
#define TIM_IER_CC2IE (1 << 2)
|
||||
#define TIM_IER_CC1IE (1 << 1)
|
||||
#define TIM_IER_UIE (1 << 0)
|
||||
|
||||
/* TIM_CR1 bits */
|
||||
#define TIM_CR1_APRE (1 << 7)
|
||||
#define TIM_CR1_CMSH (1 << 6)
|
||||
#define TIM_CR1_CMSL (1 << 5)
|
||||
#define TIM_CR1_DIR (1 << 4)
|
||||
#define TIM_CR1_OPM (1 << 3)
|
||||
#define TIM_CR1_URS (1 << 2)
|
||||
#define TIM_CR1_UDIS (1 << 1)
|
||||
#define TIM_CR1_CEN (1 << 0)
|
||||
|
||||
/* TIM_SR1 bits */
|
||||
#define TIM_SR1_BIF (1 << 7)
|
||||
#define TIM_SR1_TIF (1 << 6)
|
||||
#define TIM_SR1_COMIF (1 << 5)
|
||||
#define TIM_SR1_CC4IF (1 << 4)
|
||||
#define TIM_SR1_CC3IF (1 << 3)
|
||||
#define TIM_SR1_CC2IF (1 << 2)
|
||||
#define TIM_SR1_CC1IF (1 << 1)
|
||||
#define TIM_SR1_UIF (1 << 0)
|
||||
|
||||
/* TIM_EGR bits */
|
||||
#define TIM_EGR_BG (1 << 7)
|
||||
#define TIM_EGR_TG (1 << 6)
|
||||
#define TIM_EGR_COMG (1 << 5)
|
||||
#define TIM_EGR_CC4G (1 << 4)
|
||||
#define TIM_EGR_CC3G (1 << 3)
|
||||
#define TIM_EGR_CC2G (1 << 2)
|
||||
#define TIM_EGR_CC1G (1 << 1)
|
||||
#define TIM_EGR_UG (1 << 0)
|
||||
|
||||
|
||||
/* TIM2 */
|
||||
#define TIM2_CR1 *(unsigned char*)0x5300
|
||||
#if defined STM8S105 || defined STM8S103
|
||||
#define TIM2_IER *(unsigned char*)0x5301
|
||||
#define TIM2_SR1 *(unsigned char*)0x5302
|
||||
#define TIM2_SR2 *(unsigned char*)0x5303
|
||||
#define TIM2_EGR *(unsigned char*)0x5304
|
||||
#define TIM2_CCMR1 *(unsigned char*)0x5305
|
||||
#define TIM2_CCMR2 *(unsigned char*)0x5306
|
||||
#define TIM2_CCMR3 *(unsigned char*)0x5307
|
||||
#define TIM2_CCER1 *(unsigned char*)0x5308
|
||||
#define TIM2_CCER2 *(unsigned char*)0x5309
|
||||
#define TIM2_CNTRH *(unsigned char*)0x530A
|
||||
#define TIM2_CNTRL *(unsigned char*)0x530B
|
||||
#define TIM2_PSCR *(unsigned char*)0x530C
|
||||
#define TIM2_ARRH *(unsigned char*)0x530D
|
||||
#define TIM2_ARRL *(unsigned char*)0x530E
|
||||
#define TIM2_CCR1H *(unsigned char*)0x530F
|
||||
#define TIM2_CCR1L *(unsigned char*)0x5310
|
||||
#define TIM2_CCR2H *(unsigned char*)0x5311
|
||||
#define TIM2_CCR2L *(unsigned char*)0x5312
|
||||
#define TIM2_CCR3H *(unsigned char*)0x5313
|
||||
#define TIM2_CCR3L *(unsigned char*)0x5314
|
||||
#elif defined STM8S003
|
||||
#define TIM2_IER *(unsigned char*)0x5303
|
||||
#define TIM2_SR1 *(unsigned char*)0x5304
|
||||
#define TIM2_SR2 *(unsigned char*)0x5305
|
||||
#define TIM2_EGR *(unsigned char*)0x5306
|
||||
#define TIM2_CCMR1 *(unsigned char*)0x5307
|
||||
#define TIM2_CCMR2 *(unsigned char*)0x5308
|
||||
#define TIM2_CCMR3 *(unsigned char*)0x5309
|
||||
#define TIM2_CCER1 *(unsigned char*)0x530A
|
||||
#define TIM2_CCER2 *(unsigned char*)0x530B
|
||||
#define TIM2_CNTRH *(unsigned char*)0x530C
|
||||
#define TIM2_CNTRL *(unsigned char*)0x530D
|
||||
#define TIM2_PSCR *(unsigned char*)0x530E
|
||||
#define TIM2_ARRH *(unsigned char*)0x530F
|
||||
#define TIM2_ARRL *(unsigned char*)0x5310
|
||||
#define TIM2_CCR1H *(unsigned char*)0x5311
|
||||
#define TIM2_CCR1L *(unsigned char*)0x5312
|
||||
#define TIM2_CCR2H *(unsigned char*)0x5313
|
||||
#define TIM2_CCR2L *(unsigned char*)0x5314
|
||||
#define TIM2_CCR3H *(unsigned char*)0x5315
|
||||
#define TIM2_CCR3L *(unsigned char*)0x5316
|
||||
#endif
|
||||
|
||||
|
||||
/* TIM3 */
|
||||
#if defined STM8S105 || defined STM8S103
|
||||
#define TIM3_CR1 *(unsigned char*)0x5320
|
||||
#define TIM3_IER *(unsigned char*)0x5321
|
||||
#define TIM3_SR1 *(unsigned char*)0x5322
|
||||
#define TIM3_SR2 *(unsigned char*)0x5323
|
||||
#define TIM3_EGR *(unsigned char*)0x5324
|
||||
#define TIM3_CCMR1 *(unsigned char*)0x5325
|
||||
#define TIM3_CCMR2 *(unsigned char*)0x5326
|
||||
#define TIM3_CCER1 *(unsigned char*)0x5327
|
||||
#define TIM3_CNTRH *(unsigned char*)0x5328
|
||||
#define TIM3_CNTRL *(unsigned char*)0x5329
|
||||
#define TIM3_PSCR *(unsigned char*)0x532A
|
||||
#define TIM3_ARRH *(unsigned char*)0x532B
|
||||
#define TIM3_ARRL *(unsigned char*)0x532C
|
||||
#define TIM3_CCR1H *(unsigned char*)0x532D
|
||||
#define TIM3_CCR1L *(unsigned char*)0x532E
|
||||
#define TIM3_CCR2H *(unsigned char*)0x532F
|
||||
#define TIM3_CCR2L *(unsigned char*)0x5330
|
||||
#endif
|
||||
|
||||
/* TIM4 */
|
||||
#define TIM4_CR1 *(unsigned char*)0x5340
|
||||
#if defined STM8S105 || defined STM8S103
|
||||
#define TIM4_IER *(unsigned char*)0x5341
|
||||
#define TIM4_SR *(unsigned char*)0x5342
|
||||
#define TIM4_EGR *(unsigned char*)0x5343
|
||||
#define TIM4_CNTR *(unsigned char*)0x5344
|
||||
#define TIM4_PSCR *(unsigned char*)0x5345
|
||||
#define TIM4_ARR *(unsigned char*)0x5346
|
||||
#elif defined STM8S003
|
||||
#define TIM4_IER *(unsigned char*)0x5343
|
||||
#define TIM4_SR *(unsigned char*)0x5344
|
||||
#define TIM4_EGR *(unsigned char*)0x5345
|
||||
#define TIM4_CNTR *(unsigned char*)0x5346
|
||||
#define TIM4_PSCR *(unsigned char*)0x5347
|
||||
#define TIM4_ARR *(unsigned char*)0x5348
|
||||
#endif
|
||||
|
||||
/* ------------------- ADC ------------------- */
|
||||
#define ADC_DB0RH *(unsigned char*)0x53E0
|
||||
#define ADC_DB0RL *(unsigned char*)0x53E1
|
||||
#define ADC_DB1RH *(unsigned char*)0x53E2
|
||||
#define ADC_DB1RL *(unsigned char*)0x53E3
|
||||
#define ADC_DB2RH *(unsigned char*)0x53E4
|
||||
#define ADC_DB2RL *(unsigned char*)0x53E5
|
||||
#define ADC_DB3RH *(unsigned char*)0x53E6
|
||||
#define ADC_DB3RL *(unsigned char*)0x53E7
|
||||
#define ADC_DB4RH *(unsigned char*)0x53E8
|
||||
#define ADC_DB4RL *(unsigned char*)0x53E9
|
||||
#define ADC_DB5RH *(unsigned char*)0x53EA
|
||||
#define ADC_DB5RL *(unsigned char*)0x53EB
|
||||
#define ADC_DB6RH *(unsigned char*)0x53EC
|
||||
#define ADC_DB6RL *(unsigned char*)0x53ED
|
||||
#define ADC_DB7RH *(unsigned char*)0x53EE
|
||||
#define ADC_DB7RL *(unsigned char*)0x53EF
|
||||
#define ADC_DB8RH *(unsigned char*)0x53F0
|
||||
#define ADC_DB8RL *(unsigned char*)0x53F1
|
||||
#define ADC_DB9RH *(unsigned char*)0x53F2
|
||||
#define ADC_DB9RL *(unsigned char*)0x53F3
|
||||
#define ADC_CSR *(unsigned char*)0x5400
|
||||
#define ADC_CR1 *(unsigned char*)0x5401
|
||||
#define ADC_CR2 *(unsigned char*)0x5402
|
||||
#define ADC_CR3 *(unsigned char*)0x5403
|
||||
#define ADC_DRH *(unsigned char*)0x5404
|
||||
#define ADC_DRL *(unsigned char*)0x5405
|
||||
#define ADC_TDRH *(unsigned char*)0x5406
|
||||
#define ADC_TDRL *(unsigned char*)0x5407
|
||||
#define ADC_HTRH *(unsigned char*)0x5408
|
||||
#define ADC_HTRL *(unsigned char*)0x5409
|
||||
#define ADC_LTRH *(unsigned char*)0x540A
|
||||
#define ADC_LTRL *(unsigned char*)0x540B
|
||||
#define ADC_AWSRH *(unsigned char*)0x540C
|
||||
#define ADC_AWSRL *(unsigned char*)0x540D
|
||||
#define ADC_AWCRH *(unsigned char*)0x540E
|
||||
#define ADC_AWCRL *(unsigned char*)0x540F
|
||||
|
||||
/* ------------------- swim control ------------------- */
|
||||
#define CFG_GCR *(unsigned char*)0x7F60
|
||||
#define SWIM_CSR *(unsigned char*)0x7F80
|
||||
|
||||
/* ------------------- ITC ------------------- */
|
||||
#define ITC_SPR1 *(unsigned char*)0x7F70
|
||||
#define ITC_SPR2 *(unsigned char*)0x7F71
|
||||
#define ITC_SPR3 *(unsigned char*)0x7F72
|
||||
#define ITC_SPR4 *(unsigned char*)0x7F73
|
||||
#define ITC_SPR5 *(unsigned char*)0x7F74
|
||||
#define ITC_SPR6 *(unsigned char*)0x7F75
|
||||
#define ITC_SPR7 *(unsigned char*)0x7F76
|
||||
#define ITC_SPR8 *(unsigned char*)0x7F77
|
||||
|
||||
|
||||
/* -------------------- UNIQUE ID -------------------- */
|
||||
#if defined STM8S105 || defined STM8S103 // maybe some other MCU have this too???
|
||||
#define U_ID00 (unsigned char*)0x48CD
|
||||
#define U_ID01 (unsigned char*)0x48CE
|
||||
#define U_ID02 (unsigned char*)0x48CF
|
||||
#define U_ID03 (unsigned char*)0x48D0
|
||||
#define U_ID04 (unsigned char*)0x48D1
|
||||
#define U_ID05 (unsigned char*)0x48D2
|
||||
#define U_ID06 (unsigned char*)0x48D3
|
||||
#define U_ID07 (unsigned char*)0x48D4
|
||||
#define U_ID08 (unsigned char*)0x48D5
|
||||
#define U_ID09 (unsigned char*)0x48D6
|
||||
#define U_ID10 (unsigned char*)0x48D7
|
||||
#define U_ID11 (unsigned char*)0x48D8
|
||||
#endif // defined STM8S105 || defined STM8S103
|
||||
|
||||
// CCR REGISTER: bits 3&5 should be 1 if you wanna change EXTI_CRx
|
||||
#define CCR *(unsigned char*)0x7F0A
|
||||
|
||||
/* -------------------- OPTION BYTES -------------------- */
|
||||
#if defined STM8S105
|
||||
// readout protection
|
||||
#define OPT0 *(unsigned char*)0x4800
|
||||
// user boot code
|
||||
#define OPT1 *(unsigned char*)0x4801
|
||||
#define NOPT1 *(unsigned char*)0x4802
|
||||
// alternate functions remapping
|
||||
// | AFR7 | ... | AFR0 |
|
||||
// AFR7 - PD4 = BEEP; AFR6 - PB4/PB5 = I2C; AFR5 - PB0..3 - TIM1
|
||||
// AFR4 - PD7 = TIM1_CH4; AFR3 - PD0 = TIM1_BKIN
|
||||
// AFR2 - PD0 = CLK_CCO; AFR1 - PA3 = TIM3_CH1, PD2 = TIM2_CH3
|
||||
// AFR0 - PD3 = ADC_ETR
|
||||
#define OPT2 *(unsigned char*)0x4803
|
||||
#define NOPT2 *(unsigned char*)0x4804
|
||||
// trim, watchdog
|
||||
#define OPT3 *(unsigned char*)0x4805
|
||||
#define NOPT3 *(unsigned char*)0x4806
|
||||
// extclc, awu
|
||||
#define OPT4 *(unsigned char*)0x4807
|
||||
#define NOPT4 *(unsigned char*)0x4808
|
||||
// HSE stab time
|
||||
#define OPT5 *(unsigned char*)0x4809
|
||||
#define NOPT5 *(unsigned char*)0x480a
|
||||
// none
|
||||
#define OPT6 *(unsigned char*)0x480b
|
||||
#define NOPT6 *(unsigned char*)0x480c
|
||||
// none
|
||||
#define OPT7 *(unsigned char*)0x480d
|
||||
#define NOPT7 *(unsigned char*)0x480e
|
||||
// bootloader opt byte
|
||||
#define OPTBL *(unsigned char*)0x487e
|
||||
#define NOPTBL *(unsigned char*)0x487f
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __STM8L_H__
|
||||
|
||||
// #define *(unsigned char*)0x
|
||||
BIN
STM8/2stepper4reductor/twosteppers.bin
Normal file
BIN
STM8/2stepper4reductor/twosteppers.bin
Normal file
Binary file not shown.
629
STM8/2stepper4reductor/twosteppers.c.tags
Normal file
629
STM8/2stepper4reductor/twosteppers.c.tags
Normal file
@@ -0,0 +1,629 @@
|
||||
# format=tagmanager
|
||||
ADC_AWCRHÌ65536Ö0
|
||||
ADC_AWCRLÌ65536Ö0
|
||||
ADC_AWSRHÌ65536Ö0
|
||||
ADC_AWSRLÌ65536Ö0
|
||||
ADC_CR1Ì65536Ö0
|
||||
ADC_CR2Ì65536Ö0
|
||||
ADC_CR3Ì65536Ö0
|
||||
ADC_CSRÌ65536Ö0
|
||||
ADC_DB0RHÌ65536Ö0
|
||||
ADC_DB0RLÌ65536Ö0
|
||||
ADC_DB1RHÌ65536Ö0
|
||||
ADC_DB1RLÌ65536Ö0
|
||||
ADC_DB2RHÌ65536Ö0
|
||||
ADC_DB2RLÌ65536Ö0
|
||||
ADC_DB3RHÌ65536Ö0
|
||||
ADC_DB3RLÌ65536Ö0
|
||||
ADC_DB4RHÌ65536Ö0
|
||||
ADC_DB4RLÌ65536Ö0
|
||||
ADC_DB5RHÌ65536Ö0
|
||||
ADC_DB5RLÌ65536Ö0
|
||||
ADC_DB6RHÌ65536Ö0
|
||||
ADC_DB6RLÌ65536Ö0
|
||||
ADC_DB7RHÌ65536Ö0
|
||||
ADC_DB7RLÌ65536Ö0
|
||||
ADC_DB8RHÌ65536Ö0
|
||||
ADC_DB8RLÌ65536Ö0
|
||||
ADC_DB9RHÌ65536Ö0
|
||||
ADC_DB9RLÌ65536Ö0
|
||||
ADC_DRHÌ65536Ö0
|
||||
ADC_DRLÌ65536Ö0
|
||||
ADC_HTRHÌ65536Ö0
|
||||
ADC_HTRLÌ65536Ö0
|
||||
ADC_LTRHÌ65536Ö0
|
||||
ADC_LTRLÌ65536Ö0
|
||||
ADC_TDRHÌ65536Ö0
|
||||
ADC_TDRLÌ65536Ö0
|
||||
ADDR_MASKÌ65536Ö0
|
||||
AWU_APRÌ65536Ö0
|
||||
AWU_CSR1Ì65536Ö0
|
||||
AWU_TBRÌ65536Ö0
|
||||
BEEP_CSRÌ65536Ö0
|
||||
CCRÌ65536Ö0
|
||||
CFG_GCRÌ65536Ö0
|
||||
CHK_M0E1Ì131072Í()Ö0
|
||||
CHK_M0E2Ì131072Í()Ö0
|
||||
CHK_M1E1Ì131072Í()Ö0
|
||||
CHK_M1E2Ì131072Í()Ö0
|
||||
CLK_CCORÌ65536Ö0
|
||||
CLK_CKDIVRÌ65536Ö0
|
||||
CLK_CMSRÌ65536Ö0
|
||||
CLK_CSSRÌ65536Ö0
|
||||
CLK_ECKRÌ65536Ö0
|
||||
CLK_HSITRIMRÌ65536Ö0
|
||||
CLK_ICKRÌ65536Ö0
|
||||
CLK_PCKENR2Ì65536Ö0
|
||||
CLK_SPCKENR1Ì65536Ö0
|
||||
CLK_SWCRÌ65536Ö0
|
||||
CLK_SWIMCCRÌ65536Ö0
|
||||
CLK_SWRÌ65536Ö0
|
||||
CONCATÌ131072Í(a,b)Ö0
|
||||
EEPROM_KEY1Ì65536Ö0
|
||||
EEPROM_KEY2Ì65536Ö0
|
||||
EEPROM_START_ADDRÌ65536Ö0
|
||||
EXTI_CR1Ì65536Ö0
|
||||
EXTI_CR2Ì65536Ö0
|
||||
FLASH_CR1Ì65536Ö0
|
||||
FLASH_CR2Ì65536Ö0
|
||||
FLASH_DUKRÌ65536Ö0
|
||||
FLASH_FPRÌ65536Ö0
|
||||
FLASH_IAPSRÌ65536Ö0
|
||||
FLASH_NCR2Ì65536Ö0
|
||||
FLASH_NFPRÌ65536Ö0
|
||||
FLASH_PUKRÌ65536Ö0
|
||||
FORMPORTÌ131072Í(a,b)Ö0
|
||||
GET_ADDRÌ131072Í()Ö0
|
||||
GPIO_PIN0Ì65536Ö0
|
||||
GPIO_PIN1Ì65536Ö0
|
||||
GPIO_PIN2Ì65536Ö0
|
||||
GPIO_PIN3Ì65536Ö0
|
||||
GPIO_PIN4Ì65536Ö0
|
||||
GPIO_PIN5Ì65536Ö0
|
||||
GPIO_PIN6Ì65536Ö0
|
||||
GPIO_PIN7Ì65536Ö0
|
||||
Global_timeÌ32768Ö0Ïvolatile unsigned long
|
||||
I2C_CCRHÌ65536Ö0
|
||||
I2C_CCRLÌ65536Ö0
|
||||
I2C_CR1Ì65536Ö0
|
||||
I2C_CR2Ì65536Ö0
|
||||
I2C_DRÌ65536Ö0
|
||||
I2C_FREQRÌ65536Ö0
|
||||
I2C_ITRÌ65536Ö0
|
||||
I2C_OARHÌ65536Ö0
|
||||
I2C_OARLÌ65536Ö0
|
||||
I2C_PECRÌ65536Ö0
|
||||
I2C_SR1Ì65536Ö0
|
||||
I2C_SR2Ì65536Ö0
|
||||
I2C_SR3Ì65536Ö0
|
||||
I2C_TRISERÌ65536Ö0
|
||||
INTERRUPT_DEFINITIONÌ131072Í(fn,num)Ö0
|
||||
INTERRUPT_HANDLERÌ131072Í(fn,num)Ö0
|
||||
ITC_SPR1Ì65536Ö0
|
||||
ITC_SPR2Ì65536Ö0
|
||||
ITC_SPR3Ì65536Ö0
|
||||
ITC_SPR4Ì65536Ö0
|
||||
ITC_SPR5Ì65536Ö0
|
||||
ITC_SPR6Ì65536Ö0
|
||||
ITC_SPR7Ì65536Ö0
|
||||
ITC_SPR8Ì65536Ö0
|
||||
IWDG_KRÌ65536Ö0
|
||||
IWDG_PRÌ65536Ö0
|
||||
IWDG_RLRÌ65536Ö0
|
||||
KEY_ACCESSÌ65536Ö0
|
||||
KEY_ENABLEÌ65536Ö0
|
||||
KEY_REFRESHÌ65536Ö0
|
||||
LED_NSTATEÌ131072Í()Ö0
|
||||
LED_OFFÌ131072Í()Ö0
|
||||
LED_ONÌ131072Í()Ö0
|
||||
LED_PINÌ65536Ö0
|
||||
LED_PORTÌ65536Ö0
|
||||
M0E1_PINÌ65536Ö0
|
||||
M0E1_PORTÌ65536Ö0
|
||||
M0E2_PINÌ65536Ö0
|
||||
M0E2_PORTÌ65536Ö0
|
||||
M1E1_PINÌ65536Ö0
|
||||
M1E1_PORTÌ65536Ö0
|
||||
M1E2_PINÌ65536Ö0
|
||||
M1E2_PORTÌ65536Ö0
|
||||
MCU_noÌ32768Ö0ÏU8
|
||||
NULLÌ65536Ö0
|
||||
PA_CR1Ì65536Ö0
|
||||
PA_CR2Ì65536Ö0
|
||||
PA_DDRÌ65536Ö0
|
||||
PA_IDRÌ65536Ö0
|
||||
PA_ODRÌ65536Ö0
|
||||
PB_CR1Ì65536Ö0
|
||||
PB_CR2Ì65536Ö0
|
||||
PB_DDRÌ65536Ö0
|
||||
PB_IDRÌ65536Ö0
|
||||
PB_ODRÌ65536Ö0
|
||||
PC_CR1Ì65536Ö0
|
||||
PC_CR2Ì65536Ö0
|
||||
PC_DDRÌ65536Ö0
|
||||
PC_IDRÌ65536Ö0
|
||||
PC_ODRÌ65536Ö0
|
||||
PD_CR1Ì65536Ö0
|
||||
PD_CR2Ì65536Ö0
|
||||
PD_DDRÌ65536Ö0
|
||||
PD_IDRÌ65536Ö0
|
||||
PD_ODRÌ65536Ö0
|
||||
PE_CR1Ì65536Ö0
|
||||
PE_CR2Ì65536Ö0
|
||||
PE_DDRÌ65536Ö0
|
||||
PE_IDRÌ65536Ö0
|
||||
PE_ODRÌ65536Ö0
|
||||
PF_CR1Ì65536Ö0
|
||||
PF_CR2Ì65536Ö0
|
||||
PF_DDRÌ65536Ö0
|
||||
PF_IDRÌ65536Ö0
|
||||
PF_ODRÌ65536Ö0
|
||||
PORTÌ131072Í(a,b)Ö0
|
||||
PWM_PINSÌ65536Ö0
|
||||
RST_SRÌ65536Ö0
|
||||
SPI_CR1Ì65536Ö0
|
||||
SPI_CR1_BRMASKÌ65536Ö0
|
||||
SPI_CR1_CPHAÌ65536Ö0
|
||||
SPI_CR1_CPOLÌ65536Ö0
|
||||
SPI_CR1_LSBFIRSTÌ65536Ö0
|
||||
SPI_CR1_MSTRÌ65536Ö0
|
||||
SPI_CR1_SPEÌ65536Ö0
|
||||
SPI_CR2Ì65536Ö0
|
||||
SPI_CR2_BDMÌ65536Ö0
|
||||
SPI_CR2_BDOEÌ65536Ö0
|
||||
SPI_CR2_CRCENÌ65536Ö0
|
||||
SPI_CR2_CRCNEXTÌ65536Ö0
|
||||
SPI_CR2_RXONLYÌ65536Ö0
|
||||
SPI_CR2_SSIÌ65536Ö0
|
||||
SPI_CR2_SSMÌ65536Ö0
|
||||
SPI_CRCPRÌ65536Ö0
|
||||
SPI_DRÌ65536Ö0
|
||||
SPI_ICRÌ65536Ö0
|
||||
SPI_ICR_ERRIEÌ65536Ö0
|
||||
SPI_ICR_RXIEÌ65536Ö0
|
||||
SPI_ICR_TXIEÌ65536Ö0
|
||||
SPI_ICR_WKIEÌ65536Ö0
|
||||
SPI_RXCRCRÌ65536Ö0
|
||||
SPI_SRÌ65536Ö0
|
||||
SPI_SR_BSYÌ65536Ö0
|
||||
SPI_SR_CRCERRÌ65536Ö0
|
||||
SPI_SR_MODFÌ65536Ö0
|
||||
SPI_SR_OVRÌ65536Ö0
|
||||
SPI_SR_RXNEÌ65536Ö0
|
||||
SPI_SR_TXEÌ65536Ö0
|
||||
SPI_SR_WKUPÌ65536Ö0
|
||||
SPI_TXCRCRÌ65536Ö0
|
||||
STP0_PORTÌ65536Ö0
|
||||
STP1_PORTÌ65536Ö0
|
||||
STP_PINSÌ65536Ö0
|
||||
SWIM_CSRÌ65536Ö0
|
||||
TIM1_ARRHÌ65536Ö0
|
||||
TIM1_ARRLÌ65536Ö0
|
||||
TIM1_BKRÌ65536Ö0
|
||||
TIM1_CCER1Ì65536Ö0
|
||||
TIM1_CCER2Ì65536Ö0
|
||||
TIM1_CCMR1Ì65536Ö0
|
||||
TIM1_CCMR2Ì65536Ö0
|
||||
TIM1_CCMR3Ì65536Ö0
|
||||
TIM1_CCMR4Ì65536Ö0
|
||||
TIM1_CCR1HÌ65536Ö0
|
||||
TIM1_CCR1LÌ65536Ö0
|
||||
TIM1_CCR2HÌ65536Ö0
|
||||
TIM1_CCR2LÌ65536Ö0
|
||||
TIM1_CCR3HÌ65536Ö0
|
||||
TIM1_CCR3LÌ65536Ö0
|
||||
TIM1_CCR4HÌ65536Ö0
|
||||
TIM1_CCR4LÌ65536Ö0
|
||||
TIM1_CNTRHÌ65536Ö0
|
||||
TIM1_CNTRLÌ65536Ö0
|
||||
TIM1_CR1Ì65536Ö0
|
||||
TIM1_CR2Ì65536Ö0
|
||||
TIM1_DTRÌ65536Ö0
|
||||
TIM1_EGRÌ65536Ö0
|
||||
TIM1_ETRÌ65536Ö0
|
||||
TIM1_IERÌ65536Ö0
|
||||
TIM1_OISRÌ65536Ö0
|
||||
TIM1_PSCRHÌ65536Ö0
|
||||
TIM1_PSCRLÌ65536Ö0
|
||||
TIM1_RCRÌ65536Ö0
|
||||
TIM1_SMCRÌ65536Ö0
|
||||
TIM1_SR1Ì65536Ö0
|
||||
TIM1_SR2Ì65536Ö0
|
||||
TIM2_CR1Ì65536Ö0
|
||||
TIM4_CR1Ì65536Ö0
|
||||
TIM_CR1_APREÌ65536Ö0
|
||||
TIM_CR1_CENÌ65536Ö0
|
||||
TIM_CR1_CMSHÌ65536Ö0
|
||||
TIM_CR1_CMSLÌ65536Ö0
|
||||
TIM_CR1_DIRÌ65536Ö0
|
||||
TIM_CR1_OPMÌ65536Ö0
|
||||
TIM_CR1_UDISÌ65536Ö0
|
||||
TIM_CR1_URSÌ65536Ö0
|
||||
TIM_EGR_BGÌ65536Ö0
|
||||
TIM_EGR_CC1GÌ65536Ö0
|
||||
TIM_EGR_CC2GÌ65536Ö0
|
||||
TIM_EGR_CC3GÌ65536Ö0
|
||||
TIM_EGR_CC4GÌ65536Ö0
|
||||
TIM_EGR_COMGÌ65536Ö0
|
||||
TIM_EGR_TGÌ65536Ö0
|
||||
TIM_EGR_UGÌ65536Ö0
|
||||
TIM_IER_BIEÌ65536Ö0
|
||||
TIM_IER_CC1IEÌ65536Ö0
|
||||
TIM_IER_CC2IEÌ65536Ö0
|
||||
TIM_IER_CC3IEÌ65536Ö0
|
||||
TIM_IER_CC4IEÌ65536Ö0
|
||||
TIM_IER_COMIEÌ65536Ö0
|
||||
TIM_IER_TIEÌ65536Ö0
|
||||
TIM_IER_UIEÌ65536Ö0
|
||||
TIM_SR1_BIFÌ65536Ö0
|
||||
TIM_SR1_CC1IFÌ65536Ö0
|
||||
TIM_SR1_CC2IFÌ65536Ö0
|
||||
TIM_SR1_CC3IFÌ65536Ö0
|
||||
TIM_SR1_CC4IFÌ65536Ö0
|
||||
TIM_SR1_COMIFÌ65536Ö0
|
||||
TIM_SR1_TIFÌ65536Ö0
|
||||
TIM_SR1_UIFÌ65536Ö0
|
||||
U16Ì4096Ö0Ïunsigned int
|
||||
U32Ì4096Ö0Ïunsigned long
|
||||
U8Ì4096Ö0Ïunsigned char
|
||||
UART_BUF_LENÌ65536Ö0
|
||||
UART_CR1_MÌ65536Ö0
|
||||
UART_CR1_PCENÌ65536Ö0
|
||||
UART_CR1_PIENÌ65536Ö0
|
||||
UART_CR1_PSÌ65536Ö0
|
||||
UART_CR1_R8Ì65536Ö0
|
||||
UART_CR1_T8Ì65536Ö0
|
||||
UART_CR1_UARTDÌ65536Ö0
|
||||
UART_CR1_WAKEÌ65536Ö0
|
||||
UART_CR2_ILIENÌ65536Ö0
|
||||
UART_CR2_RENÌ65536Ö0
|
||||
UART_CR2_RIENÌ65536Ö0
|
||||
UART_CR2_RWUÌ65536Ö0
|
||||
UART_CR2_SBKÌ65536Ö0
|
||||
UART_CR2_TCIENÌ65536Ö0
|
||||
UART_CR2_TENÌ65536Ö0
|
||||
UART_CR2_TIENÌ65536Ö0
|
||||
UART_CR3_CLKENÌ65536Ö0
|
||||
UART_CR3_CPHAÌ65536Ö0
|
||||
UART_CR3_CPOLÌ65536Ö0
|
||||
UART_CR3_LBCLÌ65536Ö0
|
||||
UART_CR3_LINENÌ65536Ö0
|
||||
UART_CR3_STOP1Ì65536Ö0
|
||||
UART_CR3_STOP2Ì65536Ö0
|
||||
UART_PORTÌ65536Ö0
|
||||
UART_SR_FEÌ65536Ö0
|
||||
UART_SR_IDLEÌ65536Ö0
|
||||
UART_SR_NFÌ65536Ö0
|
||||
UART_SR_ORÌ65536Ö0
|
||||
UART_SR_PEÌ65536Ö0
|
||||
UART_SR_RXNEÌ65536Ö0
|
||||
UART_SR_TCÌ65536Ö0
|
||||
UART_SR_TXEÌ65536Ö0
|
||||
UART_TX_PINÌ65536Ö0
|
||||
UART_rxÌ32768Ö0ÏU8
|
||||
UART_txÌ32768Ö0ÏU8
|
||||
WWDG_CRÌ65536Ö0
|
||||
WWDG_WRÌ65536Ö0
|
||||
_FORTIFY_SOURCEÌ65536Ö0
|
||||
_GNU_SOURCEÌ65536Ö0
|
||||
_LP64Ì65536Ö0
|
||||
_STDC_PREDEF_HÌ65536Ö0
|
||||
__ATOMIC_ACQUIREÌ65536Ö0
|
||||
__ATOMIC_ACQ_RELÌ65536Ö0
|
||||
__ATOMIC_CONSUMEÌ65536Ö0
|
||||
__ATOMIC_HLE_ACQUIREÌ65536Ö0
|
||||
__ATOMIC_HLE_RELEASEÌ65536Ö0
|
||||
__ATOMIC_RELAXEDÌ65536Ö0
|
||||
__ATOMIC_RELEASEÌ65536Ö0
|
||||
__ATOMIC_SEQ_CSTÌ65536Ö0
|
||||
__BIGGEST_ALIGNMENT__Ì65536Ö0
|
||||
__BYTE_ORDER__Ì65536Ö0
|
||||
__CHAR16_TYPE__Ì65536Ö0
|
||||
__CHAR32_TYPE__Ì65536Ö0
|
||||
__CHAR_BIT__Ì65536Ö0
|
||||
__DBL_DECIMAL_DIG__Ì65536Ö0
|
||||
__DBL_DENORM_MIN__Ì65536Ö0
|
||||
__DBL_DIG__Ì65536Ö0
|
||||
__DBL_EPSILON__Ì65536Ö0
|
||||
__DBL_HAS_DENORM__Ì65536Ö0
|
||||
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38
STM8/2stepper4reductor/twosteppers.geany
Normal file
38
STM8/2stepper4reductor/twosteppers.geany
Normal file
@@ -0,0 +1,38 @@
|
||||
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||||
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201
STM8/2stepper4reductor/twosteppers.ihx
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STM8/2stepper4reductor/twosteppers.ihx
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||||
:20949400A6316B0C1E087B0CF72033965C891E1589CD92A05B0420261E047F1E0A89CD82F7
|
||||
:2094B400BF5B02AE00624B0489CD82FC5B03CE963889CD82BF5B02A60120194F20161E01D7
|
||||
:2094D4007F1E0A89CD82BF5B02CE963889CD82BF5B02A6015B1081520DAE00421F0A160A22
|
||||
:2094F4001704AE00021F0C1E0C5C1F011E0CF6A030725D0067274EC10066270EA132270AC1
|
||||
:20951400725F0067725F0068203B16011708160417060F037B03C1006824141E08F61E08CB
|
||||
:209534005C1F081E06F71E065C1F060C0320E5725F0068725F00671E0A89CD93B65B024DDE
|
||||
:209554002603CD92345B0D810A0A00436F6D6D616E642070726F746F636F6C3A205B2061B7
|
||||
:2095740064647220636F6D6D616E64002064617461205D0A092062726F6164636173742061
|
||||
:20959400616464723A20620A00636F6D6D616E64733A0A00302F31202D20636F6D6D616E48
|
||||
:2095B4006420666F7220676976656E206D6F746F723A0A0072202D207265736574204D434C
|
||||
:2095D400550A0047202D2067657420626F61726420616464726573730A004C20302F3120D0
|
||||
:2095F4002D204C4544206F6E2F6F66660A00502063682076616C202D2050574D206F6E20A8
|
||||
:209614006368616E6E656C2063680A0054202D2074696D6520636F756E7465722076616C75
|
||||
:0F96340075650A00963A205D0A005B20582000F9
|
||||
:20980F005B2058200000000000000000000000000000000000000000000000000000000046
|
||||
:209643001E0916072A03CD97D58990891E0916072A03CD97D5899089CD96685B087B032A99
|
||||
:2096630003CD97D58152030F030F017B0A484F494D262E160C1E0A905859170C1F0A1E08B0
|
||||
:20968300130C7B07120B7B06120A240D160C1E0A549056170C1F0A20080C017B016B03202C
|
||||
:2096A300CA7B036B021E0872F00C7B07120B90977B06120A25061F0890951706160C1E0A1D
|
||||
:2096C300549056170C1F0A7B020A024D26D71E0816065B03811E0916072A03CD97D589904A
|
||||
:2096E300891E0916072A03CD97D5899089CD96FF5B087B0318072A03CD97D58152065F1F73
|
||||
:20970300051F03A6206B027B09484F496B01160B1E09905859170B1F0916051E03905859CC
|
||||
:2097230017051F030D0127067B06AA016B061E0572F00F7B04120E90977B03120D250C1FC9
|
||||
:2097430005909517037B0CAA016B0C0A0226B81E0B16095B06815F89897B0A977B0E421F8E
|
||||
:20976300037B09977B0E4272FB021F024FA9006B017B0A977B0D4272FB021F024F19016BBF
|
||||
:20978300017B0A977B0C4272FB011F017B09977B0D4272FB011F017B08977B0E4272FB018C
|
||||
:2097A3001F017B07977B0E429F1B016B017B0A977B0B429F1B016B017B09977B0C429F1BD2
|
||||
:1D97C300016B017B08977B0D429F1B016B019085858190535D2703535C81905C81EF
|
||||
:00000001FF
|
||||
131
STM8/2stepper4reductor/uart.c
Normal file
131
STM8/2stepper4reductor/uart.c
Normal file
@@ -0,0 +1,131 @@
|
||||
/*
|
||||
* geany_encoding=koi8-r
|
||||
* uart.c
|
||||
*
|
||||
* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "uart.h"
|
||||
#include "hardware.h"
|
||||
|
||||
U8 uart_rdy = 0;
|
||||
U8 rx_idx = 0, tx_idx = 0, tx_len = 0;
|
||||
|
||||
U8 UART_rx[UART_BUF_LEN]; // buffers for received/transmitted data
|
||||
U8 UART_tx[UART_BUF_LEN];
|
||||
|
||||
void uart_init(){
|
||||
// PD5 - UART2_TX
|
||||
PORT(UART_PORT, DDR) |= UART_TX_PIN; // output
|
||||
PORT(UART_PORT, CR1) &= ~UART_TX_PIN; // open-drain
|
||||
// 8 bit, no parity, 1 stop (UART_CR1/3 = 0 - reset value)
|
||||
// 9600 on 16MHz: DIV=0x0693 -> BRR1=0x68, BRR2=0x03
|
||||
UART2_BRR1 = 0x68; UART2_BRR2 = 0x03;
|
||||
UART2_CR2 = UART_CR2_TEN | UART_CR2_REN | UART_CR2_RIEN; // Allow TX/RX, generate ints on rx
|
||||
}
|
||||
|
||||
void uart_write(const char *str){
|
||||
while(tx_len) {IWDG_KR = KEY_REFRESH;}
|
||||
do{
|
||||
UART_tx[tx_len++] = *str++;
|
||||
}while(*str && tx_len < UART_BUF_LEN);
|
||||
UART2_CR2 |= UART_CR2_TIEN; // enable TXE interrupt
|
||||
}
|
||||
|
||||
void printUint(const U8 *val, U8 len){
|
||||
unsigned long Number = 0;
|
||||
U8 i = len;
|
||||
char ch;
|
||||
U8 decimal_buff[11]; // max len of U32 == 10 + \0
|
||||
if(len > 4 || len == 3 || len == 0) return;
|
||||
decimal_buff[10] = 0;
|
||||
ch = 9;
|
||||
switch(len){
|
||||
case 1:
|
||||
Number = *((U8*)val);
|
||||
break;
|
||||
case 2:
|
||||
Number = *((U16*)val);
|
||||
break;
|
||||
case 4:
|
||||
Number = *((unsigned long*)val);
|
||||
break;
|
||||
}
|
||||
do{
|
||||
i = Number % 10L;
|
||||
decimal_buff[ch--] = i + '0';
|
||||
Number /= 10L;
|
||||
}while(Number && ch > -1);
|
||||
uart_write((char*)&decimal_buff[ch+1]);
|
||||
}
|
||||
|
||||
/**
|
||||
* fill buffer with symbols of signed long
|
||||
* max len = 10 symbols + 1 for "-" + 1 for 0 = 12
|
||||
*/
|
||||
void long2buf(long Number, char **buf){
|
||||
U8 i, L = 0;
|
||||
U8 ch;
|
||||
char decimal_buff[12];
|
||||
decimal_buff[11] = 0;
|
||||
ch = 11;
|
||||
if(Number < 0){
|
||||
Number = -Number;
|
||||
L = 1;
|
||||
}
|
||||
do{
|
||||
i = Number % 10L;
|
||||
decimal_buff[--ch] = i + '0';
|
||||
Number /= 10L;
|
||||
}while(Number && ch > 0);
|
||||
if(ch > 0 && L) decimal_buff[--ch] = '-';
|
||||
for(i = ch; i < 12; ++i) *((*buf)++) = decimal_buff[i];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* read 16 bit integer value from buffer until first non-number
|
||||
* @param buff (i) - input buffer
|
||||
* @param val (o) - output value
|
||||
* @return 1 if all OK or 0 if there's none numbers in buffer
|
||||
*/
|
||||
U8 readLong(const char *buff, long *val){
|
||||
U8 sign = 0, rb, bad = 1;
|
||||
long R = 0, oR = 0;
|
||||
if(*buff == '-'){
|
||||
sign = 1;
|
||||
++buff;
|
||||
}
|
||||
do{
|
||||
rb = *buff++;
|
||||
if(rb == '+') continue;
|
||||
if(rb < '0' || rb > '9') break;
|
||||
bad = 0;
|
||||
oR = R * 10L + rb - '0';
|
||||
if(oR < R){ // bad value
|
||||
bad = 1;
|
||||
break;
|
||||
}
|
||||
R = oR;
|
||||
}while(1);
|
||||
if(bad) return 0;
|
||||
if(sign) R = -R;
|
||||
*val = R;
|
||||
return 1;
|
||||
}
|
||||
49
STM8/2stepper4reductor/uart.h
Normal file
49
STM8/2stepper4reductor/uart.h
Normal file
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* geany_encoding=koi8-r
|
||||
* uart.h
|
||||
*
|
||||
* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*
|
||||
*/
|
||||
#pragma once
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
#include "hardware.h"
|
||||
|
||||
#define UART_BUF_LEN 32
|
||||
|
||||
extern U8 UART_rx[];
|
||||
extern U8 UART_tx[];
|
||||
extern U8 uart_rdy, rx_idx, tx_idx, tx_len;
|
||||
|
||||
|
||||
void uart_init();
|
||||
|
||||
void uart_write(const char *str);
|
||||
|
||||
char *omit_whitespace(char *str);
|
||||
|
||||
void long2buf(long Number, char **buf);
|
||||
void printUint(const U8 *val, U8 len);
|
||||
U8 readLong(const char *buff, long *val);
|
||||
|
||||
|
||||
#endif // __UART_H__
|
||||
|
||||
|
||||
144
STM8/platform/interrupts.h
Normal file
144
STM8/platform/interrupts.h
Normal file
@@ -0,0 +1,144 @@
|
||||
/*
|
||||
* interrupts.h
|
||||
*
|
||||
* Copyright 2014 Edward V. Emelianoff <eddy@sao.ru>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
#pragma once
|
||||
#ifndef __INTERRUPTS_H__
|
||||
#define __INTERRUPTS_H__
|
||||
|
||||
#include "stm8l.h"
|
||||
|
||||
// Top Level Interrupt
|
||||
INTERRUPT_DEFINITION(TLI_IRQHandler, 0);
|
||||
|
||||
// Auto Wake Up Interrupt
|
||||
INTERRUPT_DEFINITION(AWU_IRQHandler, 1);
|
||||
|
||||
// Clock Controller Interrupt
|
||||
INTERRUPT_DEFINITION(CLK_IRQHandler, 2);
|
||||
|
||||
// External Interrupt PORTA
|
||||
INTERRUPT_DEFINITION(EXTI_PORTA_IRQHandler, 3);
|
||||
|
||||
// External Interrupt PORTB
|
||||
INTERRUPT_DEFINITION(EXTI_PORTB_IRQHandler, 4);
|
||||
|
||||
// External Interrupt PORTC
|
||||
INTERRUPT_DEFINITION(EXTI_PORTC_IRQHandler, 5);
|
||||
|
||||
// External Interrupt PORTD
|
||||
INTERRUPT_DEFINITION(EXTI_PORTD_IRQHandler, 6);
|
||||
|
||||
// External Interrupt PORTE
|
||||
INTERRUPT_DEFINITION(EXTI_PORTE_IRQHandler, 7);
|
||||
|
||||
#ifdef STM8S903
|
||||
// External Interrupt PORTF
|
||||
INTERRUPT_DEFINITION(EXTI_PORTF_IRQHandler, 8);
|
||||
#endif // STM8S903
|
||||
|
||||
#if defined (STM8S208) || defined (STM8AF52Ax)
|
||||
// CAN RX Interrupt routine.
|
||||
INTERRUPT_DEFINITION(CAN_RX_IRQHandler, 8);
|
||||
|
||||
// CAN TX Interrupt routine.
|
||||
INTERRUPT_DEFINITION(CAN_TX_IRQHandler, 9);
|
||||
#endif // STM8S208 || STM8AF52Ax
|
||||
|
||||
// SPI Interrupt routine.
|
||||
INTERRUPT_DEFINITION(SPI_IRQHandler, 10);
|
||||
|
||||
// Timer1 Update/Overflow/Trigger/Break Interrupt
|
||||
INTERRUPT_DEFINITION(TIM1_UPD_OVF_TRG_BRK_IRQHandler, 11);
|
||||
|
||||
// Timer1 Capture/Compare Interrupt routine.
|
||||
INTERRUPT_DEFINITION(TIM1_CAP_COM_IRQHandler, 12);
|
||||
|
||||
#ifdef STM8S903
|
||||
// Timer5 Update/Overflow/Break/Trigger Interrupt
|
||||
INTERRUPT_DEFINITION(TIM5_UPD_OVF_BRK_TRG_IRQHandler, 13);
|
||||
|
||||
// Timer5 Capture/Compare Interrupt
|
||||
INTERRUPT_DEFINITION(TIM5_CAP_COM_IRQHandler, 14);
|
||||
|
||||
#else // STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF62Ax or STM8AF52Ax or STM8AF626x
|
||||
// Timer2 Update/Overflow/Break Interrupt
|
||||
INTERRUPT_DEFINITION(TIM2_UPD_OVF_BRK_IRQHandler, 13);
|
||||
|
||||
// Timer2 Capture/Compare Interrupt
|
||||
INTERRUPT_DEFINITION(TIM2_CAP_COM_IRQHandler, 14);
|
||||
#endif // STM8S903
|
||||
|
||||
#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
|
||||
defined(STM8S005) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8AF626x)
|
||||
// Timer3 Update/Overflow/Break Interrupt
|
||||
INTERRUPT_DEFINITION(TIM3_UPD_OVF_BRK_IRQHandler, 15);
|
||||
|
||||
// Timer3 Capture/Compare Interrupt
|
||||
INTERRUPT_DEFINITION(TIM3_CAP_COM_IRQHandler, 16);
|
||||
#endif // STM8S208, STM8S207 or STM8S105 or STM8AF62Ax or STM8AF52Ax or STM8AF626x
|
||||
|
||||
#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S103) || \
|
||||
defined(STM8S003) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8S903)
|
||||
// UART1 TX Interrupt
|
||||
INTERRUPT_DEFINITION(UART1_TX_IRQHandler, 17);
|
||||
|
||||
// UART1 RX Interrupt
|
||||
INTERRUPT_DEFINITION(UART1_RX_IRQHandler, 18);
|
||||
#endif // STM8S208 or STM8S207 or STM8S103 or STM8S903 or STM8AF62Ax or STM8AF52Ax
|
||||
|
||||
// I2C Interrupt
|
||||
INTERRUPT_DEFINITION(I2C_IRQHandler, 19);
|
||||
|
||||
#if defined(STM8S105) || defined(STM8S005) || defined (STM8AF626x)
|
||||
// UART2 TX interrupt
|
||||
INTERRUPT_DEFINITION(UART2_TX_IRQHandler, 20);
|
||||
|
||||
// UART2 RX interrupt
|
||||
INTERRUPT_DEFINITION(UART2_RX_IRQHandler, 21);
|
||||
#endif // STM8S105 or STM8AF626x
|
||||
|
||||
#if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
|
||||
// UART3 TX interrupt
|
||||
INTERRUPT_DEFINITION(UART3_TX_IRQHandler, 20);
|
||||
|
||||
// UART3 RX interrupt
|
||||
INTERRUPT_DEFINITION(UART3_RX_IRQHandler, 21);
|
||||
#endif // STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax
|
||||
|
||||
#if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
|
||||
// ADC2 interrupt
|
||||
INTERRUPT_DEFINITION(ADC2_IRQHandler, 22);
|
||||
#else // STM8S105, STM8S103 or STM8S903 or STM8AF626x
|
||||
// ADC1 interrupt
|
||||
INTERRUPT_DEFINITION(ADC1_IRQHandler, 22);
|
||||
#endif // STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax
|
||||
|
||||
#ifdef STM8S903
|
||||
// Timer6 Update/Overflow/Trigger Interrupt
|
||||
INTERRUPT_DEFINITION(TIM6_UPD_OVF_TRG_IRQHandler, 23);
|
||||
#else // STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF52Ax or STM8AF62Ax or STM8AF626x
|
||||
// Timer4 Update/Overflow Interrupt
|
||||
INTERRUPT_DEFINITION(TIM4_UPD_OVF_IRQHandler, 23);
|
||||
#endif // STM8S903
|
||||
|
||||
// Eeprom EEC Interrupt
|
||||
INTERRUPT_DEFINITION(EEPROM_EEC_IRQHandler, 24);
|
||||
|
||||
#endif // __INTERRUPTS_H__
|
||||
113
STM8/platform/sco_platform.ihx
Normal file
113
STM8/platform/sco_platform.ihx
Normal file
@@ -0,0 +1,113 @@
|
||||
:2080A000AE5007F6AA0FF7AE5008F6AA0FF7AE5009F6AA0FF7AE5011F6AA1FF7AE5012F6F1
|
||||
:2080C000AA1FF7AE5013F6AA1FF7AE5005F6A4F0F7AE500FF6A4F8F7AE500FF6AA18F781C2
|
||||
:2080E0005204965C891E0989CD868E5B044D27441E01A3FFF72D3D1E01A37FFF2E3616012A
|
||||
:2081000072A9000AAEFFFF65A3007D24034F2025CF00643504530C9E0F0390AE530D90F7AE
|
||||
:208120004F9FAE530EF735015301AE5300F6AA84F7A601214F5B048188AE5001F66B017B4A
|
||||
:2081400001954F417B0141889E1102842704029E014F4CA1FF25F09EA5022604A601200924
|
||||
:208160009EA5042603A602214F5B018152040D07270F7B07A10622091E082705CE006127FE
|
||||
:20818000044FCC825590AE004C5F7B0797581F0172F90190FE35AA50E00D082A0B350100E6
|
||||
:2081A000631E08501F082004725F00637B09C700627B08C70061AE005A9F1B0702A9009506
|
||||
:2081C000F69095AE500AF6A41F6B03909E4EA4F0481A03AE500AF7AE5005F6A4F0F7AE505F
|
||||
:2081E0000FF6A4F8F7AE500FF6AA18F7AE500FF695909F4488A6016B05844D270508044A2E
|
||||
:2082000026FB9E1A04AE500FF7AE500FF690542408A4EFAE500FF72006A4F7AE500FF7CD41
|
||||
:208220008138027B0701889EC70066844D2714A1012609725D0063260A4F2007725D0063C6
|
||||
:2082400027014F4D2706CD82584F2009AE5300F6AA01F7A6015B048172115300AE5005F61F
|
||||
:20826000A4F0F7AE500FF6A4F8F7AE500FF6AA18F7725F00675FCF006135010043815214FA
|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
:0A8CC300535D2703535C81905C8130
|
||||
:00000001FF
|
||||
Reference in New Issue
Block a user