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https://github.com/eddyem/STM8_samples.git
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365 lines
11 KiB
C
365 lines
11 KiB
C
/*
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* i2c.c - functions to work with HW I2C
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*
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* Copyright 2015 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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/*
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* I2C_FREQR - peripherial input clock (>=1MHz - standard, >=4MHz - fast)
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* + clock control & rise time
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* I2C_CR1 - enable
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* I2C_CR2 - start bit (generate + set SB bit + interrupt if ITEVTEN==1)
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* writing can be in 7 & 10 bit modes
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*
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* ** 7bit transmit**
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* 1) start; 2) read SR1 & write address to DR; 3) check ADDR, if ACK received
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* it would be 1 - clear it by read SR1 & SR3, wait for TXE==1 & BTF==1 (ready for transmit)
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* and send data writing to DR; to send EOT set STOP=1
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*
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* ** 10bit transmit**
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* 1) start; 2) read SR1 & write 11110xx0 (xx - MS bits of address) to DR;
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* 3) ADD10=1, clear it by reading SR1 & write last 8 bits of address to DR;
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* 4) similar to 3) for 7bits
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*
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* ** receive **
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* 1) clear ADDR after sending address
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* 2) set ACK if need to generate ACK bit
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* 3) check RXNE or get data by interrupt (if ITEVTEN==1 & ITBUFEN==1)
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* in case of byte transfer finished, BTF=1 (to clear it, read SR1 & DR)
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* in 10bit receive mode send start & 11110xx1 after sending address
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* in 7bit receive mode send address with LSB set
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*
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* TRA bit indicates I2C mode
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*
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* ** close **
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* Method 1 (higher interrupts):
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* 1) reset ACK=0 to generate NACK; 2) to generate Stop/Restart set STOP/START
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* all this should be done at second last byte reading (to get a single byte
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* do this just after ADDR sent); 3) read last byte
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*
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* Method 2 (low interrupt priority or polling, valid only for N>2):
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* 1) not read DR & wait for RXNE==1&&BTF==1
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* 2) clear ACK
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* 3) read DR (DATA_N-2) & set STOP/START
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* 4) read DR (DATA_N-1), read DR (DATA_N)
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*
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* to read 1 byte use Method 1;
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* to read 2 bytes with Method2, set POS&ACK, wait ADDR, clear ADDR&ACK,
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* wait BTF, set STOP, read DR twice
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*
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*
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* *** REGISTERS ***
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* I2C_CR1: | NOSTRETCH | ENGC | reserved[5:1] | PE |
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* NOSTRETCH - ==1 to slave mode
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* ENGC - generall call EN/DIS
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* PE - ==1 to enable I2C
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*
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* I2C_CR2: | SWRST | res[6:4] | POS | ACK | STOP | START |
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* SWRST - ==1 to software reset
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* POS - ACK position (==0 for current byte, ==1 for next byte)
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* ACK - send ACK after reading byte
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* STOP - send STOP after reading byte
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* START - send repeated START
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* DO NOT make any changes with I2C_CR2 when sending START/STOP
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* before they'll be cleared by hardware!
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*
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* I2C_FREQR: | res[7:6] | FREQ[5:0] |
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* FREQ - I2C clock frequency (in MHz, from 1 to 24)
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*
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* I2C_OARL: | ADD[7:1] | ADD0 | - LSB of address
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* ADD0 - 0th bit of address in 10bit mode, don't care in 7bit mode
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*
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* I2C_OARH: | ADDMODE | ADDCONF | res[5:3] | ADD[9:8] | res |
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* ADDMODE - 0 for 7bit, 1 for 10bit address
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* ADDCONF - must always be written as 1 ("address is set")
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*
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* I2C_DR - data I/O register
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*
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* I2C_SR1: | TXE | RXNE | res | STOPF | ADD10 | BTF | ADDR | SB |
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* TXE - set when DR is empty for transmission
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* RXNE - set when DR not empty in receiver mode
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* STOPF - stop detected (slave mode)
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* ADD10 - 10 bit header sent (first byte)
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* BTF - byte transfer finished (set when NOSTRETCH==0)
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* ADDR - address sent (not set if NACK)
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* SB - start condition
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*
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* I2C_SR2: | res[7:6] | WUFH | res | OVR | AF | ARLO | BERR |
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* WUFH - wakeup from halt
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* OVR - overrun/underrun
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* AF - acknowledge failure (must be cleared by software)
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* ARLO - arbitration lost (another master on line, clear it by SW)
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* BERR - bus error (clear by SW)
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*
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* I2C_SR3: | res[7:5] | GENCALL | res | TRA | BUSY | MSL |
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* GENCALL - general call in slave mode
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* TRA - transmitter(1)/receiver(0) flag
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* BUSY - bus busy (another communication detected)
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* MSL - slave(0)/master(1) mode, set/cleared by HW
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*
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* I2C_ITR: | res[7:3] | ITBUFEN | ITEVTEN | ITERREN |
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* ITBUFEN - enable buffer interrupt
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* ITEVTEN - enable event interrupt
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* ITERREN - enable error interrupt
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*
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* I2C_CCRL: | CCR[7:0] |
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* SCLH clock in master mode
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* standard: T = 2*CCR*tmaster, Tlow = Thigh = CCR*tmaster
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* fast: (DUTY==0) T = 3*CCR*tmaster, Thigh = CCR*tmaster, Tlow = 2*Thigh
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* (DUTY==1) T = 25*CCR*tmaster, Thigh=9*CCR*tmaster, Tlow=16*CCR*tmaster
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* fmaster - clock by I2C_FREQR
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* minimum allowed value is 4 (exept FAST DUTY, when it is 1)
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*
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* I2C_CCRH: | F/S | DUTY | res[5:4] | CCR[11:8] |
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* F/S - == 1 in fast mode
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* DUTY - (see upper)
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* IN standard mode 100kHz is: FREQR=8, CCR=0x28
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*
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* I2C_TRISER: | res[7:6] | TRISE[5:0] |
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* TRISE - maximum rise time (0x09 for standard @100kHz)
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*
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*/
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#include "i2c.h"
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#include "ports_definition.h"
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static U8 addr7r = 0, addr7w = 0;
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extern volatile unsigned long Global_time;
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static U16 _c;
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#define I2C_WAIT(evt, tmo) do{ \
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for(_c = 1000U*tmo; _c && !(evt); _c--); \
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if(!_c){ret = I2C_TMOUT; goto eotr;}}while(0)
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static U8 _d;
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#define I2C_LINEWAIT() do{ for(_d = 0; _d < 16; _d++){\
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for(_c = 0; (_c < 60000) && (I2C_SR3 & 2); _c++); \
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if(!(I2C_SR3 & 2)) break; I2C_CR2 |= 2;} \
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if(_d == 16) return I2C_LINEBUSY; }while(0)
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/**
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* configure 100kHz speed in standard mode & enable i2c
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*/
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void i2c_setup(){
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// configure pins: PB5 - I2C_SDA; PB4 - I2C_SCL (both opendrain)
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PORT(PB, ODR) |= GPIO_PIN4|GPIO_PIN5; // set to 1
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PORT(PB, DDR) |= GPIO_PIN4|GPIO_PIN5;
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PORT(PB, CR2) |= GPIO_PIN4|GPIO_PIN5; // fast mode
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// Don't forget to connect pullup resistor to I2C foots
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I2C_FREQR = 8; // 8MHz fmaster
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I2C_TRISER = 9; // rise time 1000ns
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I2C_CCRL = 80; // 100kHz
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I2C_CCRH = 0;
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I2C_ITR = 0; // disable all I2C interrupts
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I2C_CR2 |= 4; // ACK
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I2C_CR1 |= 1; // enable I2C
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}
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void i2c_set_addr7(U8 addr){
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addr7w = addr << 1;
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addr7r = addr7w | 1;
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}
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/**
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* send one byte in 7bit address mode
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* @param data - data to write
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* @param stop - ==1 to send stop event
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* @return I2C_OK if success errcode if fails
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*/
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i2c_status i2c_7bit_send_onebyte(U8 data, U8 stop){
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i2c_status ret = I2C_LINEBUSY;
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I2C_LINEWAIT();
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I2C_CR2 |= 1; // send START
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I2C_WAIT((I2C_SR1 & 1), 2); // wait for SB
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I2C_DR = addr7w;
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ret = I2C_NOADDR;
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I2C_WAIT(((I2C_SR1 & 2) || I2C_SR2), 2); // wait for ADDR
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if(I2C_SR2){ // NACK or other error
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ret = I2C_NACK;
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goto eotr;
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}
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ret = I2C_HWPROBLEM;
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// clear ADDR reading SR3
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if(!(I2C_SR3 & 4)) goto eotr; // interface is in receiver mode
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I2C_WAIT((I2C_SR1 & 0x80), 2); // wait for TXE
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I2C_DR = data; // send data
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I2C_WAIT(((0x84 == (I2C_SR1 & 0x84)) || I2C_SR2), 15); // wait for TXE & BTF
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if(!I2C_SR2) ret = I2C_OK;
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else ret = I2C_NACK;
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eotr:
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I2C_SR2 = 0; // clear all error flagss
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if(stop){
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I2C_CR2 |= 2; // set STOP
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while(I2C_CR2 & 2); // wait for STOP sent
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}
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return ret;
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}
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/**
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* send datalen bytes over I2C
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* @param data - data to write
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* @param datalen - amount of bytes in data array
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* @param stop - ==1 to send stop event
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* return I2C_OK if OK
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*/
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i2c_status i2c_7bit_send(U8 *data, U8 datalen, U8 stop){
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i2c_status ret = I2C_LINEBUSY;
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I2C_LINEWAIT();
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I2C_CR2 |= 1; // send START
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ret = I2C_TMOUT;
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I2C_WAIT((I2C_SR1 & 1), 2); // wait for SB
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I2C_DR = addr7w;
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ret = I2C_NOADDR;
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I2C_WAIT(((I2C_SR1 & 2) || I2C_SR2), 2); // wait for ADDR
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if(I2C_SR2){ // NACK or other error
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ret = I2C_NACK;
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goto eotr;
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}
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ret = I2C_HWPROBLEM;
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if(!(I2C_SR3 & 4)) goto eotr; // interface is in receiver mode
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while(datalen--){
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I2C_WAIT(((I2C_SR1 & 0x80) || I2C_SR2), 2); // wait for TXE
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if(I2C_SR2){
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ret = I2C_NACK;
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goto eotr;
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}
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I2C_DR = *data++; // send data
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}
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I2C_WAIT(((0x84 == (I2C_SR1 & 0x84)) || I2C_SR2), 15); // wait for TXE & BTF
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if(!I2C_SR2) ret = I2C_OK;
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else ret = I2C_NACK;
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eotr:
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I2C_SR2 = 0; // clear all error flags
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if(stop){
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I2C_CR2 |= 2; // set STOP
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while(I2C_CR2 & 2); // wait for STOP sent
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}
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return ret;
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}
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/**
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* get one byte by I2C
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* @param data - data to read (one byte)
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* @param wait - ==1 to wait while LINEBUSY (can send STOP before reading)
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* @return I2C_OK if ok || error code
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*/
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i2c_status i2c_7bit_receive_onebyte(U8 *data, U8 wait){
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i2c_status ret = I2C_LINEBUSY;
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if(wait)
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I2C_LINEWAIT();
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I2C_CR2 |= 5; // send START & set ACK
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ret = I2C_TMOUT;
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I2C_WAIT((I2C_SR1 & 1), 2); // wait for SB
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I2C_DR = addr7r; // send address & read bit
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ret = I2C_NOADDR;
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I2C_WAIT(((I2C_SR1 & 2) || I2C_SR2), 2); // wait for ADDR
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if(I2C_SR2){ // NACK or other error
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ret = I2C_NACK;
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goto eotr;
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}
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disableInterrupts();
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// clear POS|ACK
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I2C_CR2 &= ~0x0c;
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ret = I2C_HWPROBLEM;
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// read SR3 to clear ADDR
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if((I2C_SR3 & 4)){
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enableInterrupts();
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goto eotr; // interface is in transmitter mode
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}
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// set STOP
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I2C_CR2 |= 2;
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enableInterrupts();
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// wait for RxNE
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I2C_WAIT(((I2C_SR1 & 0x40) || I2C_SR2), 2);
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if(I2C_SR2){
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ret = I2C_NACK;
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goto eotr; // error
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}
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ret = I2C_OK;
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// read data clearing RxNE
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*data = I2C_DR;
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eotr:
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I2C_SR2 = 0; // clear all error flags
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if(!I2C_CR2 & 2) I2C_CR2 |= 2;
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while(I2C_CR2 & 2); // wait for STOP sent
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return ret;
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}
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/**
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* receive 2 bytes by I2C
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* @param data - data to read (two bytes array, 0 first)
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* @param wait - ==1 to wait while LINEBUSY (can send STOP before reading)
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* @return I2C_OK if ok || error code
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*/
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i2c_status i2c_7bit_receive_twobyte(U8 *data, U8 wait){
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i2c_status ret = I2C_LINEBUSY;
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if(wait)
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I2C_LINEWAIT();
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I2C_CR2 |= 5; // send START & set ACK
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ret = I2C_TMOUT;
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I2C_WAIT((I2C_SR1 & 1), 2); // wait for SB
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I2C_DR = addr7r; // send address & read bit
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// set POS|ACK
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I2C_CR2 |= 0x0c;
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ret = I2C_NOADDR;
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I2C_WAIT(((I2C_SR1 & 2) || I2C_SR2), 2); // wait for ADDR
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if(I2C_SR2){ // NACK or other error
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ret = I2C_NACK;
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goto eotr;
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}
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disableInterrupts();
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ret = I2C_HWPROBLEM;
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// read SR3 to clear ADDR
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if(I2C_SR3 & 4){
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enableInterrupts();
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goto eotr; // interface is in transmitter mode
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}
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// clear ACK
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I2C_CR2 &= ~4;
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enableInterrupts();
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// wait for BTF
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I2C_WAIT(((I2C_SR1 & 4) || I2C_SR2), 15);
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if(I2C_SR2){
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ret = I2C_NACK;
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goto eotr;
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}
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// patch from ERRATA
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disableInterrupts();
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// set STOP
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I2C_CR2 |= 2;
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ret = I2C_OK;
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// read data
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data[0] = I2C_DR;
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enableInterrupts();
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data[1] = I2C_DR;
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eotr:
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I2C_SR2 = 0; // clear all error flags
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if(!I2C_CR2 & 2) I2C_CR2 |= 2;
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while(I2C_CR2 & 2); // wait for STOP sent
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// clear POS
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I2C_CR2 &= ~8;
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return ret;
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}
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INTERRUPT_HANDLER(I2C_IRQHandler, 19){
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}
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