mirror of
https://github.com/eddyem/tsys01.git
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222 lines
7.1 KiB
C
222 lines
7.1 KiB
C
/*
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* stm32f1.h
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*
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* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#pragma once
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#ifndef __STM32F1_H__
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#define __STM32F1_H__
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#include "vector.h"
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#include "stm32f10x.h"
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#include "common_macros.h"
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/************************* RCC *************************/
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// reset clocking registers
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TRUE_INLINE void sysreset(void){
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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#ifndef STM32F10X_CL
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RCC->CFGR &= (uint32_t)0xF8FF0000;
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#else
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RCC->CFGR &= (uint32_t)0xF0FF0000;
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#endif /* STM32F10X_CL */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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#ifdef STM32F10X_CL
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/* Reset PLL2ON and PLL3ON bits */
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RCC->CR &= (uint32_t)0xEBFFFFFF;
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x00FF0000;
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/* Reset CFGR2 register */
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RCC->CFGR2 = 0x00000000;
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#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000;
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/* Reset CFGR2 register */
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RCC->CFGR2 = 0x00000000;
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#else
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000;
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#endif /* STM32F10X_CL */
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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TRUE_INLINE void StartHSE()
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{
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__IO uint32_t StartUpCounter = 0;
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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/* Enable HSE */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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++StartUpCounter;
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} while(!(RCC->CR & RCC_CR_HSERDY) && (StartUpCounter < 10000));
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if (RCC->CR & RCC_CR_HSERDY) // HSE started
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{
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/* Enable Prefetch Buffer */
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FLASH->ACR |= FLASH_ACR_PRFTBE;
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/* Flash 2 wait state */
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FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
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#ifdef STM32F10X_CL
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/* Configure PLLs ------------------------------------------------------*/
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/* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
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/* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
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RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
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RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
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RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
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RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
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/* Enable PLL2 */
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RCC->CR |= RCC_CR_PLL2ON;
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/* Wait till PLL2 is ready */
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StartUpCounter = 0;
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while((RCC->CR & RCC_CR_PLL2RDY) == 0 && ++StartUpCounter < 1000){}
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/* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
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RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
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RCC_CFGR_PLLMULL9);
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#else
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/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
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RCC_CFGR_PLLMULL));
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
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#endif /* STM32F10X_CL */
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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StartUpCounter = 0;
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while((RCC->CR & RCC_CR_PLLRDY) == 0 && ++StartUpCounter < 1000){}
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/* Select PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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StartUpCounter = 0;
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while(((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) && ++StartUpCounter < 1000){}
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}
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else // HSE fails to start-up
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{
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; // add some code here (use HSI)
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}
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}
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/************************* GPIO *************************/
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/**
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CNF1: 0 - general output or input; 1 - alternate output or pullup/down input
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CNF0: 0 - push/pull, analog or pullup/down input
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MODE: 00 - input, 01 - 10MHz, 10 - 2MHz, 11 - 50MHz
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Pullup/down: ODR = 0 - pulldown, 1 - pullup
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GPIO_BSRR and BRR also works
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IDR - input, ODR - output (or pullups management),
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*/
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// MODE:
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#define MODE_INPUT 0
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#define MODE_NORMAL 1 // 10MHz
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#define MODE_SLOW 2 // 2MHz
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#define MODE_FAST 3 // 50MHz
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// CNF:
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#define CNF_ANALOG (0 << 2)
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#define CNF_PPOUTPUT (0 << 2)
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#define CNF_FLINPUT (1 << 2)
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#define CNF_ODOUTPUT (1 << 2)
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#define CNF_PUDINPUT (2 << 2)
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#define CNF_AFPP (2 << 2)
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#define CNF_AFOD (3 << 2)
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#define CRL(pin, cnfmode) ((cnfmode) << (pin*4))
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#define CRH(pin, cnfmode) ((cnfmode) << ((pin-8)*4))
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/************************* ADC *************************/
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/* inner termometer calibration values
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* Temp = (V25 - Vsense)/Avg_Slope + 25
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*/
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#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
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/************************* IWDG *************************/
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#define IWDG_REFRESH (uint32_t)(0x0000AAAA)
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#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
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#define IWDG_START (uint32_t)(0x0000CCCC)
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// flash size
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#define FLASH_SIZE_REG ((uint32_t)0x1FFFF7E0)
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#if 0
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/************************* ADC *************************/
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/* inner termometer calibration values
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* Temp = (V30 - Vsense)/Avg_Slope + 30
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* Avg_Slope = (V30 - V110) / (110 - 30)
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*/
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#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
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#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
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// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
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#define VDD_CALIB ((uint16_t) (330))
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#define VDD_APPLI ((uint16_t) (300))
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/************************* USART *************************/
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#define USART_CR2_ADD_SHIFT 24
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// set address/character match value
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#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
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//#define do{}while(0)
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#endif
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#endif // __STM32F1_H__
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