diff --git a/STM32/TSYS_controller/2DO b/STM32/TSYS_controller/2DO new file mode 100644 index 0000000..b215f7f --- /dev/null +++ b/STM32/TSYS_controller/2DO @@ -0,0 +1,5 @@ +- CAN bus: PB8 (Rx), PB9 (Tx) +- USB bus: PA11 (DM), PA12 (DP) +- ADC inputs: PA0 (V12/4.93), PA1 (V5/2), PA3 (I12 - 1V/A), PA6 (V3.3/2) +- controller CAN address: PA13..PA15 (0..2 bits); 0 - master, other address - slave + diff --git a/STM32/TSYS_controller/Makefile b/STM32/TSYS_controller/Makefile new file mode 100644 index 0000000..e2dc292 --- /dev/null +++ b/STM32/TSYS_controller/Makefile @@ -0,0 +1,145 @@ +BINARY = tsys01 +BOOTPORT ?= /dev/ttyUSB0 +BOOTSPEED ?= 9600 +# MCU FAMILY +FAMILY = F0 +# MCU code +MCU = F042x6 +# hardware definitions +DEFS := -DUSARTNUM=1 -DI2CPINS=B6B7 +#DEFS += -DCHECK_TMOUT +#DEFS += -DEBUG +# change this linking script depending on particular MCU model, +# for example, if you have STM32F103VBT6, you should write: +LDSCRIPT = ld/stm32f042k.ld + +INDEPENDENT_HEADERS= + +FP_FLAGS ?= -msoft-float +ASM_FLAGS = -mthumb -mcpu=cortex-m0 -march=armv6-m -mtune=cortex-m0 +ARCH_FLAGS = $(ASM_FLAGS) $(FP_FLAGS) + +############################################################################### +# Executables +OPREFIX ?= /opt/bin/arm-none-eabi +#PREFIX ?= /usr/x86_64-pc-linux-gnu/arm-none-eabi/gcc-bin/7.3.0/arm-none-eabi +PREFIX ?= $(OPREFIX) + +RM := rm -f +RMDIR := rmdir +CC := $(PREFIX)-gcc +LD := $(PREFIX)-gcc +AR := $(PREFIX)-ar +AS := $(PREFIX)-as +OBJCOPY := $(OPREFIX)-objcopy +OBJDUMP := $(OPREFIX)-objdump +GDB := $(OPREFIX)-gdb +STFLASH := $(shell which st-flash) +STBOOT := $(shell which stm32flash) + +############################################################################### +# Source files +OBJDIR = mk +LDSCRIPT ?= $(BINARY).ld +SRC := $(wildcard *.c) +OBJS := $(addprefix $(OBJDIR)/, $(SRC:%.c=%.o)) +STARTUP = $(OBJDIR)/startup.o +OBJS += $(STARTUP) +DEPS := $(OBJS:.o=.d) + +INC_DIR ?= ../inc + +INCLUDE := -I$(INC_DIR)/F0 -I$(INC_DIR)/cm +LIB_DIR := $(INC_DIR)/ld + +############################################################################### +# C flags +CFLAGS += -O2 -g -MD -D__thumb2__=1 +CFLAGS += -Wall -Wextra -Wshadow -Wimplicit-function-declaration +CFLAGS += -Wredundant-decls $(INCLUDE) +# -Wmissing-prototypes -Wstrict-prototypes +CFLAGS += -fno-common -ffunction-sections -fdata-sections + +############################################################################### +# Linker flags +LDFLAGS += --static -nostartfiles +#--specs=nano.specs +LDFLAGS += -L$(LIB_DIR) +LDFLAGS += -T$(LDSCRIPT) +LDFLAGS += -Wl,-Map=$(OBJDIR)/$(BINARY).map +LDFLAGS += -Wl,--gc-sections + +############################################################################### +# Used libraries +LDLIBS += -Wl,--start-group -lc -lgcc -Wl,--end-group +LDLIBS += $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) + +DEFS += -DSTM32$(FAMILY) -DSTM32$(MCU) + +#.SUFFIXES: .elf .bin .hex .srec .list .map .images +#.SECONDEXPANSION: +#.SECONDARY: + +ELF := $(OBJDIR)/$(BINARY).elf +LIST := $(OBJDIR)/$(BINARY).list +BIN := $(BINARY).bin +HEX := $(BINARY).hex + +all: bin list + +elf: $(ELF) +bin: $(BIN) +hex: $(HEX) +list: $(LIST) + +ifneq ($(MAKECMDGOALS),clean) +-include $(DEPS) +endif + +$(OBJDIR): + mkdir $(OBJDIR) + +$(STARTUP): $(INC_DIR)/startup/vector.c + $(CC) $(CFLAGS) $(DEFS) $(INCLUDE) $(ARCH_FLAGS) -o $@ -c $< + +$(OBJDIR)/%.o: %.c + @echo " CC $<" + $(CC) $(CFLAGS) $(DEFS) $(INCLUDE) $(ARCH_FLAGS) -o $@ -c $< + +#$(OBJDIR)/%.d: %.c $(OBJDIR) +# $(CC) -MM -MG $< | sed -e 's,^\([^:]*\)\.o[ ]*:,$(@D)/\1.o $(@D)/\1.d:,' >$@ + +$(BIN): $(ELF) + @echo " OBJCOPY $(BIN)" + $(OBJCOPY) -Obinary $(ELF) $(BIN) + +$(HEX): $(ELF) + @echo " OBJCOPY $(HEX)" + $(OBJCOPY) -Oihex $(ELF) $(HEX) + +$(LIST): $(ELF) + @echo " OBJDUMP $(LIST)" + $(OBJDUMP) -S $(ELF) > $(LIST) + +$(ELF): $(OBJDIR) $(OBJS) + @echo " LD $(ELF)" + $(LD) $(LDFLAGS) $(ARCH_FLAGS) $(OBJS) $(LDLIBS) -o $(ELF) + +clean: + @echo " CLEAN" + $(RM) $(OBJS) $(DEPS) $(ELF) $(HEX) $(LIST) $(OBJDIR)/*.map + @rmdir $(OBJDIR) 2>/dev/null || true + + +flash: $(BIN) + @echo " FLASH $(BIN)" + $(STFLASH) write $(BIN) 0x8000000 + +boot: $(BIN) + @echo " LOAD $(BIN) through bootloader" + $(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN) + +gentags: + CFLAGS="$(CFLAGS) $(DEFS)" geany -g $(BINARY).c.tags *[hc] 2>/dev/null + +.PHONY: clean flash boot gentags diff --git a/STM32/TSYS_controller/Readme.md b/STM32/TSYS_controller/Readme.md new file mode 100644 index 0000000..83cf7db --- /dev/null +++ b/STM32/TSYS_controller/Readme.md @@ -0,0 +1,24 @@ +# Firmware for controllers of thermal sensors + +Make regular scan of 8 sensors' pairs. +USART speed 115200. Code for ../../kicad/stm32 + +### Serial interface commands (ends with '\n'): +- **C** show coefficients for all thermosensors +- **D** detect seosors (reseting them) +- **H** switch I2C to high speed (100kHz) +- **L** switch I2C to low speed (default, 10kHz) +- **R** reset both sensors +- **T** get temperature in degrC + +### PINOUT +- I2C: PB6 (SCL) & PB7 (SDA) +- USART1: PA9 (Tx) & PA10 (Rx) +- CAN bus: PB8 (Rx), PB9 (Tx) +- USB bus: PA11 (DM), PA12 (DP) +- I2C multiplexer: PB0..PB2 (0..2 address bits), PB12 (~EN) +- sensors' power: PB3 (in, overcurrent), PA8 (out, enable power) +- signal LEDs: PB10 (LED0), PB11 (LED1) +- ADC inputs: PA0 (V12/4.93), PA1 (V5/2), PA3 (I12 - 1V/A), PA6 (V3.3/2) +- controller CAN address: PA13..PA15 (0..2 bits); 0 - master, other address - slave + diff --git a/STM32/TSYS_controller/hardware.c b/STM32/TSYS_controller/hardware.c new file mode 100644 index 0000000..1701e45 --- /dev/null +++ b/STM32/TSYS_controller/hardware.c @@ -0,0 +1,89 @@ +/* + * geany_encoding=koi8-r + * hardware.c - hardware-dependent macros & functions + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ + +#include "hardware.h" + +I2C_SPEED curI2Cspeed = LOW_SPEED; + + +void gpio_setup(void){ + // here we turn on clocking for all periph. + RCC->AHBENR |= RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_DMAEN; + // Set LEDS (PB10/11) & multiplexer as output (PB0..2,12) + GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER10 | GPIO_MODER_MODER11 | + GPIO_MODER_MODER0 | GPIO_MODER_MODER1 | + GPIO_MODER_MODER2 | GPIO_MODER_MODER12 ) + ) | + GPIO_MODER_MODER10_O | GPIO_MODER_MODER11_O | + GPIO_MODER_MODER0_O | GPIO_MODER_MODER1_O | + GPIO_MODER_MODER2_O | GPIO_MODER_MODER12_O; + // multiplexer outputs are push-pull: + GPIOB->OTYPER |= GPIO_OTYPER_OT_0 | GPIO_OTYPER_OT_1 | GPIO_OTYPER_OT_2 | + GPIO_OTYPER_OT_12; + MUL_OFF(); + // PA8 - power enable + GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER8)) | + GPIO_MODER_MODER8_O; +} + +void i2c_setup(I2C_SPEED speed){ + if(speed == CURRENT_SPEED){ + speed = curI2Cspeed; + }else{ + curI2Cspeed = speed; + } + I2C1->CR1 = 0; +#if I2CPINS == A9A10 +/* + * GPIO Resources: I2C1_SCL - PA9, I2C1_SDA - PA10 + * GPIOA->AFR[1] + */ + GPIOA->AFR[1] &= ~0xff0; // alternate function F4 for PA9/PA10 + GPIOA->AFR[1] |= 0x440; + GPIOA->MODER &= ~(GPIO_MODER_MODER9 | GPIO_MODER_MODER10); + GPIOA->MODER |= GPIO_MODER_MODER9_AF | GPIO_MODER_MODER10_AF; // alternate function + GPIOA->OTYPER |= GPIO_OTYPER_OT_9 | GPIO_OTYPER_OT_10; // opendrain + //GPIOA->OTYPER |= GPIO_OTYPER_OT_10; // opendrain +#elif I2CPINS == B6B7 +/* + * GPIO Resources: I2C1_SCL - PB6, I2C1_SDA - PB7 (AF1) + * GPIOB->AFR[0] -> 1<<6*4 | 1<<7*4 = 0x11000000 + */ + GPIOB->AFR[0] = (GPIOB->AFR[0] & ~0xff000000) | 0x11000000; + GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER6 | GPIO_MODER_MODER7)) | + GPIO_MODER_MODER6_AF | GPIO_MODER_MODER7_AF; + GPIOB->OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7; +#else // undefined +#error "Not implemented" +#endif + // I2C + RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // timing + RCC->CFGR3 |= RCC_CFGR3_I2C1SW; // use sysclock for timing + if(speed == LOW_SPEED){ // 10kHz + // PRESC=B, SCLDEL=4, SDADEL=2, SCLH=0xC3, SCLL=0xB0 + I2C1->TIMINGR = (0xB<<28) | (4<<20) | (2<<16) | (0xC3<<8) | (0xB0); + }else{ // 100kHz + I2C1->TIMINGR = (0xB<<28) | (4<<20) | (2<<16) | (0x12<<8) | (0x11); + } + I2C1->CR1 = I2C_CR1_PE;// | I2C_CR1_RXIE; // Enable I2C & (interrupt on receive - not supported yet) +} diff --git a/STM32/TSYS_controller/hardware.h b/STM32/TSYS_controller/hardware.h new file mode 100644 index 0000000..a410cd5 --- /dev/null +++ b/STM32/TSYS_controller/hardware.h @@ -0,0 +1,86 @@ +/* + * geany_encoding=koi8-r + * hardware.h + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ +#pragma once +#ifndef __HARDWARE_H__ +#define __HARDWARE_H__ + +#include "stm32f0.h" + +// LED0 +#define LED0_port GPIOB +#define LED0_pin (1<<10) +// LED1 +#define LED1_port GPIOB +#define LED1_pin (1<<11) + +#ifndef USARTNUM +#define USARTNUM 2 +#endif + +#define CONCAT(a,b) a ## b +#define STR_HELPER(s) #s +#define STR(s) STR_HELPER(s) + +#define FORMUSART(X) CONCAT(USART, X) +#define USARTX FORMUSART(USARTNUM) + +#ifndef I2CPINS +#define I2CPINS A9A10 +#endif + +#ifndef LED1_port +#define LED1_port LED0_port +#endif +#ifndef LED1_pin +#define LED1_pin LED0_pin +#endif +#define LED_blink(x) pin_toggle(x ## _port, x ## _pin) + +// set active channel number +#define MUL_ADDRESS(x) do{GPIOB->BSRR = (0x7 << 16) | (x);}while(0) +// address from 0 to 7 +// WARNING!!! In current case all variables for sensors counting are uint8_t, so if +// MUL_MAX_ADDRESS would be greater than 7 you need to edit sensors_manage.c +#define MUL_MAX_ADDRESS (7) +// turn multiplexer on/off (PB12 -> 1/0) +#define MUL_ON() pin_clear(GPIOB, (1<<12)) +#define MUL_OFF() pin_set(GPIOB, (1<<12)) + +// turn on/off power of sensors (PA8-> 1/0) +#define SENSORS_ON() pin_set(GPIOA, (1<<8)) +#define SENSORS_OFF() pin_clear(GPIOA, (1<<8)) +// check overcurrent (PB3 == 0) +#define SENSORS_OVERCURNT() ((1<<3) != (GPIOB->IDR & (1<<3))) + +typedef enum{ + LOW_SPEED, + HIGH_SPEED, + CURRENT_SPEED +} I2C_SPEED; + +extern I2C_SPEED curI2Cspeed; + +void gpio_setup(void); +void i2c_setup(I2C_SPEED speed); + +#endif // __HARDWARE_H__ diff --git a/STM32/TSYS_controller/i2c.c b/STM32/TSYS_controller/i2c.c new file mode 100644 index 0000000..11412df --- /dev/null +++ b/STM32/TSYS_controller/i2c.c @@ -0,0 +1,99 @@ +/* + * geany_encoding=koi8-r + * i2c.c + * + * Copyright 2017 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ +#include "stm32f0.h" +#include "hardware.h" +#include "i2c.h" + +/** + * I2C for TSYS01 + * Speed <= 400kHz (200) + * t_SCLH > 21ns + * t_SCLL > 21ns + * while reading, sends NACK + * after reading get 24bits of T value, we need upper 2 bytes: ADC16 = ADC>>8 + * T = (-2) * k4 * 10^{-21} * ADC16^4 + * + 4 * k3 * 10^{-16} * ADC16^3 + * + (-2) * k2 * 10^{-11} * ADC16^2 + * + 1 * k1 * 10^{-6} * ADC16 + * +(-1.5)* k0 * 10^{-2} + * All coefficiens are in registers: + * k4 - 0xA2, k3 - 0xA4, k2 - 0xA6, k1 - 0xA8, k0 - 0xAA + */ + +extern volatile uint32_t Tms; +static uint32_t cntr; + +/** + * write command byte to I2C + * @param addr - device address (TSYS01_ADDR0 or TSYS01_ADDR1) + * @param data - byte to write + * @return 0 if error + */ +uint8_t write_i2c(uint8_t addr, uint8_t data){ + cntr = Tms; + while(I2C1->ISR & I2C_ISR_BUSY) if(Tms - cntr > I2C_TIMEOUT) return 0; // check busy + cntr = Tms; + while(I2C1->CR2 & I2C_CR2_START) if(Tms - cntr > I2C_TIMEOUT) return 0; // check start + I2C1->CR2 = 1<<16 | addr | I2C_CR2_AUTOEND; // 1 byte, autoend + // now start transfer + I2C1->CR2 |= I2C_CR2_START; + cntr = Tms; + while(!(I2C1->ISR & I2C_ISR_TXIS)){ // ready to transmit + if(I2C1->ISR & I2C_ISR_NACKF){ + I2C1->ICR |= I2C_ICR_NACKCF; + return 0; + } + if(Tms - cntr > I2C_TIMEOUT) return 0; + } + I2C1->TXDR = data; // send data + return 1; +} + +/** + * read nbytes (2 or 3) of data from I2C line + * @return 1 if all OK, 0 if NACK or no device found + */ +uint8_t read_i2c(uint8_t addr, uint32_t *data, uint8_t nbytes){ + uint32_t result = 0; + cntr = Tms; + while(I2C1->ISR & I2C_ISR_BUSY) if(Tms - cntr > 5) return 0; // check busy + cntr = Tms; + while(I2C1->CR2 & I2C_CR2_START) if(Tms - cntr > 5) return 0; // check start + // read N bytes + I2C1->CR2 = (nbytes<<16) | addr | 1 | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN; + I2C1->CR2 |= I2C_CR2_START; + uint8_t i; + cntr = Tms; + for(i = 0; i < nbytes; ++i){ + while(!(I2C1->ISR & I2C_ISR_RXNE)){ // wait for data + if(I2C1->ISR & I2C_ISR_NACKF){ + I2C1->ICR |= I2C_ICR_NACKCF; + return 0; + } + if(Tms - cntr > 5) return 0; + } + result = (result << 8) | I2C1->RXDR; + } + *data = result; + return 1; + } diff --git a/STM32/TSYS_controller/i2c.h b/STM32/TSYS_controller/i2c.h new file mode 100644 index 0000000..da481b7 --- /dev/null +++ b/STM32/TSYS_controller/i2c.h @@ -0,0 +1,39 @@ +/* + * geany_encoding=koi8-r + * i2c.h + * + * Copyright 2017 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ + +// timeout in ms +#define I2C_TIMEOUT (15) +// CSB=1, address 1110110 +#define TSYS01_ADDR0 (0x76 << 1) +// CSB=0, address 1110111 +#define TSYS01_ADDR1 (0x77 << 1) +// registers: reset, read ADC value, start converstion, sart of PROM +#define TSYS01_RESET (0x1E) +#define TSYS01_ADC_READ (0x00) +#define TSYS01_START_CONV (0x48) +#define TSYS01_PROM_ADDR0 (0xA0) +// conversion time = 10ms +#define CONV_TIME (10) + +uint8_t read_i2c(uint8_t addr, uint32_t *data, uint8_t nbytes); +uint8_t write_i2c(uint8_t addr, uint8_t data); diff --git a/STM32/TSYS_controller/ld/stm32f042k.ld b/STM32/TSYS_controller/ld/stm32f042k.ld new file mode 100644 index 0000000..e747253 --- /dev/null +++ b/STM32/TSYS_controller/ld/stm32f042k.ld @@ -0,0 +1,12 @@ +/* Linker script for STM32F042x6, 32K flash, 6K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K +} + +/* Include the common ld script. */ +INCLUDE stm32f0.ld + diff --git a/STM32/TSYS_controller/main.c b/STM32/TSYS_controller/main.c new file mode 100644 index 0000000..916d07a --- /dev/null +++ b/STM32/TSYS_controller/main.c @@ -0,0 +1,98 @@ +/* + * main.c + * + * Copyright 2017 Edward V. Emelianoff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include "hardware.h" +#include "usart.h" +#include "i2c.h" +#include "sensors_manage.h" + +volatile uint32_t Tms = 0; + +/* Called when systick fires */ +void sys_tick_handler(void){ + ++Tms; +} + +int main(void){ + uint32_t lastT = 0; + int16_t L = 0; + char *txt; + sysreset(); + SysTick_Config(6000, 1); + gpio_setup(); + usart_setup(); + i2c_setup(LOW_SPEED); + // reset on start + write_i2c(TSYS01_ADDR0, TSYS01_RESET); + write_i2c(TSYS01_ADDR1, TSYS01_RESET); + + while (1){ + if(lastT > Tms || Tms - lastT > 499){ + LED_blink(LED0); + lastT = Tms; + } + sensors_process(); + if(usartrx()){ // usart1 received data, store in in buffer + L = usart_getline(&txt); + char _1st = txt[0]; + if(L == 2 && txt[1] == '\n'){ + L = 0; + switch(_1st){ + case 'C': // 'C' - show coefficients + showcoeffs(); + break; + case 'D': + sensors_on(); + break; + case 'T': // 'T' - get temperature + showtemperature(); + break; + case 'R': + i2c_setup(CURRENT_SPEED); + SEND("Reinit I2C\n"); + break; + case 'L': + i2c_setup(LOW_SPEED); + SEND("Low speed\n"); + break; + case 'H': + i2c_setup(HIGH_SPEED); + SEND("High speed\n"); + break; + default: // help + SEND("'C' - show coefficients\n" + "'D' - slave discovery\n" + "'T' - get raw temperature\n" + "'R' - reinit I2C\n" + "'L' - low speed\n" + "'H' - high speed\n"); + break; + } + } + } + if(L){ // text waits for sending + while(LINE_BUSY == usart_send(txt, L)); + L = 0; + } + } + return 0; +} + diff --git a/STM32/TSYS_controller/sensors_manage.c b/STM32/TSYS_controller/sensors_manage.c new file mode 100644 index 0000000..43a452f --- /dev/null +++ b/STM32/TSYS_controller/sensors_manage.c @@ -0,0 +1,323 @@ +/* + * geany_encoding=koi8-r + * sensors_manage.c + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ +#include "sensors_manage.h" +#include "i2c.h" +#include "usart.h" + +extern volatile uint32_t Tms; +static uint32_t lastSensT = 0; +static SensorsState Sstate = SENS_OFF; // turn on sensors only by request +static uint8_t curr_mul_addr = 0; // current sensors pair address @ multiplexer +static uint8_t overcurnt_ctr = 0; // if this counter > 32 go to OFF state +static uint8_t sens_present[2] = {0,0}; // bit flag: Nth bit == 1 if sensor[s] on given channel found +static uint8_t Nsens_present = 0; // total amount of sensors found +static uint8_t Ntemp_measured = 0; // total amount of themperatures measured + +// 8 - amount of pairs, 2 - amount in pair, 5 - amount of Coef. +static uint16_t coefficients[MUL_MAX_ADDRESS+1][2][5]; // Coefficients for given sensors +// measured temperatures * 100 +static int16_t Temperatures[MUL_MAX_ADDRESS+1][2]; + +// pair addresses +static const uint8_t Taddr[2] = {TSYS01_ADDR0, TSYS01_ADDR1}; + +SensorsState sensors_get_state(){return Sstate;} + +/** + * Get temperature & calculate it by polinome + * T = (-2) * k4 * 10^{-21} * ADC16^4 + * + 4 * k3 * 10^{-16} * ADC16^3 + * + (-2) * k2 * 10^{-11} * ADC16^2 + * + 1 * k1 * 10^{-6} * ADC16 + * +(-1.5)* k0 * 10^{-2} + * k0*(-1.5e-2) + 1e-6*val*(k1 + 1e-5*val*(-2*k2 + 1e-5*val*(4*k3 + -2e-5*k4*val))) + * + * @param t - value from sensor + * @param i - number of sensor in pair + * @return -30000 if something wrong or T*100 if all OK + */ +static uint16_t calc_t(uint32_t t, int i){ + uint16_t *coeff = coefficients[curr_mul_addr][i]; + if(coeff[0] == 0) return BAD_TEMPERATURE; // what is with coeffs? + if(t < 6500000 || t > 13000000) return BAD_TEMPERATURE; // wrong value - too small or too large + int j; + double d = (double)t/256., tmp = 0.; + // k0*(-1.5e-2) + 0.1*1e-5*val*(1*k1 + 1e-5*val*(-2.*k2 + 1e-5*val*(4*k3 + 1e-5*val*(-2*k4)))) + const double mul[5] = {-1.5e-2, 1., -2., 4., -2.}; + for(j = 4; j > 0; --j){ + tmp += mul[j] * (double)coeff[j]; + tmp *= 1e-5*d; + } + tmp = tmp * 10. + 100. * mul[0] * coeff[0]; + return (uint16_t)tmp; +} + +// turn off sensors' power +void sensors_off(){ + MUL_OFF(); // turn off multiplexers + SENSORS_OFF(); // turn off sensors' power + Sstate = SENS_OFF; +} + +/** + * if all OK with current, turn ON sensors' power and change state to "initing" + */ +void sensors_on(){ + sens_present[0] = sens_present[1] = 0; + curr_mul_addr = 0; + Nsens_present = 0; + MUL_OFF(); + if(SENSORS_OVERCURNT()){ + SENSORS_OFF(); + Sstate = (++overcurnt_ctr > 32) ? SENS_OVERCURNT_OFF : SENS_OVERCURNT; + }else{ + SENSORS_ON(); + Sstate = SENS_INITING; + } +} + +/* / count bits in byte +static uint8_t bitCount(uint8_t B){ + uint8_t ctr = 0; + while(B){ + ++ctr; + B &= (B - 1); + } + return ctr; +}*/ + +// count 1 bits in sens_present & set `Nsens_present` to this value +static void count_sensors(){ + Nsens_present = 0; + uint16_t B = sens_present[0]<<8 | sens_present[1]; + while(B){ + ++Nsens_present; + B &= (B - 1); + } + /* / reset temperature values + uint16_t *t = Temperatures; + for(B = 0; B < 2*(MUL_MAX_ADDRESS+1); ++B) + *t++ = BAD_TEMPERATURE; */ +} + +/** + * All procedures return 1 if they change current state due to error & 0 if all OK + */ +// procedure call each time @ resetting +static uint8_t resetproc(){ + uint8_t i, ctr = 0; + SEND("pair "); printu(curr_mul_addr); + SEND(" : "); + for(i = 0; i < 2; ++i){ + if(write_i2c(Taddr[i], TSYS01_RESET)){ + usart_putchar('0' + i); + ++ctr; + sens_present[i] |= 1< MUL_MAX_ADDRESS){ // scan is over + curr_mul_addr = 0; + return 1; + } + } + return 0; +} + +// print coefficients @debug console +void showcoeffs(){ + int a, p, k; + for(a = 0; a <= MUL_MAX_ADDRESS; ++a){ + for(p = 0; p < 2; ++p){ + if(!(sens_present[p] & (1< 32) ? SENS_OVERCURNT_OFF : SENS_OVERCURNT; + return; + } + switch (Sstate){ + case SENS_INITING: // initialisation (restart I2C) + i2c_setup(CURRENT_SPEED); + Sstate = SENS_RESETING; + break; + case SENS_RESETING: // reset & discovery procedure + overcurnt_ctr = 0; + if(sensors_scan(resetproc)) Sstate = SENS_GET_COEFFS; + break; + case SENS_GET_COEFFS: // get coefficients + if(sensors_scan(getcoefsproc)){ + count_sensors(); // get total amount of sensors + Sstate = SENS_START_MSRMNT; + } + break; + case SENS_START_MSRMNT: // send all sensors command to start measurements + if(sensors_scan(msrtempproc)){ + lastSensT = Tms; + Sstate = SENS_WAITING; + Ntemp_measured = 0; // reset value of good measurements + } + break; + case SENS_WAITING: // wait for end of conversion + if(Tms - lastSensT > CONV_TIME){ + Sstate = SENS_GATHERING; + } + break; + case SENS_GATHERING: // scan all sensors, get thermal data & calculate temperature + if(sensors_scan(gettempproc)){ + lastSensT = Tms; + if(Nsens_present == Ntemp_measured) // All OK, amount of T == amount of sensors + Sstate = SENS_SLEEPING; + else{ // reinit I2C & try to start measurements again + i2c_setup(CURRENT_SPEED); + Sstate = SENS_START_MSRMNT; + } + } + break; + case SENS_SLEEPING: // wait for `SLEEP_TIME` till next measurements + if(Tms - lastSensT > SLEEP_TIME){ + Sstate = SENS_START_MSRMNT; + } + break; + case SENS_OVERCURNT: // try to reinit all after overcurrent + sensors_on(); + break; + default: // do nothing + break; + } +} diff --git a/STM32/TSYS_controller/sensors_manage.h b/STM32/TSYS_controller/sensors_manage.h new file mode 100644 index 0000000..b79e081 --- /dev/null +++ b/STM32/TSYS_controller/sensors_manage.h @@ -0,0 +1,56 @@ +/* + * geany_encoding=koi8-r + * sensors_manage.h + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ +#pragma once +#ifndef __SENSORS_MANAGE_H__ +#define __SENSORS_MANAGE_H__ + +#include "hardware.h" + +// time between two readings (3sec) +#define SLEEP_TIME (3000) +// error in measurement == -300degrC +#define BAD_TEMPERATURE (-30000) + +typedef enum{ + SENS_INITING // power on + ,SENS_RESETING // discovery sensors resetting them + ,SENS_GET_COEFFS // get coefficients from all sensors + ,SENS_SLEEPING // wait for a time to process measurements + ,SENS_START_MSRMNT // send command 2 start measurement + ,SENS_WAITING // wait for measurements end + ,SENS_GATHERING // collect information + ,SENS_OFF // sensors' power is off by external command + ,SENS_OVERCURNT // overcurrent detected @ any stage + ,SENS_OVERCURNT_OFF // sensors' power is off due to continuous overcurrent +} SensorsState; + +SensorsState sensors_get_state(); +void sensors_process(); + +void sensors_off(); +void sensors_on(); + +void showcoeffs(); +void showtemperature(); + +#endif // __SENSORS_MANAGE_H__ diff --git a/STM32/TSYS_controller/tmp_UPGWJZ.d b/STM32/TSYS_controller/tmp_UPGWJZ.d new file mode 100644 index 0000000..951ce81 --- /dev/null +++ b/STM32/TSYS_controller/tmp_UPGWJZ.d @@ -0,0 +1,17 @@ +tmp_UPGWJZ.o: /tmp/tmp_UPGWJZ.cpp /usr/include/stdc-predef.h i2c.h \ + usart.c ../inc/F0/stm32f0.h ../inc/F0/stm32f0xx.h \ + ../inc/F0/stm32f042x6.h ../inc/cm/core_cm0.h \ + /usr/lib/gcc/x86_64-pc-linux-gnu/6.4.0/include/stdint.h \ + /usr/include/stdint.h /usr/include/bits/libc-header-start.h \ + /usr/include/features.h /usr/include/sys/cdefs.h \ + /usr/include/bits/wordsize.h /usr/include/bits/long-double.h \ + /usr/include/gnu/stubs.h /usr/include/gnu/stubs-64.h \ + /usr/include/bits/types.h /usr/include/bits/typesizes.h \ + /usr/include/bits/wchar.h /usr/include/bits/stdint-intn.h \ + /usr/include/bits/stdint-uintn.h ../inc/cm/core_cmInstr.h \ + ../inc/cm/core_cmFunc.h hardware.h usart.h /usr/include/string.h \ + /usr/lib/gcc/x86_64-pc-linux-gnu/6.4.0/include/stddef.h \ + /usr/include/bits/types/locale_t.h /usr/include/bits/types/__locale_t.h \ + /usr/include/strings.h /usr/include/bits/strings_fortified.h \ + /usr/include/bits/string_fortified.h main.c i2c.h i2c.c hardware.h \ + hardware.c diff --git a/STM32/TSYS_controller/tsys01.bin b/STM32/TSYS_controller/tsys01.bin new file mode 100755 index 0000000..6d836ad Binary files /dev/null and b/STM32/TSYS_controller/tsys01.bin differ diff --git a/STM32/TSYS_controller/tsys01.c.tags b/STM32/TSYS_controller/tsys01.c.tags new file mode 100644 index 0000000..ce75179 --- /dev/null +++ b/STM32/TSYS_controller/tsys01.c.tags @@ -0,0 +1,4408 @@ +# format=tagmanager +ADCÌ65536Ö0 +ADC1Ì65536Ö0 +ADC1_BASEÌ65536Ö0 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+EXTI_BASEÌ65536Ö0 +EXTI_EMR_MR0Ì65536Ö0 +EXTI_EMR_MR1Ì65536Ö0 +EXTI_EMR_MR10Ì65536Ö0 +EXTI_EMR_MR11Ì65536Ö0 +EXTI_EMR_MR12Ì65536Ö0 +EXTI_EMR_MR13Ì65536Ö0 +EXTI_EMR_MR14Ì65536Ö0 +EXTI_EMR_MR15Ì65536Ö0 +EXTI_EMR_MR16Ì65536Ö0 +EXTI_EMR_MR17Ì65536Ö0 +EXTI_EMR_MR19Ì65536Ö0 +EXTI_EMR_MR2Ì65536Ö0 +EXTI_EMR_MR21Ì65536Ö0 +EXTI_EMR_MR22Ì65536Ö0 +EXTI_EMR_MR23Ì65536Ö0 +EXTI_EMR_MR25Ì65536Ö0 +EXTI_EMR_MR27Ì65536Ö0 +EXTI_EMR_MR3Ì65536Ö0 +EXTI_EMR_MR4Ì65536Ö0 +EXTI_EMR_MR5Ì65536Ö0 +EXTI_EMR_MR6Ì65536Ö0 +EXTI_EMR_MR7Ì65536Ö0 +EXTI_EMR_MR8Ì65536Ö0 +EXTI_EMR_MR9Ì65536Ö0 +EXTI_FTSR_TR0Ì65536Ö0 +EXTI_FTSR_TR1Ì65536Ö0 +EXTI_FTSR_TR10Ì65536Ö0 +EXTI_FTSR_TR11Ì65536Ö0 +EXTI_FTSR_TR12Ì65536Ö0 +EXTI_FTSR_TR13Ì65536Ö0 +EXTI_FTSR_TR14Ì65536Ö0 +EXTI_FTSR_TR15Ì65536Ö0 +EXTI_FTSR_TR16Ì65536Ö0 +EXTI_FTSR_TR17Ì65536Ö0 +EXTI_FTSR_TR19Ì65536Ö0 +EXTI_FTSR_TR2Ì65536Ö0 +EXTI_FTSR_TR3Ì65536Ö0 +EXTI_FTSR_TR4Ì65536Ö0 +EXTI_FTSR_TR5Ì65536Ö0 +EXTI_FTSR_TR6Ì65536Ö0 +EXTI_FTSR_TR7Ì65536Ö0 +EXTI_FTSR_TR8Ì65536Ö0 +EXTI_FTSR_TR9Ì65536Ö0 +EXTI_IMR_MR0Ì65536Ö0 +EXTI_IMR_MR1Ì65536Ö0 +EXTI_IMR_MR10Ì65536Ö0 +EXTI_IMR_MR11Ì65536Ö0 +EXTI_IMR_MR12Ì65536Ö0 +EXTI_IMR_MR13Ì65536Ö0 +EXTI_IMR_MR14Ì65536Ö0 +EXTI_IMR_MR15Ì65536Ö0 +EXTI_IMR_MR16Ì65536Ö0 +EXTI_IMR_MR17Ì65536Ö0 +EXTI_IMR_MR19Ì65536Ö0 +EXTI_IMR_MR2Ì65536Ö0 +EXTI_IMR_MR21Ì65536Ö0 +EXTI_IMR_MR22Ì65536Ö0 +EXTI_IMR_MR23Ì65536Ö0 +EXTI_IMR_MR25Ì65536Ö0 +EXTI_IMR_MR27Ì65536Ö0 +EXTI_IMR_MR3Ì65536Ö0 +EXTI_IMR_MR4Ì65536Ö0 +EXTI_IMR_MR5Ì65536Ö0 +EXTI_IMR_MR6Ì65536Ö0 +EXTI_IMR_MR7Ì65536Ö0 +EXTI_IMR_MR8Ì65536Ö0 +EXTI_IMR_MR9Ì65536Ö0 +EXTI_PR_PR0Ì65536Ö0 +EXTI_PR_PR1Ì65536Ö0 +EXTI_PR_PR10Ì65536Ö0 +EXTI_PR_PR11Ì65536Ö0 +EXTI_PR_PR12Ì65536Ö0 +EXTI_PR_PR13Ì65536Ö0 +EXTI_PR_PR14Ì65536Ö0 +EXTI_PR_PR15Ì65536Ö0 +EXTI_PR_PR16Ì65536Ö0 +EXTI_PR_PR17Ì65536Ö0 +EXTI_PR_PR19Ì65536Ö0 +EXTI_PR_PR2Ì65536Ö0 +EXTI_PR_PR3Ì65536Ö0 +EXTI_PR_PR4Ì65536Ö0 +EXTI_PR_PR5Ì65536Ö0 +EXTI_PR_PR6Ì65536Ö0 +EXTI_PR_PR7Ì65536Ö0 +EXTI_PR_PR8Ì65536Ö0 +EXTI_PR_PR9Ì65536Ö0 +EXTI_RTSR_TR0Ì65536Ö0 +EXTI_RTSR_TR1Ì65536Ö0 +EXTI_RTSR_TR10Ì65536Ö0 +EXTI_RTSR_TR11Ì65536Ö0 +EXTI_RTSR_TR12Ì65536Ö0 +EXTI_RTSR_TR13Ì65536Ö0 +EXTI_RTSR_TR14Ì65536Ö0 +EXTI_RTSR_TR15Ì65536Ö0 +EXTI_RTSR_TR16Ì65536Ö0 +EXTI_RTSR_TR17Ì65536Ö0 +EXTI_RTSR_TR19Ì65536Ö0 +EXTI_RTSR_TR2Ì65536Ö0 +EXTI_RTSR_TR3Ì65536Ö0 +EXTI_RTSR_TR4Ì65536Ö0 +EXTI_RTSR_TR5Ì65536Ö0 +EXTI_RTSR_TR6Ì65536Ö0 +EXTI_RTSR_TR7Ì65536Ö0 +EXTI_RTSR_TR8Ì65536Ö0 +EXTI_RTSR_TR9Ì65536Ö0 +EXTI_SWIER_SWIER0Ì65536Ö0 +EXTI_SWIER_SWIER1Ì65536Ö0 +EXTI_SWIER_SWIER10Ì65536Ö0 +EXTI_SWIER_SWIER11Ì65536Ö0 +EXTI_SWIER_SWIER12Ì65536Ö0 +EXTI_SWIER_SWIER13Ì65536Ö0 +EXTI_SWIER_SWIER14Ì65536Ö0 +EXTI_SWIER_SWIER15Ì65536Ö0 +EXTI_SWIER_SWIER16Ì65536Ö0 +EXTI_SWIER_SWIER17Ì65536Ö0 +EXTI_SWIER_SWIER19Ì65536Ö0 +EXTI_SWIER_SWIER2Ì65536Ö0 +EXTI_SWIER_SWIER3Ì65536Ö0 +EXTI_SWIER_SWIER4Ì65536Ö0 +EXTI_SWIER_SWIER5Ì65536Ö0 +EXTI_SWIER_SWIER6Ì65536Ö0 +EXTI_SWIER_SWIER7Ì65536Ö0 +EXTI_SWIER_SWIER8Ì65536Ö0 +EXTI_SWIER_SWIER9Ì65536Ö0 +FLASHÌ65536Ö0 +FLASH_ACR_LATENCYÌ65536Ö0 +FLASH_ACR_PRFTBEÌ65536Ö0 +FLASH_ACR_PRFTBSÌ65536Ö0 +FLASH_AR_FARÌ65536Ö0 +FLASH_BASEÌ65536Ö0 +FLASH_CR_EOPIEÌ65536Ö0 +FLASH_CR_ERRIEÌ65536Ö0 +FLASH_CR_LOCKÌ65536Ö0 +FLASH_CR_MERÌ65536Ö0 +FLASH_CR_OBL_LAUNCHÌ65536Ö0 +FLASH_CR_OPTERÌ65536Ö0 +FLASH_CR_OPTPGÌ65536Ö0 +FLASH_CR_OPTWREÌ65536Ö0 +FLASH_CR_PERÌ65536Ö0 +FLASH_CR_PGÌ65536Ö0 +FLASH_CR_STRTÌ65536Ö0 +FLASH_FKEY1Ì65536Ö0 +FLASH_FKEY2Ì65536Ö0 +FLASH_KEYR_FKEYRÌ65536Ö0 +FLASH_OBR_BOOT1Ì65536Ö0 +FLASH_OBR_IWDG_SWÌ65536Ö0 +FLASH_OBR_OPTERRÌ65536Ö0 +FLASH_OBR_RDPRT1Ì65536Ö0 +FLASH_OBR_RDPRT2Ì65536Ö0 +FLASH_OBR_USERÌ65536Ö0 +FLASH_OBR_VDDA_ANALOGÌ65536Ö0 +FLASH_OBR_VDDA_MONITORÌ65536Ö0 +FLASH_OBR_nBOOT1Ì65536Ö0 +FLASH_OBR_nRST_STDBYÌ65536Ö0 +FLASH_OBR_nRST_STOPÌ65536Ö0 +FLASH_OPTKEY1Ì65536Ö0 +FLASH_OPTKEY2Ì65536Ö0 +FLASH_OPTKEYR_OPTKEYRÌ65536Ö0 +FLASH_R_BASEÌ65536Ö0 +FLASH_SR_BSYÌ65536Ö0 +FLASH_SR_EOPÌ65536Ö0 +FLASH_SR_PGERRÌ65536Ö0 +FLASH_SR_WRPERRÌ65536Ö0 +FLASH_SR_WRPRTERRÌ65536Ö0 +FLASH_WRPR_WRPÌ65536Ö0 +FORMUSARTÌ131072Í(X)Ö0 +GPIOAÌ65536Ö0 +GPIOA_BASEÌ65536Ö0 +GPIOBÌ65536Ö0 +GPIOB_BASEÌ65536Ö0 +GPIOCÌ65536Ö0 +GPIOC_BASEÌ65536Ö0 +GPIOFÌ65536Ö0 +GPIOF_BASEÌ65536Ö0 +GPIO_AFRH_AFRH0Ì65536Ö0 +GPIO_AFRH_AFRH1Ì65536Ö0 +GPIO_AFRH_AFRH2Ì65536Ö0 +GPIO_AFRH_AFRH3Ì65536Ö0 +GPIO_AFRH_AFRH4Ì65536Ö0 +GPIO_AFRH_AFRH5Ì65536Ö0 +GPIO_AFRH_AFRH6Ì65536Ö0 +GPIO_AFRH_AFRH7Ì65536Ö0 +GPIO_AFRL_AFRL0Ì65536Ö0 +GPIO_AFRL_AFRL1Ì65536Ö0 +GPIO_AFRL_AFRL2Ì65536Ö0 +GPIO_AFRL_AFRL3Ì65536Ö0 +GPIO_AFRL_AFRL4Ì65536Ö0 +GPIO_AFRL_AFRL5Ì65536Ö0 +GPIO_AFRL_AFRL6Ì65536Ö0 +GPIO_AFRL_AFRL7Ì65536Ö0 +GPIO_BRR_BR_0Ì65536Ö0 +GPIO_BRR_BR_1Ì65536Ö0 +GPIO_BRR_BR_10Ì65536Ö0 +GPIO_BRR_BR_11Ì65536Ö0 +GPIO_BRR_BR_12Ì65536Ö0 +GPIO_BRR_BR_13Ì65536Ö0 +GPIO_BRR_BR_14Ì65536Ö0 +GPIO_BRR_BR_15Ì65536Ö0 +GPIO_BRR_BR_2Ì65536Ö0 +GPIO_BRR_BR_3Ì65536Ö0 +GPIO_BRR_BR_4Ì65536Ö0 +GPIO_BRR_BR_5Ì65536Ö0 +GPIO_BRR_BR_6Ì65536Ö0 +GPIO_BRR_BR_7Ì65536Ö0 +GPIO_BRR_BR_8Ì65536Ö0 +GPIO_BRR_BR_9Ì65536Ö0 +GPIO_BSRR_BR_0Ì65536Ö0 +GPIO_BSRR_BR_1Ì65536Ö0 +GPIO_BSRR_BR_10Ì65536Ö0 +GPIO_BSRR_BR_11Ì65536Ö0 +GPIO_BSRR_BR_12Ì65536Ö0 +GPIO_BSRR_BR_13Ì65536Ö0 +GPIO_BSRR_BR_14Ì65536Ö0 +GPIO_BSRR_BR_15Ì65536Ö0 +GPIO_BSRR_BR_2Ì65536Ö0 +GPIO_BSRR_BR_3Ì65536Ö0 +GPIO_BSRR_BR_4Ì65536Ö0 +GPIO_BSRR_BR_5Ì65536Ö0 +GPIO_BSRR_BR_6Ì65536Ö0 +GPIO_BSRR_BR_7Ì65536Ö0 +GPIO_BSRR_BR_8Ì65536Ö0 +GPIO_BSRR_BR_9Ì65536Ö0 +GPIO_BSRR_BS_0Ì65536Ö0 +GPIO_BSRR_BS_1Ì65536Ö0 +GPIO_BSRR_BS_10Ì65536Ö0 +GPIO_BSRR_BS_11Ì65536Ö0 +GPIO_BSRR_BS_12Ì65536Ö0 +GPIO_BSRR_BS_13Ì65536Ö0 +GPIO_BSRR_BS_14Ì65536Ö0 +GPIO_BSRR_BS_15Ì65536Ö0 +GPIO_BSRR_BS_2Ì65536Ö0 +GPIO_BSRR_BS_3Ì65536Ö0 +GPIO_BSRR_BS_4Ì65536Ö0 +GPIO_BSRR_BS_5Ì65536Ö0 +GPIO_BSRR_BS_6Ì65536Ö0 +GPIO_BSRR_BS_7Ì65536Ö0 +GPIO_BSRR_BS_8Ì65536Ö0 +GPIO_BSRR_BS_9Ì65536Ö0 +GPIO_IDR_0Ì65536Ö0 +GPIO_IDR_1Ì65536Ö0 +GPIO_IDR_10Ì65536Ö0 +GPIO_IDR_11Ì65536Ö0 +GPIO_IDR_12Ì65536Ö0 +GPIO_IDR_13Ì65536Ö0 +GPIO_IDR_14Ì65536Ö0 +GPIO_IDR_15Ì65536Ö0 +GPIO_IDR_2Ì65536Ö0 +GPIO_IDR_3Ì65536Ö0 +GPIO_IDR_4Ì65536Ö0 +GPIO_IDR_5Ì65536Ö0 +GPIO_IDR_6Ì65536Ö0 +GPIO_IDR_7Ì65536Ö0 +GPIO_IDR_8Ì65536Ö0 +GPIO_IDR_9Ì65536Ö0 +GPIO_LCKR_LCK0Ì65536Ö0 +GPIO_LCKR_LCK1Ì65536Ö0 +GPIO_LCKR_LCK10Ì65536Ö0 +GPIO_LCKR_LCK11Ì65536Ö0 +GPIO_LCKR_LCK12Ì65536Ö0 +GPIO_LCKR_LCK13Ì65536Ö0 +GPIO_LCKR_LCK14Ì65536Ö0 +GPIO_LCKR_LCK15Ì65536Ö0 +GPIO_LCKR_LCK2Ì65536Ö0 +GPIO_LCKR_LCK3Ì65536Ö0 +GPIO_LCKR_LCK4Ì65536Ö0 +GPIO_LCKR_LCK5Ì65536Ö0 +GPIO_LCKR_LCK6Ì65536Ö0 +GPIO_LCKR_LCK7Ì65536Ö0 +GPIO_LCKR_LCK8Ì65536Ö0 +GPIO_LCKR_LCK9Ì65536Ö0 +GPIO_LCKR_LCKKÌ65536Ö0 +GPIO_MODER_MODER0Ì65536Ö0 +GPIO_MODER_MODER0_0Ì65536Ö0 +GPIO_MODER_MODER0_1Ì65536Ö0 +GPIO_MODER_MODER0_AFÌ65536Ö0 +GPIO_MODER_MODER0_AIÌ65536Ö0 +GPIO_MODER_MODER0_OÌ65536Ö0 +GPIO_MODER_MODER1Ì65536Ö0 +GPIO_MODER_MODER10Ì65536Ö0 +GPIO_MODER_MODER10_0Ì65536Ö0 +GPIO_MODER_MODER10_1Ì65536Ö0 +GPIO_MODER_MODER10_AFÌ65536Ö0 +GPIO_MODER_MODER10_AIÌ65536Ö0 +GPIO_MODER_MODER10_OÌ65536Ö0 +GPIO_MODER_MODER11Ì65536Ö0 +GPIO_MODER_MODER11_0Ì65536Ö0 +GPIO_MODER_MODER11_1Ì65536Ö0 +GPIO_MODER_MODER11_AFÌ65536Ö0 +GPIO_MODER_MODER11_AIÌ65536Ö0 +GPIO_MODER_MODER11_OÌ65536Ö0 +GPIO_MODER_MODER12Ì65536Ö0 +GPIO_MODER_MODER12_0Ì65536Ö0 +GPIO_MODER_MODER12_1Ì65536Ö0 +GPIO_MODER_MODER12_AFÌ65536Ö0 +GPIO_MODER_MODER12_AIÌ65536Ö0 +GPIO_MODER_MODER12_OÌ65536Ö0 +GPIO_MODER_MODER13Ì65536Ö0 +GPIO_MODER_MODER13_0Ì65536Ö0 +GPIO_MODER_MODER13_1Ì65536Ö0 +GPIO_MODER_MODER13_AFÌ65536Ö0 +GPIO_MODER_MODER13_AIÌ65536Ö0 +GPIO_MODER_MODER13_OÌ65536Ö0 +GPIO_MODER_MODER14Ì65536Ö0 +GPIO_MODER_MODER14_0Ì65536Ö0 +GPIO_MODER_MODER14_1Ì65536Ö0 +GPIO_MODER_MODER14_AFÌ65536Ö0 +GPIO_MODER_MODER14_AIÌ65536Ö0 +GPIO_MODER_MODER14_OÌ65536Ö0 +GPIO_MODER_MODER15Ì65536Ö0 +GPIO_MODER_MODER15_0Ì65536Ö0 +GPIO_MODER_MODER15_1Ì65536Ö0 +GPIO_MODER_MODER15_AFÌ65536Ö0 +GPIO_MODER_MODER15_AIÌ65536Ö0 +GPIO_MODER_MODER15_OÌ65536Ö0 +GPIO_MODER_MODER1_0Ì65536Ö0 +GPIO_MODER_MODER1_1Ì65536Ö0 +GPIO_MODER_MODER1_AFÌ65536Ö0 +GPIO_MODER_MODER1_AIÌ65536Ö0 +GPIO_MODER_MODER1_OÌ65536Ö0 +GPIO_MODER_MODER2Ì65536Ö0 +GPIO_MODER_MODER2_0Ì65536Ö0 +GPIO_MODER_MODER2_1Ì65536Ö0 +GPIO_MODER_MODER2_AFÌ65536Ö0 +GPIO_MODER_MODER2_AIÌ65536Ö0 +GPIO_MODER_MODER2_OÌ65536Ö0 +GPIO_MODER_MODER3Ì65536Ö0 +GPIO_MODER_MODER3_0Ì65536Ö0 +GPIO_MODER_MODER3_1Ì65536Ö0 +GPIO_MODER_MODER3_AFÌ65536Ö0 +GPIO_MODER_MODER3_AIÌ65536Ö0 +GPIO_MODER_MODER3_OÌ65536Ö0 +GPIO_MODER_MODER4Ì65536Ö0 +GPIO_MODER_MODER4_0Ì65536Ö0 +GPIO_MODER_MODER4_1Ì65536Ö0 +GPIO_MODER_MODER4_AFÌ65536Ö0 +GPIO_MODER_MODER4_AIÌ65536Ö0 +GPIO_MODER_MODER4_OÌ65536Ö0 +GPIO_MODER_MODER5Ì65536Ö0 +GPIO_MODER_MODER5_0Ì65536Ö0 +GPIO_MODER_MODER5_1Ì65536Ö0 +GPIO_MODER_MODER5_AFÌ65536Ö0 +GPIO_MODER_MODER5_AIÌ65536Ö0 +GPIO_MODER_MODER5_OÌ65536Ö0 +GPIO_MODER_MODER6Ì65536Ö0 +GPIO_MODER_MODER6_0Ì65536Ö0 +GPIO_MODER_MODER6_1Ì65536Ö0 +GPIO_MODER_MODER6_AFÌ65536Ö0 +GPIO_MODER_MODER6_AIÌ65536Ö0 +GPIO_MODER_MODER6_OÌ65536Ö0 +GPIO_MODER_MODER7Ì65536Ö0 +GPIO_MODER_MODER7_0Ì65536Ö0 +GPIO_MODER_MODER7_1Ì65536Ö0 +GPIO_MODER_MODER7_AFÌ65536Ö0 +GPIO_MODER_MODER7_AIÌ65536Ö0 +GPIO_MODER_MODER7_OÌ65536Ö0 +GPIO_MODER_MODER8Ì65536Ö0 +GPIO_MODER_MODER8_0Ì65536Ö0 +GPIO_MODER_MODER8_1Ì65536Ö0 +GPIO_MODER_MODER8_AFÌ65536Ö0 +GPIO_MODER_MODER8_AIÌ65536Ö0 +GPIO_MODER_MODER8_OÌ65536Ö0 +GPIO_MODER_MODER9Ì65536Ö0 +GPIO_MODER_MODER9_0Ì65536Ö0 +GPIO_MODER_MODER9_1Ì65536Ö0 +GPIO_MODER_MODER9_AFÌ65536Ö0 +GPIO_MODER_MODER9_AIÌ65536Ö0 +GPIO_MODER_MODER9_OÌ65536Ö0 +GPIO_ODR_0Ì65536Ö0 +GPIO_ODR_1Ì65536Ö0 +GPIO_ODR_10Ì65536Ö0 +GPIO_ODR_11Ì65536Ö0 +GPIO_ODR_12Ì65536Ö0 +GPIO_ODR_13Ì65536Ö0 +GPIO_ODR_14Ì65536Ö0 +GPIO_ODR_15Ì65536Ö0 +GPIO_ODR_2Ì65536Ö0 +GPIO_ODR_3Ì65536Ö0 +GPIO_ODR_4Ì65536Ö0 +GPIO_ODR_5Ì65536Ö0 +GPIO_ODR_6Ì65536Ö0 +GPIO_ODR_7Ì65536Ö0 +GPIO_ODR_8Ì65536Ö0 +GPIO_ODR_9Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR0_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR0_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR10Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR10_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR10_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR11Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR11_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR11_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR12Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR12_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR12_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR13Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR13_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR13_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR14Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR14_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR14_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR15Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR15_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR15_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR1_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR1_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR2Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR2_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR2_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR3Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR3_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR3_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR4Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR4_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR4_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR5Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR5_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR5_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR6Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR6_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR6_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR7Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR7_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR7_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR8Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR8_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR8_1Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR9Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR9_0Ì65536Ö0 +GPIO_OSPEEDER_OSPEEDR9_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR0_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR0_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR10Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR10_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR10_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR11Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR11_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR11_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR12Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR12_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR12_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR13Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR13_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR13_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR14Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR14_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR14_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR15Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR15_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR15_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR1_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR1_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR2Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR2_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR2_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR3Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR3_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR3_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR4Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR4_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR4_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR5Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR5_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR5_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR6Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR6_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR6_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR7Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR7_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR7_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR8Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR8_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR8_1Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR9Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR9_0Ì65536Ö0 +GPIO_OSPEEDR_OSPEEDR9_1Ì65536Ö0 +GPIO_OTYPER_OT_0Ì65536Ö0 +GPIO_OTYPER_OT_1Ì65536Ö0 +GPIO_OTYPER_OT_10Ì65536Ö0 +GPIO_OTYPER_OT_11Ì65536Ö0 +GPIO_OTYPER_OT_12Ì65536Ö0 +GPIO_OTYPER_OT_13Ì65536Ö0 +GPIO_OTYPER_OT_14Ì65536Ö0 +GPIO_OTYPER_OT_15Ì65536Ö0 +GPIO_OTYPER_OT_2Ì65536Ö0 +GPIO_OTYPER_OT_3Ì65536Ö0 +GPIO_OTYPER_OT_4Ì65536Ö0 +GPIO_OTYPER_OT_5Ì65536Ö0 +GPIO_OTYPER_OT_6Ì65536Ö0 +GPIO_OTYPER_OT_7Ì65536Ö0 +GPIO_OTYPER_OT_8Ì65536Ö0 +GPIO_OTYPER_OT_9Ì65536Ö0 +GPIO_PUPDR_PUPDR0Ì65536Ö0 +GPIO_PUPDR_PUPDR0_0Ì65536Ö0 +GPIO_PUPDR_PUPDR0_1Ì65536Ö0 +GPIO_PUPDR_PUPDR1Ì65536Ö0 +GPIO_PUPDR_PUPDR10Ì65536Ö0 +GPIO_PUPDR_PUPDR10_0Ì65536Ö0 +GPIO_PUPDR_PUPDR10_1Ì65536Ö0 +GPIO_PUPDR_PUPDR11Ì65536Ö0 +GPIO_PUPDR_PUPDR11_0Ì65536Ö0 +GPIO_PUPDR_PUPDR11_1Ì65536Ö0 +GPIO_PUPDR_PUPDR12Ì65536Ö0 +GPIO_PUPDR_PUPDR12_0Ì65536Ö0 +GPIO_PUPDR_PUPDR12_1Ì65536Ö0 +GPIO_PUPDR_PUPDR13Ì65536Ö0 +GPIO_PUPDR_PUPDR13_0Ì65536Ö0 +GPIO_PUPDR_PUPDR13_1Ì65536Ö0 +GPIO_PUPDR_PUPDR14Ì65536Ö0 +GPIO_PUPDR_PUPDR14_0Ì65536Ö0 +GPIO_PUPDR_PUPDR14_1Ì65536Ö0 +GPIO_PUPDR_PUPDR15Ì65536Ö0 +GPIO_PUPDR_PUPDR15_0Ì65536Ö0 +GPIO_PUPDR_PUPDR15_1Ì65536Ö0 +GPIO_PUPDR_PUPDR1_0Ì65536Ö0 +GPIO_PUPDR_PUPDR1_1Ì65536Ö0 +GPIO_PUPDR_PUPDR2Ì65536Ö0 +GPIO_PUPDR_PUPDR2_0Ì65536Ö0 +GPIO_PUPDR_PUPDR2_1Ì65536Ö0 +GPIO_PUPDR_PUPDR3Ì65536Ö0 +GPIO_PUPDR_PUPDR3_0Ì65536Ö0 +GPIO_PUPDR_PUPDR3_1Ì65536Ö0 +GPIO_PUPDR_PUPDR4Ì65536Ö0 +GPIO_PUPDR_PUPDR4_0Ì65536Ö0 +GPIO_PUPDR_PUPDR4_1Ì65536Ö0 +GPIO_PUPDR_PUPDR5Ì65536Ö0 +GPIO_PUPDR_PUPDR5_0Ì65536Ö0 +GPIO_PUPDR_PUPDR5_1Ì65536Ö0 +GPIO_PUPDR_PUPDR6Ì65536Ö0 +GPIO_PUPDR_PUPDR6_0Ì65536Ö0 +GPIO_PUPDR_PUPDR6_1Ì65536Ö0 +GPIO_PUPDR_PUPDR7Ì65536Ö0 +GPIO_PUPDR_PUPDR7_0Ì65536Ö0 +GPIO_PUPDR_PUPDR7_1Ì65536Ö0 +GPIO_PUPDR_PUPDR8Ì65536Ö0 +GPIO_PUPDR_PUPDR8_0Ì65536Ö0 +GPIO_PUPDR_PUPDR8_1Ì65536Ö0 +GPIO_PUPDR_PUPDR9Ì65536Ö0 +GPIO_PUPDR_PUPDR9_0Ì65536Ö0 +GPIO_PUPDR_PUPDR9_1Ì65536Ö0 +HIGH_SPEEDÌ4Îanon_enum_0Ö0 +HIGH_SPEEDÌ4Îanon_enum_2Ö0 +HIGH_SPEEDÌ4Îanon_enum_3Ö0 +HIGH_SPEEDÌ4Îanon_enum_4Ö0 +HIGH_SPEEDÌ4Îanon_enum_5Ö0 +I2C1Ì65536Ö0 +I2C1_BASEÌ65536Ö0 +I2CPINSÌ65536Ö0 +I2C_CR1_ADDRIEÌ65536Ö0 +I2C_CR1_ALERTENÌ65536Ö0 +I2C_CR1_ANFOFFÌ65536Ö0 +I2C_CR1_DFNÌ65536Ö0 +I2C_CR1_ERRIEÌ65536Ö0 +I2C_CR1_GCENÌ65536Ö0 +I2C_CR1_NACKIEÌ65536Ö0 +I2C_CR1_NOSTRETCHÌ65536Ö0 +I2C_CR1_PEÌ65536Ö0 +I2C_CR1_PECENÌ65536Ö0 +I2C_CR1_RXDMAENÌ65536Ö0 +I2C_CR1_RXIEÌ65536Ö0 +I2C_CR1_SBCÌ65536Ö0 +I2C_CR1_SMBDENÌ65536Ö0 +I2C_CR1_SMBHENÌ65536Ö0 +I2C_CR1_STOPIEÌ65536Ö0 +I2C_CR1_SWRSTÌ65536Ö0 +I2C_CR1_TCIEÌ65536Ö0 +I2C_CR1_TXDMAENÌ65536Ö0 +I2C_CR1_TXIEÌ65536Ö0 +I2C_CR1_WUPENÌ65536Ö0 +I2C_CR2_ADD10Ì65536Ö0 +I2C_CR2_AUTOENDÌ65536Ö0 +I2C_CR2_HEAD10RÌ65536Ö0 +I2C_CR2_NACKÌ65536Ö0 +I2C_CR2_NBYTESÌ65536Ö0 +I2C_CR2_PECBYTEÌ65536Ö0 +I2C_CR2_RD_WRNÌ65536Ö0 +I2C_CR2_RELOADÌ65536Ö0 +I2C_CR2_SADDÌ65536Ö0 +I2C_CR2_STARTÌ65536Ö0 +I2C_CR2_STOPÌ65536Ö0 +I2C_ICR_ADDRCFÌ65536Ö0 +I2C_ICR_ALERTCFÌ65536Ö0 +I2C_ICR_ARLOCFÌ65536Ö0 +I2C_ICR_BERRCFÌ65536Ö0 +I2C_ICR_NACKCFÌ65536Ö0 +I2C_ICR_OVRCFÌ65536Ö0 +I2C_ICR_PECCFÌ65536Ö0 +I2C_ICR_STOPCFÌ65536Ö0 +I2C_ICR_TIMOUTCFÌ65536Ö0 +I2C_ISR_ADDCODEÌ65536Ö0 +I2C_ISR_ADDRÌ65536Ö0 +I2C_ISR_ALERTÌ65536Ö0 +I2C_ISR_ARLOÌ65536Ö0 +I2C_ISR_BERRÌ65536Ö0 +I2C_ISR_BUSYÌ65536Ö0 +I2C_ISR_DIRÌ65536Ö0 +I2C_ISR_NACKFÌ65536Ö0 +I2C_ISR_OVRÌ65536Ö0 +I2C_ISR_PECERRÌ65536Ö0 +I2C_ISR_RXNEÌ65536Ö0 +I2C_ISR_STOPFÌ65536Ö0 +I2C_ISR_TCÌ65536Ö0 +I2C_ISR_TCRÌ65536Ö0 +I2C_ISR_TIMEOUTÌ65536Ö0 +I2C_ISR_TXEÌ65536Ö0 +I2C_ISR_TXISÌ65536Ö0 +I2C_OAR1_OA1Ì65536Ö0 +I2C_OAR1_OA1ENÌ65536Ö0 +I2C_OAR1_OA1MODEÌ65536Ö0 +I2C_OAR2_OA2Ì65536Ö0 +I2C_OAR2_OA2ENÌ65536Ö0 +I2C_OAR2_OA2MSKÌ65536Ö0 +I2C_PECR_PECÌ65536Ö0 +I2C_RXDR_RXDATAÌ65536Ö0 +I2C_SPEEDÌ4096Ö0Ïanon_enum_5 +I2C_TIMEOUTÌ65536Ö0 +I2C_TIMEOUTR_TEXTENÌ65536Ö0 +I2C_TIMEOUTR_TIDLEÌ65536Ö0 +I2C_TIMEOUTR_TIMEOUTAÌ65536Ö0 +I2C_TIMEOUTR_TIMEOUTBÌ65536Ö0 +I2C_TIMEOUTR_TIMOUTENÌ65536Ö0 +I2C_TIMINGR_PRESCÌ65536Ö0 +I2C_TIMINGR_SCLDELÌ65536Ö0 +I2C_TIMINGR_SCLHÌ65536Ö0 +I2C_TIMINGR_SCLLÌ65536Ö0 +I2C_TIMINGR_SDADELÌ65536Ö0 +I2C_TXDR_TXDATAÌ65536Ö0 +INT16_CÌ131072Í(c)Ö0 +INT16_MAXÌ65536Ö0 +INT16_MINÌ65536Ö0 +INT16_WIDTHÌ65536Ö0 +INT32_CÌ131072Í(c)Ö0 +INT32_MAXÌ65536Ö0 +INT32_MINÌ65536Ö0 +INT32_WIDTHÌ65536Ö0 +INT64_CÌ131072Í(c)Ö0 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+IS_CAN_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_CEC_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_CRC_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_DMA_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_FUNCTIONAL_STATEÌ131072Í(STATE)Ö0 +IS_GPIO_AF_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_GPIO_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_GPIO_LOCK_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_I2C_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_I2S_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_IRDA_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_IWDG_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_RTC_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_SMARTCARD_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_SMBUS_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_SPI_ALL_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_32B_COUNTER_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_BKIN2_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_BREAK_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CC1_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CC2_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CC3_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CC4_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CC5_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CC6_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CCXN_INSTANCEÌ131072Í(INSTANCE,CHANNEL)Ö0 +IS_TIM_CCX_INSTANCEÌ131072Í(INSTANCE,CHANNEL)Ö0 +IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CLOCKSOURCE_ITRX_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CLOCKSOURCE_TIX_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CLOCK_DIVISION_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_CLOCK_SELECT_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_COMMUTATION_EVENT_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_COUNTER_MODE_SELECT_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_DMABURST_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_DMA_CC_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_DMA_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_ENCODER_INTERFACE_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_HALL_INTERFACE_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_MASTER_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_OCXREF_CLEAR_INSTANCEÌ131072Í(INSTANCE)Ö0 +IS_TIM_REMAP_INSTANCEÌ131072Í(INSTANCE)Ö0 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+SYSCFG_EXTICR2_EXTI6Ì65536Ö0 +SYSCFG_EXTICR2_EXTI6_PAÌ65536Ö0 +SYSCFG_EXTICR2_EXTI6_PBÌ65536Ö0 +SYSCFG_EXTICR2_EXTI6_PCÌ65536Ö0 +SYSCFG_EXTICR2_EXTI6_PDÌ65536Ö0 +SYSCFG_EXTICR2_EXTI6_PEÌ65536Ö0 +SYSCFG_EXTICR2_EXTI6_PFÌ65536Ö0 +SYSCFG_EXTICR2_EXTI7Ì65536Ö0 +SYSCFG_EXTICR2_EXTI7_PAÌ65536Ö0 +SYSCFG_EXTICR2_EXTI7_PBÌ65536Ö0 +SYSCFG_EXTICR2_EXTI7_PCÌ65536Ö0 +SYSCFG_EXTICR2_EXTI7_PDÌ65536Ö0 +SYSCFG_EXTICR2_EXTI7_PEÌ65536Ö0 +SYSCFG_EXTICR2_EXTI7_PFÌ65536Ö0 +SYSCFG_EXTICR3_EXTI10Ì65536Ö0 +SYSCFG_EXTICR3_EXTI10_PAÌ65536Ö0 +SYSCFG_EXTICR3_EXTI10_PBÌ65536Ö0 +SYSCFG_EXTICR3_EXTI10_PCÌ65536Ö0 +SYSCFG_EXTICR3_EXTI10_PDÌ65536Ö0 +SYSCFG_EXTICR3_EXTI10_PEÌ65536Ö0 +SYSCFG_EXTICR3_EXTI10_PFÌ65536Ö0 +SYSCFG_EXTICR3_EXTI11Ì65536Ö0 +SYSCFG_EXTICR3_EXTI11_PAÌ65536Ö0 +SYSCFG_EXTICR3_EXTI11_PBÌ65536Ö0 +SYSCFG_EXTICR3_EXTI11_PCÌ65536Ö0 +SYSCFG_EXTICR3_EXTI11_PDÌ65536Ö0 +SYSCFG_EXTICR3_EXTI11_PEÌ65536Ö0 +SYSCFG_EXTICR3_EXTI8Ì65536Ö0 +SYSCFG_EXTICR3_EXTI8_PAÌ65536Ö0 +SYSCFG_EXTICR3_EXTI8_PBÌ65536Ö0 +SYSCFG_EXTICR3_EXTI8_PCÌ65536Ö0 +SYSCFG_EXTICR3_EXTI8_PDÌ65536Ö0 +SYSCFG_EXTICR3_EXTI8_PEÌ65536Ö0 +SYSCFG_EXTICR3_EXTI9Ì65536Ö0 +SYSCFG_EXTICR3_EXTI9_PAÌ65536Ö0 +SYSCFG_EXTICR3_EXTI9_PBÌ65536Ö0 +SYSCFG_EXTICR3_EXTI9_PCÌ65536Ö0 +SYSCFG_EXTICR3_EXTI9_PDÌ65536Ö0 +SYSCFG_EXTICR3_EXTI9_PEÌ65536Ö0 +SYSCFG_EXTICR3_EXTI9_PFÌ65536Ö0 +SYSCFG_EXTICR4_EXTI12Ì65536Ö0 +SYSCFG_EXTICR4_EXTI12_PAÌ65536Ö0 +SYSCFG_EXTICR4_EXTI12_PBÌ65536Ö0 +SYSCFG_EXTICR4_EXTI12_PCÌ65536Ö0 +SYSCFG_EXTICR4_EXTI12_PDÌ65536Ö0 +SYSCFG_EXTICR4_EXTI12_PEÌ65536Ö0 +SYSCFG_EXTICR4_EXTI13Ì65536Ö0 +SYSCFG_EXTICR4_EXTI13_PAÌ65536Ö0 +SYSCFG_EXTICR4_EXTI13_PBÌ65536Ö0 +SYSCFG_EXTICR4_EXTI13_PCÌ65536Ö0 +SYSCFG_EXTICR4_EXTI13_PDÌ65536Ö0 +SYSCFG_EXTICR4_EXTI13_PEÌ65536Ö0 +SYSCFG_EXTICR4_EXTI14Ì65536Ö0 +SYSCFG_EXTICR4_EXTI14_PAÌ65536Ö0 +SYSCFG_EXTICR4_EXTI14_PBÌ65536Ö0 +SYSCFG_EXTICR4_EXTI14_PCÌ65536Ö0 +SYSCFG_EXTICR4_EXTI14_PDÌ65536Ö0 +SYSCFG_EXTICR4_EXTI14_PEÌ65536Ö0 +SYSCFG_EXTICR4_EXTI15Ì65536Ö0 +SYSCFG_EXTICR4_EXTI15_PAÌ65536Ö0 +SYSCFG_EXTICR4_EXTI15_PBÌ65536Ö0 +SYSCFG_EXTICR4_EXTI15_PCÌ65536Ö0 +SYSCFG_EXTICR4_EXTI15_PDÌ65536Ö0 +SYSCFG_EXTICR4_EXTI15_PEÌ65536Ö0 +StartHSEÌ16Í()Ö0Ïinline void +StartHSI48Ì16Í()Ö0Ïinline void +SysTickÌ65536Ö0 +SysTick_BASEÌ65536Ö0 +SysTick_CALIB_NOREF_MskÌ65536Ö0 +SysTick_CALIB_NOREF_PosÌ65536Ö0 +SysTick_CALIB_SKEW_MskÌ65536Ö0 +SysTick_CALIB_SKEW_PosÌ65536Ö0 +SysTick_CALIB_TENMS_MskÌ65536Ö0 +SysTick_CALIB_TENMS_PosÌ65536Ö0 +SysTick_CTRL_CLKSOURCE_MskÌ65536Ö0 +SysTick_CTRL_CLKSOURCE_PosÌ65536Ö0 +SysTick_CTRL_COUNTFLAG_MskÌ65536Ö0 +SysTick_CTRL_COUNTFLAG_PosÌ65536Ö0 +SysTick_CTRL_ENABLE_MskÌ65536Ö0 +SysTick_CTRL_ENABLE_PosÌ65536Ö0 +SysTick_CTRL_TICKINT_MskÌ65536Ö0 +SysTick_CTRL_TICKINT_PosÌ65536Ö0 +SysTick_LOAD_RELOAD_MskÌ65536Ö0 +SysTick_LOAD_RELOAD_PosÌ65536Ö0 +SysTick_VAL_CURRENT_MskÌ65536Ö0 +SysTick_VAL_CURRENT_PosÌ65536Ö0 +TEMP110_CAL_ADDRÌ65536Ö0 +TEMP30_CAL_ADDRÌ65536Ö0 +TIM1Ì65536Ö0 +TIM14Ì65536Ö0 +TIM14_BASEÌ65536Ö0 +TIM14_OR_TI1_RMPÌ65536Ö0 +TIM14_OR_TI1_RMP_0Ì65536Ö0 +TIM14_OR_TI1_RMP_1Ì65536Ö0 +TIM16Ì65536Ö0 +TIM16_BASEÌ65536Ö0 +TIM17Ì65536Ö0 +TIM17_BASEÌ65536Ö0 +TIM1_BASEÌ65536Ö0 +TIM2Ì65536Ö0 +TIM2_BASEÌ65536Ö0 +TIM3Ì65536Ö0 +TIM3_BASEÌ65536Ö0 +TIMEOUT_MSÌ65536Ö0 +TIM_ARR_ARRÌ65536Ö0 +TIM_BDTR_AOEÌ65536Ö0 +TIM_BDTR_BKEÌ65536Ö0 +TIM_BDTR_BKPÌ65536Ö0 +TIM_BDTR_DTGÌ65536Ö0 +TIM_BDTR_DTG_0Ì65536Ö0 +TIM_BDTR_DTG_1Ì65536Ö0 +TIM_BDTR_DTG_2Ì65536Ö0 +TIM_BDTR_DTG_3Ì65536Ö0 +TIM_BDTR_DTG_4Ì65536Ö0 +TIM_BDTR_DTG_5Ì65536Ö0 +TIM_BDTR_DTG_6Ì65536Ö0 +TIM_BDTR_DTG_7Ì65536Ö0 +TIM_BDTR_LOCKÌ65536Ö0 +TIM_BDTR_LOCK_0Ì65536Ö0 +TIM_BDTR_LOCK_1Ì65536Ö0 +TIM_BDTR_MOEÌ65536Ö0 +TIM_BDTR_OSSIÌ65536Ö0 +TIM_BDTR_OSSRÌ65536Ö0 +TIM_CCER_CC1EÌ65536Ö0 +TIM_CCER_CC1NEÌ65536Ö0 +TIM_CCER_CC1NPÌ65536Ö0 +TIM_CCER_CC1PÌ65536Ö0 +TIM_CCER_CC2EÌ65536Ö0 +TIM_CCER_CC2NEÌ65536Ö0 +TIM_CCER_CC2NPÌ65536Ö0 +TIM_CCER_CC2PÌ65536Ö0 +TIM_CCER_CC3EÌ65536Ö0 +TIM_CCER_CC3NEÌ65536Ö0 +TIM_CCER_CC3NPÌ65536Ö0 +TIM_CCER_CC3PÌ65536Ö0 +TIM_CCER_CC4EÌ65536Ö0 +TIM_CCER_CC4NPÌ65536Ö0 +TIM_CCER_CC4PÌ65536Ö0 +TIM_CCMR1_CC1SÌ65536Ö0 +TIM_CCMR1_CC1S_0Ì65536Ö0 +TIM_CCMR1_CC1S_1Ì65536Ö0 +TIM_CCMR1_CC2SÌ65536Ö0 +TIM_CCMR1_CC2S_0Ì65536Ö0 +TIM_CCMR1_CC2S_1Ì65536Ö0 +TIM_CCMR1_IC1FÌ65536Ö0 +TIM_CCMR1_IC1F_0Ì65536Ö0 +TIM_CCMR1_IC1F_1Ì65536Ö0 +TIM_CCMR1_IC1F_2Ì65536Ö0 +TIM_CCMR1_IC1F_3Ì65536Ö0 +TIM_CCMR1_IC1PSCÌ65536Ö0 +TIM_CCMR1_IC1PSC_0Ì65536Ö0 +TIM_CCMR1_IC1PSC_1Ì65536Ö0 +TIM_CCMR1_IC2FÌ65536Ö0 +TIM_CCMR1_IC2F_0Ì65536Ö0 +TIM_CCMR1_IC2F_1Ì65536Ö0 +TIM_CCMR1_IC2F_2Ì65536Ö0 +TIM_CCMR1_IC2F_3Ì65536Ö0 +TIM_CCMR1_IC2PSCÌ65536Ö0 +TIM_CCMR1_IC2PSC_0Ì65536Ö0 +TIM_CCMR1_IC2PSC_1Ì65536Ö0 +TIM_CCMR1_OC1CEÌ65536Ö0 +TIM_CCMR1_OC1FEÌ65536Ö0 +TIM_CCMR1_OC1MÌ65536Ö0 +TIM_CCMR1_OC1M_0Ì65536Ö0 +TIM_CCMR1_OC1M_1Ì65536Ö0 +TIM_CCMR1_OC1M_2Ì65536Ö0 +TIM_CCMR1_OC1PEÌ65536Ö0 +TIM_CCMR1_OC2CEÌ65536Ö0 +TIM_CCMR1_OC2FEÌ65536Ö0 +TIM_CCMR1_OC2MÌ65536Ö0 +TIM_CCMR1_OC2M_0Ì65536Ö0 +TIM_CCMR1_OC2M_1Ì65536Ö0 +TIM_CCMR1_OC2M_2Ì65536Ö0 +TIM_CCMR1_OC2PEÌ65536Ö0 +TIM_CCMR2_CC3SÌ65536Ö0 +TIM_CCMR2_CC3S_0Ì65536Ö0 +TIM_CCMR2_CC3S_1Ì65536Ö0 +TIM_CCMR2_CC4SÌ65536Ö0 +TIM_CCMR2_CC4S_0Ì65536Ö0 +TIM_CCMR2_CC4S_1Ì65536Ö0 +TIM_CCMR2_IC3FÌ65536Ö0 +TIM_CCMR2_IC3F_0Ì65536Ö0 +TIM_CCMR2_IC3F_1Ì65536Ö0 +TIM_CCMR2_IC3F_2Ì65536Ö0 +TIM_CCMR2_IC3F_3Ì65536Ö0 +TIM_CCMR2_IC3PSCÌ65536Ö0 +TIM_CCMR2_IC3PSC_0Ì65536Ö0 +TIM_CCMR2_IC3PSC_1Ì65536Ö0 +TIM_CCMR2_IC4FÌ65536Ö0 +TIM_CCMR2_IC4F_0Ì65536Ö0 +TIM_CCMR2_IC4F_1Ì65536Ö0 +TIM_CCMR2_IC4F_2Ì65536Ö0 +TIM_CCMR2_IC4F_3Ì65536Ö0 +TIM_CCMR2_IC4PSCÌ65536Ö0 +TIM_CCMR2_IC4PSC_0Ì65536Ö0 +TIM_CCMR2_IC4PSC_1Ì65536Ö0 +TIM_CCMR2_OC3CEÌ65536Ö0 +TIM_CCMR2_OC3FEÌ65536Ö0 +TIM_CCMR2_OC3MÌ65536Ö0 +TIM_CCMR2_OC3M_0Ì65536Ö0 +TIM_CCMR2_OC3M_1Ì65536Ö0 +TIM_CCMR2_OC3M_2Ì65536Ö0 +TIM_CCMR2_OC3PEÌ65536Ö0 +TIM_CCMR2_OC4CEÌ65536Ö0 +TIM_CCMR2_OC4FEÌ65536Ö0 +TIM_CCMR2_OC4MÌ65536Ö0 +TIM_CCMR2_OC4M_0Ì65536Ö0 +TIM_CCMR2_OC4M_1Ì65536Ö0 +TIM_CCMR2_OC4M_2Ì65536Ö0 +TIM_CCMR2_OC4PEÌ65536Ö0 +TIM_CCR1_CCR1Ì65536Ö0 +TIM_CCR2_CCR2Ì65536Ö0 +TIM_CCR3_CCR3Ì65536Ö0 +TIM_CCR4_CCR4Ì65536Ö0 +TIM_CNT_CNTÌ65536Ö0 +TIM_CR1_ARPEÌ65536Ö0 +TIM_CR1_CENÌ65536Ö0 +TIM_CR1_CKDÌ65536Ö0 +TIM_CR1_CKD_0Ì65536Ö0 +TIM_CR1_CKD_1Ì65536Ö0 +TIM_CR1_CMSÌ65536Ö0 +TIM_CR1_CMS_0Ì65536Ö0 +TIM_CR1_CMS_1Ì65536Ö0 +TIM_CR1_DIRÌ65536Ö0 +TIM_CR1_OPMÌ65536Ö0 +TIM_CR1_UDISÌ65536Ö0 +TIM_CR1_URSÌ65536Ö0 +TIM_CR2_CCDSÌ65536Ö0 +TIM_CR2_CCPCÌ65536Ö0 +TIM_CR2_CCUSÌ65536Ö0 +TIM_CR2_MMSÌ65536Ö0 +TIM_CR2_MMS_0Ì65536Ö0 +TIM_CR2_MMS_1Ì65536Ö0 +TIM_CR2_MMS_2Ì65536Ö0 +TIM_CR2_OIS1Ì65536Ö0 +TIM_CR2_OIS1NÌ65536Ö0 +TIM_CR2_OIS2Ì65536Ö0 +TIM_CR2_OIS2NÌ65536Ö0 +TIM_CR2_OIS3Ì65536Ö0 +TIM_CR2_OIS3NÌ65536Ö0 +TIM_CR2_OIS4Ì65536Ö0 +TIM_CR2_TI1SÌ65536Ö0 +TIM_DCR_DBAÌ65536Ö0 +TIM_DCR_DBA_0Ì65536Ö0 +TIM_DCR_DBA_1Ì65536Ö0 +TIM_DCR_DBA_2Ì65536Ö0 +TIM_DCR_DBA_3Ì65536Ö0 +TIM_DCR_DBA_4Ì65536Ö0 +TIM_DCR_DBLÌ65536Ö0 +TIM_DCR_DBL_0Ì65536Ö0 +TIM_DCR_DBL_1Ì65536Ö0 +TIM_DCR_DBL_2Ì65536Ö0 +TIM_DCR_DBL_3Ì65536Ö0 +TIM_DCR_DBL_4Ì65536Ö0 +TIM_DIER_BIEÌ65536Ö0 +TIM_DIER_CC1DEÌ65536Ö0 +TIM_DIER_CC1IEÌ65536Ö0 +TIM_DIER_CC2DEÌ65536Ö0 +TIM_DIER_CC2IEÌ65536Ö0 +TIM_DIER_CC3DEÌ65536Ö0 +TIM_DIER_CC3IEÌ65536Ö0 +TIM_DIER_CC4DEÌ65536Ö0 +TIM_DIER_CC4IEÌ65536Ö0 +TIM_DIER_COMDEÌ65536Ö0 +TIM_DIER_COMIEÌ65536Ö0 +TIM_DIER_TDEÌ65536Ö0 +TIM_DIER_TIEÌ65536Ö0 +TIM_DIER_UDEÌ65536Ö0 +TIM_DIER_UIEÌ65536Ö0 +TIM_DMAR_DMABÌ65536Ö0 +TIM_EGR_BGÌ65536Ö0 +TIM_EGR_CC1GÌ65536Ö0 +TIM_EGR_CC2GÌ65536Ö0 +TIM_EGR_CC3GÌ65536Ö0 +TIM_EGR_CC4GÌ65536Ö0 +TIM_EGR_COMGÌ65536Ö0 +TIM_EGR_TGÌ65536Ö0 +TIM_EGR_UGÌ65536Ö0 +TIM_PSC_PSCÌ65536Ö0 +TIM_RCR_REPÌ65536Ö0 +TIM_SMCR_ECEÌ65536Ö0 +TIM_SMCR_ETFÌ65536Ö0 +TIM_SMCR_ETF_0Ì65536Ö0 +TIM_SMCR_ETF_1Ì65536Ö0 +TIM_SMCR_ETF_2Ì65536Ö0 +TIM_SMCR_ETF_3Ì65536Ö0 +TIM_SMCR_ETPÌ65536Ö0 +TIM_SMCR_ETPSÌ65536Ö0 +TIM_SMCR_ETPS_0Ì65536Ö0 +TIM_SMCR_ETPS_1Ì65536Ö0 +TIM_SMCR_MSMÌ65536Ö0 +TIM_SMCR_OCCSÌ65536Ö0 +TIM_SMCR_SMSÌ65536Ö0 +TIM_SMCR_SMS_0Ì65536Ö0 +TIM_SMCR_SMS_1Ì65536Ö0 +TIM_SMCR_SMS_2Ì65536Ö0 +TIM_SMCR_TSÌ65536Ö0 +TIM_SMCR_TS_0Ì65536Ö0 +TIM_SMCR_TS_1Ì65536Ö0 +TIM_SMCR_TS_2Ì65536Ö0 +TIM_SR_BIFÌ65536Ö0 +TIM_SR_CC1IFÌ65536Ö0 +TIM_SR_CC1OFÌ65536Ö0 +TIM_SR_CC2IFÌ65536Ö0 +TIM_SR_CC2OFÌ65536Ö0 +TIM_SR_CC3IFÌ65536Ö0 +TIM_SR_CC3OFÌ65536Ö0 +TIM_SR_CC4IFÌ65536Ö0 +TIM_SR_CC4OFÌ65536Ö0 +TIM_SR_COMIFÌ65536Ö0 +TIM_SR_TIFÌ65536Ö0 +TIM_SR_UIFÌ65536Ö0 +TRUE_INLINEÌ65536Ö0 +TSCÌ65536Ö0 +TSC_BASEÌ65536Ö0 +TSC_CR_AMÌ65536Ö0 +TSC_CR_CTPHÌ65536Ö0 +TSC_CR_CTPH_0Ì65536Ö0 +TSC_CR_CTPH_1Ì65536Ö0 +TSC_CR_CTPH_2Ì65536Ö0 +TSC_CR_CTPH_3Ì65536Ö0 +TSC_CR_CTPLÌ65536Ö0 +TSC_CR_CTPL_0Ì65536Ö0 +TSC_CR_CTPL_1Ì65536Ö0 +TSC_CR_CTPL_2Ì65536Ö0 +TSC_CR_CTPL_3Ì65536Ö0 +TSC_CR_IODEFÌ65536Ö0 +TSC_CR_MCVÌ65536Ö0 +TSC_CR_MCV_0Ì65536Ö0 +TSC_CR_MCV_1Ì65536Ö0 +TSC_CR_MCV_2Ì65536Ö0 +TSC_CR_PGPSCÌ65536Ö0 +TSC_CR_PGPSC_0Ì65536Ö0 +TSC_CR_PGPSC_1Ì65536Ö0 +TSC_CR_PGPSC_2Ì65536Ö0 +TSC_CR_SSDÌ65536Ö0 +TSC_CR_SSD_0Ì65536Ö0 +TSC_CR_SSD_1Ì65536Ö0 +TSC_CR_SSD_2Ì65536Ö0 +TSC_CR_SSD_3Ì65536Ö0 +TSC_CR_SSD_4Ì65536Ö0 +TSC_CR_SSD_5Ì65536Ö0 +TSC_CR_SSD_6Ì65536Ö0 +TSC_CR_SSEÌ65536Ö0 +TSC_CR_SSPSCÌ65536Ö0 +TSC_CR_STARTÌ65536Ö0 +TSC_CR_SYNCPOLÌ65536Ö0 +TSC_CR_TSCEÌ65536Ö0 +TSC_ICR_EOAICÌ65536Ö0 +TSC_ICR_MCEICÌ65536Ö0 +TSC_IER_EOAIEÌ65536Ö0 +TSC_IER_MCEIEÌ65536Ö0 +TSC_IOASCR_G1_IO1Ì65536Ö0 +TSC_IOASCR_G1_IO2Ì65536Ö0 +TSC_IOASCR_G1_IO3Ì65536Ö0 +TSC_IOASCR_G1_IO4Ì65536Ö0 +TSC_IOASCR_G2_IO1Ì65536Ö0 +TSC_IOASCR_G2_IO2Ì65536Ö0 +TSC_IOASCR_G2_IO3Ì65536Ö0 +TSC_IOASCR_G2_IO4Ì65536Ö0 +TSC_IOASCR_G3_IO1Ì65536Ö0 +TSC_IOASCR_G3_IO2Ì65536Ö0 +TSC_IOASCR_G3_IO3Ì65536Ö0 +TSC_IOASCR_G3_IO4Ì65536Ö0 +TSC_IOASCR_G4_IO1Ì65536Ö0 +TSC_IOASCR_G4_IO2Ì65536Ö0 +TSC_IOASCR_G4_IO3Ì65536Ö0 +TSC_IOASCR_G4_IO4Ì65536Ö0 +TSC_IOASCR_G5_IO1Ì65536Ö0 +TSC_IOASCR_G5_IO2Ì65536Ö0 +TSC_IOASCR_G5_IO3Ì65536Ö0 +TSC_IOASCR_G5_IO4Ì65536Ö0 +TSC_IOASCR_G6_IO1Ì65536Ö0 +TSC_IOASCR_G6_IO2Ì65536Ö0 +TSC_IOASCR_G6_IO3Ì65536Ö0 +TSC_IOASCR_G6_IO4Ì65536Ö0 +TSC_IOASCR_G7_IO1Ì65536Ö0 +TSC_IOASCR_G7_IO2Ì65536Ö0 +TSC_IOASCR_G7_IO3Ì65536Ö0 +TSC_IOASCR_G7_IO4Ì65536Ö0 +TSC_IOASCR_G8_IO1Ì65536Ö0 +TSC_IOASCR_G8_IO2Ì65536Ö0 +TSC_IOASCR_G8_IO3Ì65536Ö0 +TSC_IOASCR_G8_IO4Ì65536Ö0 +TSC_IOCCR_G1_IO1Ì65536Ö0 +TSC_IOCCR_G1_IO2Ì65536Ö0 +TSC_IOCCR_G1_IO3Ì65536Ö0 +TSC_IOCCR_G1_IO4Ì65536Ö0 +TSC_IOCCR_G2_IO1Ì65536Ö0 +TSC_IOCCR_G2_IO2Ì65536Ö0 +TSC_IOCCR_G2_IO3Ì65536Ö0 +TSC_IOCCR_G2_IO4Ì65536Ö0 +TSC_IOCCR_G3_IO1Ì65536Ö0 +TSC_IOCCR_G3_IO2Ì65536Ö0 +TSC_IOCCR_G3_IO3Ì65536Ö0 +TSC_IOCCR_G3_IO4Ì65536Ö0 +TSC_IOCCR_G4_IO1Ì65536Ö0 +TSC_IOCCR_G4_IO2Ì65536Ö0 +TSC_IOCCR_G4_IO3Ì65536Ö0 +TSC_IOCCR_G4_IO4Ì65536Ö0 +TSC_IOCCR_G5_IO1Ì65536Ö0 +TSC_IOCCR_G5_IO2Ì65536Ö0 +TSC_IOCCR_G5_IO3Ì65536Ö0 +TSC_IOCCR_G5_IO4Ì65536Ö0 +TSC_IOCCR_G6_IO1Ì65536Ö0 +TSC_IOCCR_G6_IO2Ì65536Ö0 +TSC_IOCCR_G6_IO3Ì65536Ö0 +TSC_IOCCR_G6_IO4Ì65536Ö0 +TSC_IOCCR_G7_IO1Ì65536Ö0 +TSC_IOCCR_G7_IO2Ì65536Ö0 +TSC_IOCCR_G7_IO3Ì65536Ö0 +TSC_IOCCR_G7_IO4Ì65536Ö0 +TSC_IOCCR_G8_IO1Ì65536Ö0 +TSC_IOCCR_G8_IO2Ì65536Ö0 +TSC_IOCCR_G8_IO3Ì65536Ö0 +TSC_IOCCR_G8_IO4Ì65536Ö0 +TSC_IOGCSR_G1EÌ65536Ö0 +TSC_IOGCSR_G1SÌ65536Ö0 +TSC_IOGCSR_G2EÌ65536Ö0 +TSC_IOGCSR_G2SÌ65536Ö0 +TSC_IOGCSR_G3EÌ65536Ö0 +TSC_IOGCSR_G3SÌ65536Ö0 +TSC_IOGCSR_G4EÌ65536Ö0 +TSC_IOGCSR_G4SÌ65536Ö0 +TSC_IOGCSR_G5EÌ65536Ö0 +TSC_IOGCSR_G5SÌ65536Ö0 +TSC_IOGCSR_G6EÌ65536Ö0 +TSC_IOGCSR_G6SÌ65536Ö0 +TSC_IOGCSR_G7EÌ65536Ö0 +TSC_IOGCSR_G7SÌ65536Ö0 +TSC_IOGCSR_G8EÌ65536Ö0 +TSC_IOGCSR_G8SÌ65536Ö0 +TSC_IOGXCR_CNTÌ65536Ö0 +TSC_IOHCR_G1_IO1Ì65536Ö0 +TSC_IOHCR_G1_IO2Ì65536Ö0 +TSC_IOHCR_G1_IO3Ì65536Ö0 +TSC_IOHCR_G1_IO4Ì65536Ö0 +TSC_IOHCR_G2_IO1Ì65536Ö0 +TSC_IOHCR_G2_IO2Ì65536Ö0 +TSC_IOHCR_G2_IO3Ì65536Ö0 +TSC_IOHCR_G2_IO4Ì65536Ö0 +TSC_IOHCR_G3_IO1Ì65536Ö0 +TSC_IOHCR_G3_IO2Ì65536Ö0 +TSC_IOHCR_G3_IO3Ì65536Ö0 +TSC_IOHCR_G3_IO4Ì65536Ö0 +TSC_IOHCR_G4_IO1Ì65536Ö0 +TSC_IOHCR_G4_IO2Ì65536Ö0 +TSC_IOHCR_G4_IO3Ì65536Ö0 +TSC_IOHCR_G4_IO4Ì65536Ö0 +TSC_IOHCR_G5_IO1Ì65536Ö0 +TSC_IOHCR_G5_IO2Ì65536Ö0 +TSC_IOHCR_G5_IO3Ì65536Ö0 +TSC_IOHCR_G5_IO4Ì65536Ö0 +TSC_IOHCR_G6_IO1Ì65536Ö0 +TSC_IOHCR_G6_IO2Ì65536Ö0 +TSC_IOHCR_G6_IO3Ì65536Ö0 +TSC_IOHCR_G6_IO4Ì65536Ö0 +TSC_IOHCR_G7_IO1Ì65536Ö0 +TSC_IOHCR_G7_IO2Ì65536Ö0 +TSC_IOHCR_G7_IO3Ì65536Ö0 +TSC_IOHCR_G7_IO4Ì65536Ö0 +TSC_IOHCR_G8_IO1Ì65536Ö0 +TSC_IOHCR_G8_IO2Ì65536Ö0 +TSC_IOHCR_G8_IO3Ì65536Ö0 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+linuxÌ65536Ö0 +mainÌ16Í(void)Ö0Ïint +newlineÌ16Í()Ö0Ïvoid +newlineÌ1024Í()Ö0Ïvoid +nopÌ131072Í()Ö0 +pin_clearÌ131072Í(gpioport,gpios)Ö0 +pin_readÌ131072Í(gpioport,gpios)Ö0 +pin_setÌ131072Í(gpioport,gpios)Ö0 +pin_toggleÌ131072Í(gpioport,gpios)Ö0 +pin_writeÌ131072Í(gpioport,gpios)Ö0 +printuÌ16Í(uint32_t val)Ö0Ïvoid +rbufÌ16384Ö0Ïchar +rbufnoÌ16384Ö0Ïint +read_i2cÌ16Í(uint8_t addr, uint32_t *data, uint8_t nbytes)Ö0Ïuint8_t +read_i2cÌ1024Í(uint8_t addr, uint32_t *data, uint8_t nbytes)Ö0Ïuint8_t +recvdataÌ16384Ö0Ïchar * +showcoeffsÌ16Í(uint8_t addr, uint8_t verb)Ö0Ïvoid +strdupaÌ131072Í(s)Ö0 +strndupaÌ131072Í(s,n)Ö0 +sys_tick_handlerÌ16Í(void)Ö0Ïvoid +sysresetÌ16Í(void)Ö0Ïinline void +tbufÌ16384Ö0Ïchar +txrdyÌ16384Ö0Ïint +txrdyÌ32768Ö0Ïint +unixÌ65536Ö0 +usart1_isrÌ16Í()Ö0Ïvoid +usart_getlineÌ16Í(char **line)Ö0Ïint +usart_getlineÌ1024Í(char **line)Ö0Ïint +usart_sendÌ16Í(const char *str, int len)Ö0ÏTXstatus +usart_sendÌ1024Í(const char *str, int len)Ö0ÏTXstatus +usart_send_blockingÌ16Í(const char *str, int len)Ö0ÏTXstatus +usart_send_blockingÌ1024Í(const char *str, int len)Ö0ÏTXstatus +usart_setupÌ16Í()Ö0Ïvoid +usart_setupÌ1024Í()Ö0Ïvoid +usartovrÌ131072Í()Ö0 +usartrxÌ131072Í()Ö0 +write_i2cÌ16Í(uint8_t addr, uint8_t data)Ö0Ïuint8_t +write_i2cÌ1024Í(uint8_t addr, uint8_t data)Ö0Ïuint8_t diff --git a/STM32/TSYS_controller/tsys01.geany b/STM32/TSYS_controller/tsys01.geany new file mode 100644 index 0000000..4c15574 --- /dev/null +++ b/STM32/TSYS_controller/tsys01.geany @@ -0,0 +1,33 @@ +[editor] +line_wrapping=false +line_break_column=100 +auto_continue_multiline=true + +[file_prefs] +final_new_line=true +ensure_convert_new_lines=true +strip_trailing_spaces=true +replace_tabs=true + +[indentation] +indent_width=4 +indent_type=0 +indent_hard_tab_width=4 +detect_indent=false +detect_indent_width=false +indent_mode=3 + +[project] +name=tsys01 +base_path=/home/eddy/Docs/SAO/BTA/Зеркало_контроль/Project/STM32src/TSYS_controller +description= + +[long line marker] +long_line_behaviour=1 +long_line_column=100 + +[files] +current_page=-1 + +[VTE] +last_dir=/home/eddy diff --git a/STM32/TSYS_controller/usart.c b/STM32/TSYS_controller/usart.c new file mode 100644 index 0000000..5ab9c7f --- /dev/null +++ b/STM32/TSYS_controller/usart.c @@ -0,0 +1,238 @@ +/*us + * usart.c + * + * Copyright 2017 Edward V. Emelianoff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include "stm32f0.h" +#include "hardware.h" +#include "usart.h" +#include + +extern volatile uint32_t Tms; +static int datalen[2] = {0,0}; // received data line length (including '\n') + +int linerdy = 0, // received data ready + dlen = 0, // length of data (including '\n') in current buffer + bufovr = 0, // input buffer overfull + txrdy = 1 // transmission done +; + + +int rbufno = 0; // current rbuf number +static char rbuf[UARTBUFSZ][2], tbuf[UARTBUFSZ]; // receive & transmit buffers +static char *recvdata = NULL; + +/** + * return length of received data (without trailing zero + */ +int usart_getline(char **line){ + if(bufovr){ + bufovr = 0; + linerdy = 0; + return 0; + } + *line = recvdata; + linerdy = 0; + return dlen; +} + +TXstatus usart_send(const char *str, int len){ + if(!txrdy) return LINE_BUSY; + if(len > UARTBUFSZ) return STR_TOO_LONG; + txrdy = 0; + memcpy(tbuf, str, len); +#if USARTNUM == 2 + DMA1_Channel4->CCR &= ~DMA_CCR_EN; + DMA1_Channel4->CNDTR = len; + DMA1_Channel4->CCR |= DMA_CCR_EN; // start transmission +#elif USARTNUM == 1 + DMA1_Channel2->CCR &= ~DMA_CCR_EN; + DMA1_Channel2->CNDTR = len; + DMA1_Channel2->CCR |= DMA_CCR_EN; +#else +#error "Not implemented" +#endif + return ALL_OK; +} + +TXstatus usart_send_blocking(const char *str, int len){ + if(!txrdy) return LINE_BUSY; + int i; + bufovr = 0; + for(i = 0; i < len; ++i){ + USARTX -> TDR = *str++; + while(!(USARTX->ISR & USART_ISR_TXE)); + } + return ALL_OK; +} + +void usart_putchar(const char ch){ + while(!txrdy); + USARTX -> TDR = ch; + while(!(USARTX->ISR & USART_ISR_TXE)); +} + +void newline(){ + while(!txrdy); + USARTX -> TDR = '\n'; + while(!(USARTX->ISR & USART_ISR_TXE)); +} + + +void usart_setup(){ +// Nucleo's USART2 connected to VCP proxy of st-link +#if USARTNUM == 2 + // setup pins: PA2 (Tx - AF1), PA15 (Rx - AF1) + // AF mode (AF1) + GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER2|GPIO_MODER_MODER15))\ + | (GPIO_MODER_MODER2_AF | GPIO_MODER_MODER15_AF); + GPIOA->AFR[0] = (GPIOA->AFR[0] &~GPIO_AFRH_AFRH2) | 1 << (2 * 4); // PA2 + GPIOA->AFR[1] = (GPIOA->AFR[1] &~GPIO_AFRH_AFRH7) | 1 << (7 * 4); // PA15 + // DMA: Tx - Ch4 + DMA1_Channel4->CPAR = (uint32_t) &USART2->TDR; // periph + DMA1_Channel4->CMAR = (uint32_t) tbuf; // mem + DMA1_Channel4->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq + // Tx CNDTR set @ each transmission due to data size + NVIC_SetPriority(DMA1_Channel4_5_IRQn, 3); + NVIC_EnableIRQ(DMA1_Channel4_5_IRQn); + NVIC_SetPriority(USART2_IRQn, 0); + // setup usart2 + RCC->APB1ENR |= RCC_APB1ENR_USART2EN; // clock + // oversampling by16, 115200bps (fck=48mHz) + //USART2_BRR = 0x1a1; // 48000000 / 115200 + USART2->BRR = 480000 / 1152; + USART2->CR3 = USART_CR3_DMAT; // enable DMA Tx + USART2->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART + while(!(USART2->ISR & USART_ISR_TC)); // polling idle frame Transmission + USART2->ICR |= USART_ICR_TCCF; // clear TC flag + USART2->CR1 |= USART_CR1_RXNEIE; + NVIC_EnableIRQ(USART2_IRQn); +// USART1 of main board +#elif USARTNUM == 1 + // PA9 - Tx, PA10 - Rx (AF1) + GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER9 | GPIO_MODER_MODER10))\ + | (GPIO_MODER_MODER9_AF | GPIO_MODER_MODER10_AF); + GPIOA->AFR[1] = (GPIOA->AFR[1] & ~(GPIO_AFRH_AFRH1 | GPIO_AFRH_AFRH2)) | + 1 << (1 * 4) | 1 << (2 * 4); // PA9, PA10 + // USART1 Tx DMA - Channel2 (default value in SYSCFG_CFGR1) + DMA1_Channel2->CPAR = (uint32_t) &USART1->TDR; // periph + DMA1_Channel2->CMAR = (uint32_t) tbuf; // mem + DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq + // Tx CNDTR set @ each transmission due to data size + NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3); + NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + NVIC_SetPriority(USART1_IRQn, 0); + // setup usart1 + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + USART1->BRR = 480000 / 1152; + USART1->CR3 = USART_CR3_DMAT; // enable DMA Tx + USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART + while(!(USART1->ISR & USART_ISR_TC)); // polling idle frame Transmission + USART1->ICR |= USART_ICR_TCCF; // clear TC flag + USART1->CR1 |= USART_CR1_RXNEIE; + NVIC_EnableIRQ(USART1_IRQn); +#else +#error "Not implemented" +#endif +} + +#if USARTNUM == 2 +void usart2_isr(){ +// USART1 +#elif USARTNUM == 1 +void usart1_isr(){ +#else +#error "Not implemented" +#endif + #ifdef CHECK_TMOUT + static uint32_t tmout = 0; + #endif + if(USARTX->ISR & USART_ISR_RXNE){ // RX not emty - receive next char + #ifdef CHECK_TMOUT + if(tmout && Tms >= tmout){ // set overflow flag + bufovr = 1; + datalen[rbufno] = 0; + } + tmout = Tms + TIMEOUT_MS; + if(!tmout) tmout = 1; // prevent 0 + #endif + // read RDR clears flag + uint8_t rb = USARTX->RDR; + if(datalen[rbufno] < UARTBUFSZ){ // put next char into buf + rbuf[rbufno][datalen[rbufno]++] = rb; + if(rb == '\n'){ // got newline - line ready + linerdy = 1; + dlen = datalen[rbufno]; + recvdata = rbuf[rbufno]; + // prepare other buffer + rbufno = !rbufno; + datalen[rbufno] = 0; + #ifdef CHECK_TMOUT + // clear timeout at line end + tmout = 0; + #endif + } + }else{ // buffer overrun + bufovr = 1; + datalen[rbufno] = 0; + #ifdef CHECK_TMOUT + tmout = 0; + #endif + } + } +} + +// print 32bit unsigned int +void printu(uint32_t val){ + char bufa[11], bufb[10]; + int l = 0, bpos = 0; + if(!val){ + bufa[0] = '0'; + l = 1; + }else{ + while(val){ + bufb[l++] = val % 10 + '0'; + val /= 10; + } + int i; + bpos += l; + for(i = 0; i < l; ++i){ + bufa[--bpos] = bufb[i]; + } + } + while(LINE_BUSY == usart_send_blocking(bufa, l+bpos)); +} + +#if USARTNUM == 2 +void dma1_channel4_5_isr(){ + if(DMA1->ISR & DMA_ISR_TCIF4){ // Tx + DMA1->IFCR |= DMA_IFCR_CTCIF4; // clear TC flag + txrdy = 1; + } +} +// USART1 +#elif USARTNUM == 1 +void dma1_channel2_3_isr(){ + if(DMA1->ISR & DMA_ISR_TCIF2){ // Tx + DMA1->IFCR |= DMA_IFCR_CTCIF2; // clear TC flag + txrdy = 1; + } +} +#else +#error "Not implemented" +#endif diff --git a/STM32/TSYS_controller/usart.h b/STM32/TSYS_controller/usart.h new file mode 100644 index 0000000..9d6165d --- /dev/null +++ b/STM32/TSYS_controller/usart.h @@ -0,0 +1,55 @@ +/* + * usart.h + * + * Copyright 2017 Edward V. Emelianoff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#pragma once +#ifndef __USART_H__ +#define __USART_H__ + +// input and output buffers size +#define UARTBUFSZ (64) +// timeout between data bytes +#ifndef TIMEOUT_MS +#define TIMEOUT_MS (1500) +#endif + +// macro for static strings +#define SEND(str) do{}while(LINE_BUSY == usart_send_blocking(str, sizeof(str)-1)) +#define NEWLINE() do{}while(LINE_BUSY == usart_send_blocking('\n', 1)) + +typedef enum{ + ALL_OK, + LINE_BUSY, + STR_TOO_LONG +} TXstatus; + +#define usartrx() (linerdy) +#define usartovr() (bufovr) + +extern int linerdy, bufovr, txrdy; + +void usart_setup(); +int usart_getline(char **line); +TXstatus usart_send(const char *str, int len); +TXstatus usart_send_blocking(const char *str, int len); +void newline(); +void usart_putchar(const char ch); +void printu(uint32_t val); + +#endif // __USART_H__