initial commit

STM32/inc/startup/vector.c

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+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>,
+ * Copyright (C) 2012 chrysn <chrysn@fsfe.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "stm32f0xx.h"
+
+/* Initialization template for the interrupt vector table. This definition is
+ * used by the startup code generator (vector.c) to set the initial values for
+ * the interrupt handling routines to the chip family specific _isr weak
+ * symbols. */
+#define NVIC_IRQ_COUNT 32
+
+#define F0_IRQ_HANDLERS \
+    wwdg_isr, \
+    pvd_isr, \
+    rtc_isr, \
+    flash_isr, \
+    rcc_isr, \
+    exti0_1_isr, \
+    exti2_3_isr, \
+    exti4_15_isr, \
+    tsc_isr, \
+    dma1_channel1_isr, \
+    dma1_channel2_3_isr, \
+    dma1_channel4_5_isr, \
+    adc_comp_isr, \
+    tim1_brk_up_trg_com_isr, \
+    tim1_cc_isr, \
+    tim2_isr, \
+    tim3_isr, \
+    tim6_dac_isr, \
+    tim7_isr, \
+    tim14_isr, \
+    tim15_isr, \
+    tim16_isr, \
+    tim17_isr, \
+    i2c1_isr, \
+    i2c2_isr, \
+    spi1_isr, \
+    spi2_isr, \
+    usart1_isr, \
+    usart2_isr, \
+    usart3_4_isr, \
+    cec_can_isr, \
+    usb_isr
+
+typedef void (*vector_table_entry_t)(void);
+typedef void (*funcp_t) (void);
+
+typedef struct {
+    unsigned int *initial_sp_value; /**< Initial stack pointer value. */
+    vector_table_entry_t reset;
+    vector_table_entry_t nmi;
+    vector_table_entry_t hard_fault;
+    vector_table_entry_t memory_manage_fault; /* not in CM0 */
+    vector_table_entry_t bus_fault;           /* not in CM0 */
+    vector_table_entry_t usage_fault;         /* not in CM0 */
+    vector_table_entry_t reserved_x001c[4];
+    vector_table_entry_t sv_call;
+    vector_table_entry_t debug_monitor;       /* not in CM0 */
+    vector_table_entry_t reserved_x0034;
+    vector_table_entry_t pend_sv;
+    vector_table_entry_t systick;
+    vector_table_entry_t irq[NVIC_IRQ_COUNT];
+} vector_table_t;
+
+/* Symbols exported by the linker script(s): */
+extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
+extern funcp_t __preinit_array_start, __preinit_array_end;
+extern funcp_t __init_array_start, __init_array_end;
+extern funcp_t __fini_array_start, __fini_array_end;
+
+void main(void);
+void blocking_handler(void);
+void null_handler(void);
+
+__attribute__ ((section(".vectors")))
+vector_table_t vector_table = {
+    .initial_sp_value = &_stack,
+    .reset = reset_handler,
+    .nmi = nmi_handler,
+    .hard_fault = hard_fault_handler,
+    .sv_call = sv_call_handler,
+    .pend_sv = pend_sv_handler,
+    .systick = sys_tick_handler,
+    .irq = {
+        F0_IRQ_HANDLERS
+    }
+};
+
+void WEAK __attribute__ ((naked)) reset_handler(void)
+{
+    volatile unsigned *src, *dest;
+    funcp_t *fp;
+
+    for (src = &_data_loadaddr, dest = &_data;
+        dest < &_edata;
+        src++, dest++) {
+        *dest = *src;
+    }
+
+    while (dest < &_ebss) {
+        *dest++ = 0;
+    }
+
+    /* Constructors. */
+    for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) {
+        (*fp)();
+    }
+    for (fp = &__init_array_start; fp < &__init_array_end; fp++) {
+        (*fp)();
+    }
+
+    /* Call the application's entry point. */
+    main();
+
+    /* Destructors. */
+    for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) {
+        (*fp)();
+    }
+
+}
+
+void blocking_handler(void)
+{
+    while (1);
+}
+
+void null_handler(void)
+{
+    /* Do nothing. */
+}
+
+#pragma weak nmi_handler = null_handler
+#pragma weak hard_fault_handler = blocking_handler
+#pragma weak sv_call_handler = null_handler
+#pragma weak pend_sv_handler = null_handler
+#pragma weak sys_tick_handler = null_handler
+
+#pragma weak wwdg_isr = blocking_handler
+#pragma weak pvd_isr = blocking_handler
+#pragma weak rtc_isr = blocking_handler
+#pragma weak flash_isr = blocking_handler
+#pragma weak rcc_isr = blocking_handler
+#pragma weak exti0_1_isr = blocking_handler
+#pragma weak exti2_3_isr = blocking_handler
+#pragma weak exti4_15_isr = blocking_handler
+#pragma weak tsc_isr = blocking_handler
+#pragma weak dma1_channel1_isr = blocking_handler
+#pragma weak dma1_channel2_3_isr = blocking_handler
+#pragma weak dma1_channel4_5_isr = blocking_handler
+#pragma weak adc_comp_isr = blocking_handler
+#pragma weak tim1_brk_up_trg_com_isr = blocking_handler
+#pragma weak tim1_cc_isr = blocking_handler
+#pragma weak tim2_isr = blocking_handler
+#pragma weak tim3_isr = blocking_handler
+#pragma weak tim6_dac_isr = blocking_handler
+#pragma weak tim7_isr = blocking_handler
+#pragma weak tim14_isr = blocking_handler
+#pragma weak tim15_isr = blocking_handler
+#pragma weak tim16_isr = blocking_handler
+#pragma weak tim17_isr = blocking_handler
+#pragma weak i2c1_isr = blocking_handler
+#pragma weak i2c2_isr = blocking_handler
+#pragma weak spi1_isr = blocking_handler
+#pragma weak spi2_isr = blocking_handler
+#pragma weak usart1_isr = blocking_handler
+#pragma weak usart2_isr = blocking_handler
+#pragma weak usart3_4_isr = blocking_handler
+#pragma weak cec_can_isr = blocking_handler
+#pragma weak usb_isr = blocking_handler