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Add code & schematic for 48-channel I2C multiplexer
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66
STM32/src4multiplexer/hardware.c
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66
STM32/src4multiplexer/hardware.c
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/*
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* geany_encoding=koi8-r
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* hardware.c - hardware-dependent macros & functions
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*
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* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*
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*/
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#include "hardware.h"
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void gpio_setup(void){
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// Set green led (PB3) as output
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOAEN;
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GPIOB->MODER = GPIO_MODER_MODER3_O;
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// setup of multiplexer channel address bus: PA3..8
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GPIOA->MODER = GPIO_MODER_MODER3_O | GPIO_MODER_MODER4_O | GPIO_MODER_MODER5_O |
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GPIO_MODER_MODER6_O | GPIO_MODER_MODER7_O | GPIO_MODER_MODER8_O;
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}
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void i2c_setup(I2C_SPEED speed){
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I2C1->CR1 = 0;
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#if I2CPINS == A9A10
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/*
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* GPIO Resources: I2C1_SCL - PA9, I2C1_SDA - PA10
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* GPIOA->AFR[1] AF4 -- GPIOA->AFR[1] &= ~0xff0, GPIOA->AFR[1] |= 0x440
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*/
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN; // clock
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GPIOA->AFR[1] &= ~0xff0; // alternate function F4 for PA9/PA10
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GPIOA->AFR[1] |= 0x440;
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GPIOA->MODER &= ~(GPIO_MODER_MODER9 | GPIO_MODER_MODER10);
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GPIOA->MODER |= GPIO_MODER_MODER9_AF | GPIO_MODER_MODER10_AF; // alternate function
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GPIOA->OTYPER |= GPIO_OTYPER_OT_9 | GPIO_OTYPER_OT_10; // opendrain
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//GPIOA->OTYPER |= GPIO_OTYPER_OT_10; // opendrain
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#else // undefined
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#error "Not implemented"
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#endif
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// I2C
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // timing
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RCC->CFGR3 |= RCC_CFGR3_I2C1SW; // use sysclock for timing
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if(speed == LOW_SPEED){ // 10kHz
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// PRESC=B, SCLDEL=4, SDADEL=2, SCLH=0xC3, SCLL=0xC7
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//I2C1->TIMINGR = (0xB<<28) | (4<<20) | (2<<16) | (0xC3<<8) | (0xC7);
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I2C1->TIMINGR = (0xB<<28) | (4<<20) | (2<<16) | (0xC3<<8) | (0xB0);
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}else{ // 100kHz
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// Clock = 6MHz, 0.16(6)us, need 5us (*30)
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// PRESC=4 (f/5), SCLDEL=0 (t_SU=5/6us), SDADEL=0 (t_HD=5/6us), SCLL,SCLH=14 (2.(3)us)
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//I2C1->TIMINGR = (4<<28) | (14<<8) | (14); // 0x40000e0e
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I2C1->TIMINGR = (0xB<<28) | (4<<20) | (2<<16) | (0x12<<8) | (0x11);
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}
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I2C1->CR1 = I2C_CR1_PE;// | I2C_CR1_RXIE; // Enable I2C & (interrupt on receive - not supported yet)
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}
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