change protocol & firmware (to work @250kbaud and in sniffer mode)

STM32/inc/F0

@@ -0,0 +1 @@
+Fx

STM32/inc/Fx/common_macros.h

@@ -0,0 +1,57 @@
+/*
+ * common_macros.h - common usable things
+ *
+ * Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+#ifndef __COMMON_MACROS_H__
+#define __COMMON_MACROS_H__
+
+#include <stdint.h>
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE_INLINE
+#define TRUE_INLINE  __attribute__((always_inline)) static inline
+#endif
+
+#ifndef NULL
+#define NULL (0)
+#endif
+
+// some good things from CMSIS
+#define nop()   __NOP()
+
+#define pin_toggle(gpioport, gpios)  do{  \
+    register uint32_t __port = gpioport->ODR;  \
+    gpioport->BSRR = ((__port & gpios) << 16) | (~__port & gpios);}while(0)
+
+#define pin_set(gpioport, gpios)  do{gpioport->BSRR = gpios;}while(0)
+#define pin_clear(gpioport, gpios) do{gpioport->BSRR = ((gpios) << 16);}while(0)
+#define pin_read(gpioport, gpios) (gpioport->IDR & (gpios) ? 1 : 0)
+#define pin_write(gpioport, gpios)  do{gpioport->ODR = gpios;}while(0)
+
+
+
+#endif // __COMMON_MACROS_H__

STM32/inc/Fx/flash_size_reg.h

@@ -0,0 +1,10 @@
+#define STM32F0_FlashAddr   0x1FFFF7CC   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F0
+#define STM32F1_FlashAddr   0x1FFFF7E0   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F1
+#define STM32F2_FlashAddr   0x1FFF7A22   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F2
+#define STM32F3_FlashAddr   0x1FFFF7CC   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F3
+#define STM32F4_FlashAddr   0x1FFF7A22   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F4
+#define STM32F7_FlashAddr   0x1FF0F442   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F7
+#define STM32L0_FlashAddr   0x1FF8007C   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L0
+#define STM32L1_FlashAddr   0x1FF8004C   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L1
+#define STM32L4_FlashAddr   0x1FFF75E0   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L4
+#define STM32H7_FlashAddr   0x1FF0F442   // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÆÌÜÛ-ÐÁÍÑÔÉ STM32H7

STM32/inc/Fx/stm32f0.h

@@ -22,18 +22,10 @@
 #ifndef __STM32F0_H__
 #define __STM32F0_H__
 
+#include "vector.h"
 #include "stm32f0xx.h"
+#include "common_macros.h"
 
-#ifndef TRUE_INLINE
-#define TRUE_INLINE  __attribute__((always_inline)) static inline
-#endif
-
-#ifndef NULL
-#define NULL (0)
-#endif
-
-// some good things from CMSIS
-#define nop()   __NOP()
 
 /************************* RCC *************************/
 // reset clocking registers
@@ -105,33 +97,34 @@ TRUE_INLINE void sysreset(void){
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL){}
 }
-/* wrong
+
 TRUE_INLINE void StartHSE(){
     // disable PLL
     RCC->CR &= ~RCC_CR_PLLON;
     RCC->CR |= RCC_CR_HSEON;
-    while ((RCC->CIR & RCC_CIR_HSERDYF) == 0);
+    while ((RCC->CIR & RCC_CIR_HSERDYF) != 0);
     RCC->CIR |= RCC_CIR_HSERDYC; // clear rdy flag
-    // PLL configuration = (HSE) * 12 = ~48 MHz
+    /* PLL configuration = (HSE) * 12 = ~48 MHz */
     RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
     RCC->CFGR |= RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL12;
     RCC->CR |= RCC_CR_PLLON;
     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL){}
-}       */
+}
 
 #if defined (STM32F042x6) || defined (STM32F072xb)
 TRUE_INLINE void StartHSI48(){
-    RCC->APB1ENR |= RCC_APB1ENR_CRSEN | RCC_APB1ENR_USBEN; // enable CRS (hsi48 sync) & USB
-    RCC->CFGR3 &= ~RCC_CFGR3_USBSW; // reset USB
-    RCC->CR2 |= RCC_CR2_HSI48ON; // turn ON HSI48
-    uint32_t tmout = 16000000;
-    while(!(RCC->CR2 & RCC_CR2_HSI48RDY)){if(--tmout == 0) break;}
-    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
-    CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
-    CRS->CFGR |= CRS_CFGR_SYNCSRC_1; // USB SOF selected as sync source
-    CRS->CR |= CRS_CR_AUTOTRIMEN; // enable auto trim
-    CRS->CR |= CRS_CR_CEN; // enable freq counter & block CRS->CFGR as read-only
-    RCC->CFGR |= RCC_CFGR_SW;
+    // disable PLL
+    RCC->CR &= ~RCC_CR_PLLON;
+    RCC->CR2 &= RCC_CR2_HSI48ON; // turn on HSI48
+    while((RCC->CR2 & RCC_CR2_HSI48RDY) == 0);
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL));
+    // HSI48/2 * 2 = HSI48
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI48_PREDIV | RCC_CFGR_PLLMUL2);
+    RCC->CR |= RCC_CR_PLLON;
+    // select HSI48 as system clock source
+    RCC->CFGR &= ~RCC_CFGR_SW;
+    RCC->CFGR |= RCC_CFGR_SW_HSI48;
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI48){}
 }
 #endif
 
@@ -188,14 +181,86 @@ TRUE_INLINE void StartHSI48(){
 #define GPIO_MODER_MODER15_O        ((uint32_t)0x40000000)
 #define GPIO_MODER_MODER15_AF       ((uint32_t)0x80000000)
 
-#define pin_toggle(gpioport, gpios)  do{  \
-    register uint32_t __port = gpioport->ODR;  \
-    gpioport->BSRR = ((__port & gpios) << 16) | (~__port & gpios);}while(0)
+/*******************  Bit definition for GPIO_PUPDR register  *****************/
+// no/pullup/pulldown/reserved
+// for n in $(seq 0 15); do echo "#define GPIO_PUPDR${n}_PU              ((uint32_t)(1<<$((n*2))))";
+// echo "#define GPIO_PUPDR${n}_PD              ((uint32_t)(1<<$((n*2+1))))"; done
+// alt+select column -> delete
+#define GPIO_PUPDR0_PU              ((uint32_t)(1<<0))
+#define GPIO_PUPDR0_PD              ((uint32_t)(1<<1))
+#define GPIO_PUPDR1_PU              ((uint32_t)(1<<2))
+#define GPIO_PUPDR1_PD              ((uint32_t)(1<<3))
+#define GPIO_PUPDR2_PU              ((uint32_t)(1<<4))
+#define GPIO_PUPDR2_PD              ((uint32_t)(1<<5))
+#define GPIO_PUPDR3_PU              ((uint32_t)(1<<6))
+#define GPIO_PUPDR3_PD              ((uint32_t)(1<<7))
+#define GPIO_PUPDR4_PU              ((uint32_t)(1<<8))
+#define GPIO_PUPDR4_PD              ((uint32_t)(1<<9))
+#define GPIO_PUPDR5_PU              ((uint32_t)(1<<10))
+#define GPIO_PUPDR5_PD              ((uint32_t)(1<<11))
+#define GPIO_PUPDR6_PU              ((uint32_t)(1<<12))
+#define GPIO_PUPDR6_PD              ((uint32_t)(1<<13))
+#define GPIO_PUPDR7_PU              ((uint32_t)(1<<14))
+#define GPIO_PUPDR7_PD              ((uint32_t)(1<<15))
+#define GPIO_PUPDR8_PU              ((uint32_t)(1<<16))
+#define GPIO_PUPDR8_PD              ((uint32_t)(1<<17))
+#define GPIO_PUPDR9_PU              ((uint32_t)(1<<18))
+#define GPIO_PUPDR9_PD              ((uint32_t)(1<<19))
+#define GPIO_PUPDR10_PU             ((uint32_t)(1<<20))
+#define GPIO_PUPDR10_PD             ((uint32_t)(1<<21))
+#define GPIO_PUPDR11_PU             ((uint32_t)(1<<22))
+#define GPIO_PUPDR11_PD             ((uint32_t)(1<<23))
+#define GPIO_PUPDR12_PU             ((uint32_t)(1<<24))
+#define GPIO_PUPDR12_PD             ((uint32_t)(1<<25))
+#define GPIO_PUPDR13_PU             ((uint32_t)(1<<26))
+#define GPIO_PUPDR13_PD             ((uint32_t)(1<<27))
+#define GPIO_PUPDR14_PU             ((uint32_t)(1<<28))
+#define GPIO_PUPDR14_PD             ((uint32_t)(1<<29))
+#define GPIO_PUPDR15_PU             ((uint32_t)(1<<30))
+#define GPIO_PUPDR15_PD             ((uint32_t)(1<<31))
+// OSPEEDR
+// for n in $(seq 0 15); do echo "#define GPIO_OSPEEDR${n}_MED           ((uint32_t)(1<<$((n*2))))";
+// echo "#define GPIO_OSPEEDR${n}_HIGH          ((uint32_t)(3<<$((2*n))))"; done
+#define GPIO_OSPEEDR0_MED           ((uint32_t)(1<<0))
+#define GPIO_OSPEEDR0_HIGH          ((uint32_t)(3<<0))
+#define GPIO_OSPEEDR1_MED           ((uint32_t)(1<<2))
+#define GPIO_OSPEEDR1_HIGH          ((uint32_t)(3<<2))
+#define GPIO_OSPEEDR2_MED           ((uint32_t)(1<<4))
+#define GPIO_OSPEEDR2_HIGH          ((uint32_t)(3<<4))
+#define GPIO_OSPEEDR3_MED           ((uint32_t)(1<<6))
+#define GPIO_OSPEEDR3_HIGH          ((uint32_t)(3<<6))
+#define GPIO_OSPEEDR4_MED           ((uint32_t)(1<<8))
+#define GPIO_OSPEEDR4_HIGH          ((uint32_t)(3<<8))
+#define GPIO_OSPEEDR5_MED           ((uint32_t)(1<<10))
+#define GPIO_OSPEEDR5_HIGH          ((uint32_t)(3<<10))
+#define GPIO_OSPEEDR6_MED           ((uint32_t)(1<<12))
+#define GPIO_OSPEEDR6_HIGH          ((uint32_t)(3<<12))
+#define GPIO_OSPEEDR7_MED           ((uint32_t)(1<<14))
+#define GPIO_OSPEEDR7_HIGH          ((uint32_t)(3<<14))
+#define GPIO_OSPEEDR8_MED           ((uint32_t)(1<<16))
+#define GPIO_OSPEEDR8_HIGH          ((uint32_t)(3<<16))
+#define GPIO_OSPEEDR9_MED           ((uint32_t)(1<<18))
+#define GPIO_OSPEEDR9_HIGH          ((uint32_t)(3<<18))
+#define GPIO_OSPEEDR10_MED          ((uint32_t)(1<<20))
+#define GPIO_OSPEEDR10_HIGH         ((uint32_t)(3<<20))
+#define GPIO_OSPEEDR11_MED          ((uint32_t)(1<<22))
+#define GPIO_OSPEEDR11_HIGH         ((uint32_t)(3<<22))
+#define GPIO_OSPEEDR12_MED          ((uint32_t)(1<<24))
+#define GPIO_OSPEEDR12_HIGH         ((uint32_t)(3<<24))
+#define GPIO_OSPEEDR13_MED          ((uint32_t)(1<<26))
+#define GPIO_OSPEEDR13_HIGH         ((uint32_t)(3<<26))
+#define GPIO_OSPEEDR14_MED          ((uint32_t)(1<<28))
+#define GPIO_OSPEEDR14_HIGH         ((uint32_t)(3<<28))
+#define GPIO_OSPEEDR15_MED          ((uint32_t)(1<<30))
+#define GPIO_OSPEEDR15_HIGH         ((uint32_t)(3<<30))
 
-#define pin_set(gpioport, gpios)  do{gpioport->BSRR = gpios;}while(0)
-#define pin_clear(gpioport, gpios) do{gpioport->BSRR = (gpios << 16);}while(0)
-#define pin_read(gpioport, gpios) (gpioport->IDR & gpios ? 1 : 0)
-#define pin_write(gpioport, gpios)  do{gpioport->ODR = gpios;}while(0)
+
+
+/******************  FLASH Keys  **********************************************/
+#define RDP_Key                 ((uint16_t)0x00A5)
+#define FLASH_KEY1              ((uint32_t)0x45670123)
+#define FLASH_KEY2              ((uint32_t)0xCDEF89AB)
+#define FLASH_SIZE_REG          ((uint32_t)0x1FFFF7CC)
 
 /************************* ADC *************************/
 /* inner termometer calibration values

STM32/inc/Fx/stm32f0xx.h

@@ -73,51 +73,6 @@
     #error "Define STM32 family, for example -DSTM32F042x6"
 #endif
 
-#ifndef WEAK
-#define WEAK __attribute__((weak))
-#endif
-
-void WEAK reset_handler(void);
-void WEAK nmi_handler(void);
-void WEAK hard_fault_handler(void);
-void WEAK sv_call_handler(void);
-void WEAK pend_sv_handler(void);
-void WEAK sys_tick_handler(void);
-
-void WEAK wwdg_isr(void);
-void WEAK pvd_isr(void);
-void WEAK rtc_isr(void);
-void WEAK flash_isr(void);
-void WEAK rcc_isr(void);
-void WEAK exti0_1_isr(void);
-void WEAK exti2_3_isr(void);
-void WEAK exti4_15_isr(void);
-void WEAK tsc_isr(void);
-void WEAK dma1_channel1_isr(void);
-void WEAK dma1_channel2_3_isr(void);
-void WEAK dma1_channel4_5_isr(void);
-void WEAK adc_comp_isr(void);
-void WEAK tim1_brk_up_trg_com_isr(void);
-void WEAK tim1_cc_isr(void);
-void WEAK tim2_isr(void);
-void WEAK tim3_isr(void);
-void WEAK tim6_dac_isr(void);
-void WEAK tim7_isr(void);
-void WEAK tim14_isr(void);
-void WEAK tim15_isr(void);
-void WEAK tim16_isr(void);
-void WEAK tim17_isr(void);
-void WEAK i2c1_isr(void);
-void WEAK i2c2_isr(void);
-void WEAK spi1_isr(void);
-void WEAK spi2_isr(void);
-void WEAK usart1_isr(void);
-void WEAK usart2_isr(void);
-void WEAK usart3_4_isr(void);
-void WEAK cec_can_isr(void);
-void WEAK usb_isr(void);
-
-
 /**
   * @brief CMSIS Device version number V2.2.0
   */

STM32/inc/Fx/stm32f1.h

@@ -0,0 +1,221 @@
+/*
+ * stm32f1.h
+ *
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+#ifndef __STM32F1_H__
+#define __STM32F1_H__
+
+#include "vector.h"
+#include "stm32f10x.h"
+#include "common_macros.h"
+
+
+/************************* RCC *************************/
+// reset clocking registers
+TRUE_INLINE void sysreset(void){
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */   
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+#ifdef STM32F10X_CL
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */ 
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+TRUE_INLINE void StartHSE()
+{
+  __IO uint32_t StartUpCounter = 0;
+  
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
+  /* Enable HSE */    
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    ++StartUpCounter;
+  } while(!(RCC->CR & RCC_CR_HSERDY) && (StartUpCounter < 10000));
+
+
+  if (RCC->CR & RCC_CR_HSERDY) // HSE started
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    
+ 
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+    
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+        
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+  
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    StartUpCounter = 0;
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0 && ++StartUpCounter < 1000){}
+       
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
+                            RCC_CFGR_PLLMULL9); 
+#else    
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    StartUpCounter = 0;
+    while((RCC->CR & RCC_CR_PLLRDY) == 0 && ++StartUpCounter < 1000){}
+    
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
+
+    /* Wait till PLL is used as system clock source */
+    StartUpCounter = 0;
+    while(((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) && ++StartUpCounter < 1000){}
+  }
+  else // HSE fails to start-up
+  { 
+        ; // add some code here (use HSI)
+  }  
+}
+
+
+
+/************************* GPIO *************************/
+/**
+CNF1: 0 - general output or input; 1 - alternate output or pullup/down input
+CNF0: 0 - push/pull, analog or pullup/down input
+MODE: 00 - input, 01 - 10MHz, 10 - 2MHz, 11 - 50MHz
+Pullup/down: ODR = 0 - pulldown, 1 - pullup
+GPIO_BSRR and BRR also works
+IDR - input, ODR - output (or pullups management), 
+*/
+// MODE:
+#define MODE_INPUT      0
+#define MODE_NORMAL     1  // 10MHz
+#define MODE_SLOW       2  // 2MHz
+#define MODE_FAST       3  // 50MHz
+// CNF:
+#define CNF_ANALOG      (0 << 2)
+#define CNF_PPOUTPUT    (0 << 2)
+#define CNF_FLINPUT     (1 << 2)
+#define CNF_ODOUTPUT    (1 << 2)
+#define CNF_PUDINPUT    (2 << 2)
+#define CNF_AFPP        (2 << 2)
+#define CNF_AFOD        (3 << 2)
+
+#define CRL(pin, cnfmode)  ((cnfmode) << (pin*4))
+#define CRH(pin, cnfmode)  ((cnfmode) << ((pin-8)*4))
+
+
+/************************* ADC *************************/
+/* inner termometer calibration values
+ *         Temp = (V25 - Vsense)/Avg_Slope + 25
+ */
+#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
+
+/************************* IWDG *************************/
+#define IWDG_REFRESH      (uint32_t)(0x0000AAAA)
+#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
+#define IWDG_START        (uint32_t)(0x0000CCCC)
+
+// flash size
+#define FLASH_SIZE_REG      ((uint32_t)0x1FFFF7E0)
+
+
+#if 0
+/************************* ADC *************************/
+/* inner termometer calibration values
+ *         Temp = (V30 - Vsense)/Avg_Slope + 30
+ *         Avg_Slope = (V30 - V110) / (110 - 30)
+ */
+#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
+#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
+// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
+#define VDD_CALIB ((uint16_t) (330))
+#define VDD_APPLI ((uint16_t) (300))
+
+/************************* USART *************************/
+
+#define USART_CR2_ADD_SHIFT     24
+// set address/character match value
+#define USART_CR2_ADD_VAL(x)        ((x) << USART_CR2_ADD_SHIFT)
+
+
+//#define  do{}while(0)
+
+
+#endif
+
+#endif // __STM32F1_H__

STM32/inc/Fx/vector.h

@@ -0,0 +1,410 @@
+/*
+ * vector.h
+ *
+ * Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#pragma once
+#ifndef VECTOR_H
+#define VECTOR_H 
+
+#ifndef WEAK
+#define WEAK __attribute__((weak))
+#endif
+
+void WEAK reset_handler(void);
+void WEAK nmi_handler(void);
+void WEAK hard_fault_handler(void);
+void WEAK sv_call_handler(void);
+void WEAK pend_sv_handler(void);
+void WEAK sys_tick_handler(void);
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+void WEAK mem_manage_handler(void);
+void WEAK bus_fault_handler(void);
+void WEAK usage_fault_handler(void);
+void WEAK debug_monitor_handler(void);
+#endif
+
+#if defined STM32F0
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK rtc_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_1_isr(void);
+void WEAK exti2_3_isr(void);
+void WEAK exti4_15_isr(void);
+void WEAK tsc_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_3_isr(void);
+void WEAK dma1_channel4_5_isr(void);
+void WEAK adc_comp_isr(void);
+void WEAK tim1_brk_up_trg_com_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK tim14_isr(void);
+void WEAK tim15_isr(void);
+void WEAK tim16_isr(void);
+void WEAK tim17_isr(void);
+void WEAK i2c1_isr(void);
+void WEAK i2c2_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_4_isr(void);
+void WEAK cec_can_isr(void);
+void WEAK usb_isr(void);
+
+#elif defined STM32F1 
+void WEAK wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamper_isr(void);
+void WEAK rtc_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_isr(void);
+void WEAK dma1_channel3_isr(void);
+void WEAK dma1_channel4_isr(void);
+void WEAK dma1_channel5_isr(void);
+void WEAK dma1_channel6_isr(void);
+void WEAK dma1_channel7_isr(void);
+void WEAK adc1_2_isr(void);
+void WEAK usb_hp_can_tx_isr(void);
+void WEAK usb_lp_can_rx0_isr(void);
+void WEAK can_rx1_isr(void);
+void WEAK can_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_isr(void);
+void WEAK tim1_up_isr(void);
+void WEAK tim1_trg_com_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_wakeup_isr(void);
+void WEAK tim8_brk_isr(void);
+void WEAK tim8_up_isr(void);
+void WEAK tim8_trg_com_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK adc3_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_channel1_isr(void);
+void WEAK dma2_channel2_isr(void);
+void WEAK dma2_channel3_isr(void);
+void WEAK dma2_channel4_5_isr(void);
+void WEAK dma2_channel5_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+
+#elif defined STM32F2
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+
+#elif defined STM32F3
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_tsc_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_channel1_isr(void);
+void WEAK dma1_channel2_isr(void);
+void WEAK dma1_channel3_isr(void);
+void WEAK dma1_channel4_isr(void);
+void WEAK dma1_channel5_isr(void);
+void WEAK dma1_channel6_isr(void);
+void WEAK dma1_channel7_isr(void);
+void WEAK adc1_2_isr(void);
+void WEAK usb_hp_can1_tx_isr(void);
+void WEAK usb_lp_can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim15_isr(void);
+void WEAK tim1_up_tim16_isr(void);
+void WEAK tim1_trg_com_tim17_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_exti23_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_exti24_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_exti25_isr(void);
+void WEAK usart2_exti26_isr(void);
+void WEAK usart3_exti28_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_wkup_a_isr(void);
+void WEAK tim8_brk_isr(void);
+void WEAK tim8_up_isr(void);
+void WEAK tim8_trg_com_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK adc3_isr(void);
+void WEAK reserved_1_isr(void);
+void WEAK reserved_2_isr(void);
+void WEAK reserved_3_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_exti34_isr(void);
+void WEAK uart5_exti35_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_channel1_isr(void);
+void WEAK dma2_channel2_isr(void);
+void WEAK dma2_channel3_isr(void);
+void WEAK dma2_channel4_isr(void);
+void WEAK dma2_channel5_isr(void);
+void WEAK eth_isr(void);
+void WEAK reserved_4_isr(void);
+void WEAK reserved_5_isr(void);
+void WEAK comp123_isr(void);
+void WEAK comp456_isr(void);
+void WEAK comp7_isr(void);
+void WEAK reserved_6_isr(void);
+void WEAK reserved_7_isr(void);
+void WEAK reserved_8_isr(void);
+void WEAK reserved_9_isr(void);
+void WEAK reserved_10_isr(void);
+void WEAK reserved_11_isr(void);
+void WEAK reserved_12_isr(void);
+void WEAK usb_hp_isr(void);
+void WEAK usb_lp_isr(void);
+void WEAK usb_wkup_isr(void);
+void WEAK reserved_13_isr(void);
+void WEAK reserved_14_isr(void);
+void WEAK reserved_15_isr(void);
+void WEAK reserved_16_isr(void);
+
+#elif defined STM32F4
+void WEAK nvic_wwdg_isr(void);
+void WEAK pvd_isr(void);
+void WEAK tamp_stamp_isr(void);
+void WEAK rtc_wkup_isr(void);
+void WEAK flash_isr(void);
+void WEAK rcc_isr(void);
+void WEAK exti0_isr(void);
+void WEAK exti1_isr(void);
+void WEAK exti2_isr(void);
+void WEAK exti3_isr(void);
+void WEAK exti4_isr(void);
+void WEAK dma1_stream0_isr(void);
+void WEAK dma1_stream1_isr(void);
+void WEAK dma1_stream2_isr(void);
+void WEAK dma1_stream3_isr(void);
+void WEAK dma1_stream4_isr(void);
+void WEAK dma1_stream5_isr(void);
+void WEAK dma1_stream6_isr(void);
+void WEAK adc_isr(void);
+void WEAK can1_tx_isr(void);
+void WEAK can1_rx0_isr(void);
+void WEAK can1_rx1_isr(void);
+void WEAK can1_sce_isr(void);
+void WEAK exti9_5_isr(void);
+void WEAK tim1_brk_tim9_isr(void);
+void WEAK tim1_up_tim10_isr(void);
+void WEAK tim1_trg_com_tim11_isr(void);
+void WEAK tim1_cc_isr(void);
+void WEAK tim2_isr(void);
+void WEAK tim3_isr(void);
+void WEAK tim4_isr(void);
+void WEAK i2c1_ev_isr(void);
+void WEAK i2c1_er_isr(void);
+void WEAK i2c2_ev_isr(void);
+void WEAK i2c2_er_isr(void);
+void WEAK spi1_isr(void);
+void WEAK spi2_isr(void);
+void WEAK usart1_isr(void);
+void WEAK usart2_isr(void);
+void WEAK usart3_isr(void);
+void WEAK exti15_10_isr(void);
+void WEAK rtc_alarm_isr(void);
+void WEAK usb_fs_wkup_isr(void);
+void WEAK tim8_brk_tim12_isr(void);
+void WEAK tim8_up_tim13_isr(void);
+void WEAK tim8_trg_com_tim14_isr(void);
+void WEAK tim8_cc_isr(void);
+void WEAK dma1_stream7_isr(void);
+void WEAK fsmc_isr(void);
+void WEAK sdio_isr(void);
+void WEAK tim5_isr(void);
+void WEAK spi3_isr(void);
+void WEAK uart4_isr(void);
+void WEAK uart5_isr(void);
+void WEAK tim6_dac_isr(void);
+void WEAK tim7_isr(void);
+void WEAK dma2_stream0_isr(void);
+void WEAK dma2_stream1_isr(void);
+void WEAK dma2_stream2_isr(void);
+void WEAK dma2_stream3_isr(void);
+void WEAK dma2_stream4_isr(void);
+void WEAK eth_isr(void);
+void WEAK eth_wkup_isr(void);
+void WEAK can2_tx_isr(void);
+void WEAK can2_rx0_isr(void);
+void WEAK can2_rx1_isr(void);
+void WEAK can2_sce_isr(void);
+void WEAK otg_fs_isr(void);
+void WEAK dma2_stream5_isr(void);
+void WEAK dma2_stream6_isr(void);
+void WEAK dma2_stream7_isr(void);
+void WEAK usart6_isr(void);
+void WEAK i2c3_ev_isr(void);
+void WEAK i2c3_er_isr(void);
+void WEAK otg_hs_ep1_out_isr(void);
+void WEAK otg_hs_ep1_in_isr(void);
+void WEAK otg_hs_wkup_isr(void);
+void WEAK otg_hs_isr(void);
+void WEAK dcmi_isr(void);
+void WEAK cryp_isr(void);
+void WEAK hash_rng_isr(void);
+void WEAK fpu_isr(void);
+void WEAK uart7_isr(void);
+void WEAK uart8_isr(void);
+void WEAK spi4_isr(void);
+void WEAK spi5_isr(void);
+void WEAK spi6_isr(void);
+void WEAK sai1_isr(void);
+void WEAK lcd_tft_isr(void);
+void WEAK lcd_tft_err_isr(void);
+void WEAK dma2d_isr(void);
+
+#else
+    #error "Not supported platform"
+#endif
+
+#endif // VECTOR_H

STM32/inc/cm/core_cmFunc.h

@@ -453,7 +453,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 {
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack));
 }
 
 

STM32/inc/gen042

@@ -1,2 +0,0 @@
-#!/bin/sh
-CFLAGS="-IF0 -Icm -DSTM32F042x6" geany -g stm32f042.c.tags F0/stm32f042x6.h F0/stm32f0.h F0/stm32f0xx.h cm/core_cm0.h cm/core_cmFunc.h cm/core_cmInstr.h cm/core_cmSimd.h startup/vector.c

STM32/inc/ld/stm32f0.ld

@@ -1,106 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Generic linker script for STM32 targets using libopencm3. */
-
-/* Memory regions must be defined in the ld script which includes this one. */
-
-/* Enforce emmition of the vector table. */
-EXTERN (vector_table)
-
-/* Define the entry point of the output file. */
-ENTRY(reset_handler)
-
-/* Define sections. */
-SECTIONS
-{
-	.text : {
-		*(.vectors)	/* Vector table */
-		*(.text*)	/* Program code */
-		. = ALIGN(4);
-		*(.rodata*)	/* Read-only data */
-		. = ALIGN(4);
-	} >rom
-
-	/* C++ Static constructors/destructors, also used for __attribute__
-	 * ((constructor)) and the likes */
-	.preinit_array : {
-		. = ALIGN(4);
-		__preinit_array_start = .;
-		KEEP (*(.preinit_array))
-		__preinit_array_end = .;
-	} >rom
-	.init_array : {
-		. = ALIGN(4);
-		__init_array_start = .;
-		KEEP (*(SORT(.init_array.*)))
-		KEEP (*(.init_array))
-		__init_array_end = .;
-	} >rom
-	.fini_array : {
-		. = ALIGN(4);
-		__fini_array_start = .;
-		KEEP (*(.fini_array))
-		KEEP (*(SORT(.fini_array.*)))
-		__fini_array_end = .;
-	} >rom
-
-	/*
-	 * Another section used by C++ stuff, appears when using newlib with
-	 * 64bit (long long) printf support
-	 */
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} >rom
-	.ARM.exidx : {
-		__exidx_start = .;
-		*(.ARM.exidx*)
-		__exidx_end = .;
-	} >rom
-
-	. = ALIGN(4);
-	_etext = .;
-
-	.data : {
-		_data = .;
-		*(.data*)	/* Read-write initialized data */
-		. = ALIGN(4);
-		_edata = .;
-	} >ram AT >rom
-	_data_loadaddr = LOADADDR(.data);
-
-	.bss : {
-		*(.bss*)	/* Read-write zero initialized data */
-		*(COMMON)
-		. = ALIGN(4);
-		_ebss = .;
-	} >ram
-
-	/*
-	 * The .eh_frame section appears to be used for C++ exception handling.
-	 * You may need to fix this if you're using C++.
-	 */
-	/DISCARD/ : { *(.eh_frame) }
-
-	. = ALIGN(4);
-	end = .;
-}
-
-PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
-

STM32/inc/ld/stm32f01234.ld

@@ -0,0 +1,94 @@
+/*
+********************************************************************************
+*                                                                              *
+* Copyright (c) 2017 Andrea Loi                                                *
+*                                                                              *
+* Permission is hereby granted, free of charge, to any person obtaining a      *
+* copy of this software and associated documentation files (the "Software"),   *
+* to deal in the Software without restriction, including without limitation    *
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,     *
+* and/or sell copies of the Software, and to permit persons to whom the        *
+* Software is furnished to do so, subject to the following conditions:         *
+*                                                                              *
+* The above copyright notice and this permission notice shall be included      *
+* in all copies or substantial portions of the Software.                       *
+*                                                                              *
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR   *
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,     *
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL      *
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER   *
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING      *
+* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER          *
+* DEALINGS IN THE SOFTWARE.                                                    *
+*                                                                              *
+********************************************************************************
+*/
+
+
+
+/******************************************************************************/
+/*          DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING!           */
+/******************************************************************************/
+
+/* _isrvectors_tend =    0x00000150; - different for different series */
+
+ENTRY(reset_handler)
+
+SECTIONS {
+  .vector_table 0x08000000 :
+  {
+    _sisrvectors = .;
+    KEEP(*(.vector_table))
+    /* ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!"); */
+    _eisrvectors = .;
+  } >rom
+
+  .text :
+  {
+    . = ALIGN(4);
+    _stext = .;
+    *(.text*)
+    *(.rodata*)
+    . = ALIGN(4);
+    _etext = .;
+  } >rom
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >rom
+  
+  .ARM : {
+    *(.ARM.exidx*)
+  } >rom
+  
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;
+    *(.data*)
+    . = ALIGN(4);
+    _edata = .;
+  } >ram AT >rom
+
+  .myvars :
+  {
+    . = ALIGN(_BLOCKSIZE);
+    __varsstart = ABSOLUTE(.);
+    KEEP(*(.myvars));
+  } > rom
+
+  _ldata = LOADADDR(.data);
+
+  .bss :
+  {
+    . = ALIGN(4);
+    _sbss = .;
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    _ebss = .;
+  } >ram
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));

STM32/inc/ld/stm32f030f.ld

@@ -0,0 +1,14 @@
+/* Linker script for STM32F030f4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+    rom   (rx) : ORIGIN = 0x08000000, LENGTH = 16K
+    ram  (rwx) : ORIGIN = 0x20000000, LENGTH = 4K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f042k.ld

@@ -0,0 +1,14 @@
+/* Linker script for STM32F042x6, 32K flash, 6K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+    rom   (rx) : ORIGIN = 0x08000000, LENGTH = 32K
+    ram  (rwx) : ORIGIN = 0x20000000, LENGTH = 6K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f042x6.ld

@@ -0,0 +1,14 @@
+/* Linker script for STM32F042x6, 32K flash, 6K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+    rom   (rx) : ORIGIN = 0x08000000, LENGTH = 32K
+    ram  (rwx) : ORIGIN = 0x20000000, LENGTH = 6K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f051x8.ld

@@ -0,0 +1,14 @@
+/* Linker script for STM32F051x8, 64K flash, 8K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+    rom (rx) : ORIGIN = 0x08000000, LENGTH =  64K
+    ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f0728.ld

@@ -0,0 +1,14 @@
+/* Linker script for STM32F072x8, 64K flash, 16K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+    rom   (rx) : ORIGIN = 0x08000000, LENGTH = 64K
+    ram  (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f072B.ld

@@ -0,0 +1,14 @@
+/* Linker script for STM32F072xB, 128K flash, 16K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+    rom   (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+    ram  (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+}
+
+_BLOCKSIZE = 2048;
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103x4.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 16K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103x6.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH =  32K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 10K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103x8.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH =  64K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103xB.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103xC.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103xD.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 384K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103xE.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103xF.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 768K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+

STM32/inc/ld/stm32f103xG.ld

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH =  96K
+}
+
+PROVIDE(_BLOCKSIZE = 1024);
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+