mirror of
https://github.com/eddyem/stm32samples.git
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75 lines
2.4 KiB
C
75 lines
2.4 KiB
C
/*
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* dmagpio.c
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*
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* Copyright 2016 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include "dmagpio.h"
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#include "user_proto.h"
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int transfer_complete = 0;
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static uint16_t gpiobuff[128] = {0};
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void dmagpio_init(){
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// init TIM2 & DMA1ch2 (TIM2UP)
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rcc_periph_clock_enable(RCC_TIM2);
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rcc_periph_clock_enable(RCC_DMA1);
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timer_reset(TIM2);
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// timer have frequency of 1MHz
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timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
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// 72MHz div 18 = 4MHz
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TIM2_PSC = 0; // prescaler is (div - 1)
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TIM2_ARR = 1; // 36MHz (6.25)
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TIM2_DIER = TIM_DIER_UDE;// | TIM_DIER_UIE;
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dma_channel_reset(DMA1, DMA_CHANNEL2);
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// mem2mem, medium prio, 8bits, memory increment, read from mem, transfer complete en
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DMA1_CCR2 = DMA_CCR_PL_MEDIUM | DMA_CCR_MSIZE_16BIT |
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DMA_CCR_PSIZE_16BIT | DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE | DMA_CCR_TEIE ;
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nvic_enable_irq(NVIC_DMA1_CHANNEL2_IRQ);
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// target address:
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DMA1_CPAR2 = DMAGPIO_TARGADDR;
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DMA1_CMAR2 = (uint32_t) gpiobuff;
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}
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void dmagpio_transfer(uint8_t *databuf, uint32_t length){
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while(DMA1_CCR2 & DMA_CCR_EN);
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transfer_complete = 0;
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DMA1_IFCR = 0xff00; // clear all flags for ch2
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// buffer length
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DMA1_CNDTR2 = length;
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uint32_t i;
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for(i = 0; i < length; ++i) gpiobuff[i] = databuf[i];
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TIM2_CR1 |= TIM_CR1_CEN; // run timer
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DMA1_CCR2 |= DMA_CCR_EN;
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}
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void dma1_channel2_isr(){
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if(DMA1_ISR & DMA_ISR_TCIF2){
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transfer_complete = 1;
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// stop timer & turn off DMA
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TIM2_CR1 &= ~TIM_CR1_CEN;
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DMA1_CCR2 &= ~DMA_CCR_EN;
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DMA1_IFCR = DMA_IFCR_CTCIF2; // clear flag
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}else if(DMA1_ISR & DMA_ISR_TEIF2){
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P("Error\n");
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DMA1_IFCR = DMA_IFCR_CTEIF2;
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TIM2_CR1 &= ~TIM_CR1_CEN;
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DMA1_CCR2 &= ~DMA_CCR_EN;
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}
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}
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