mirror of
https://github.com/eddyem/stm32samples.git
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87 lines
2.9 KiB
Plaintext
87 lines
2.9 KiB
Plaintext
/*
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********************************************************************************
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* *
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* Copyright (c) 2017 Andrea Loi *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included *
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* in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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********************************************************************************
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*/
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/******************************************************************************/
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/* DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING! */
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/******************************************************************************/
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/* _isrvectors_tend = 0x00000150; - different for different series */
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ENTRY(reset_handler)
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SECTIONS {
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.vector_table 0x08000000 :
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{
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_sisrvectors = .;
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KEEP(*(.vector_table))
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/* ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!"); */
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_eisrvectors = .;
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} >rom
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.text :
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{
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. = ALIGN(4);
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_stext = .;
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*(.text*)
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*(.rodata*)
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. = ALIGN(4);
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_etext = .;
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} >rom
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >rom
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.ARM : {
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*(.ARM.exidx*)
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} >rom
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.data :
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{
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. = ALIGN(4);
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_sdata = .;
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*(.data*)
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. = ALIGN(4);
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_edata = .;
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} >ram AT >rom
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_ldata = LOADADDR(.data);
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.bss :
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{
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. = ALIGN(4);
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_sbss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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} >ram
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}
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PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); |