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123 lines
5.4 KiB
C
123 lines
5.4 KiB
C
/*
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* This file is part of the multistepper project.
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* Copyright 2023 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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// Buttons: PA8, PA9, PA10, PF6, PD3, PD4, PD5, pullup (active - 0)
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volatile GPIO_TypeDef* const BTNports[BTNSNO] = {GPIOA, GPIOA, GPIOA, GPIOF, GPIOD, GPIOD, GPIOD};
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const uint32_t BTNpins[BTNSNO] = {1<<8, 1<<9, 1<<10, 1<<6, 1<<3, 1<<4, 1<<5};
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// setup here ALL GPIO pins (due to table in Readme.md)
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// leave SWD as default AF; high speed for CLK and some other AF; med speed for some another AF
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TRUE_INLINE void gpio_setup(){
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN
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| RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN;
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for(int i = 0; i < 10000; ++i) nop();
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GPIOA->ODR = 0;
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GPIOA->AFR[0] = AFRf(5, 5) | AFRf(5, 6) | AFRf(5, 7);
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GPIOA->AFR[1] = /*AFRf(4, 10) |*/ AFRf(14, 11) | AFRf(14,12) | AFRf(1, 15);
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GPIOA->MODER = MODER_AF(5) | MODER_AF(6) | MODER_AF(7) | MODER_I(8) | MODER_I(9) | MODER_I(10) /*MODER_AF(10)*/
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| MODER_AF(11) | MODER_AF(12) | MODER_O(13) | MODER_AF(14) | MODER_AF(15);
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GPIOA->OSPEEDR = OSPEED_MED(5) | OSPEED_MED(6) | OSPEED_MED(7) | OSPEED_HI(11) | OSPEED_HI(12)
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| OSPEED_HI(13) | OSPEED_HI(15);
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GPIOA->OTYPER = 0;
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GPIOA->PUPDR = PUPD_PU(8) | PUPD_PU(9) | PUPD_PU(10);
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GPIOB->ODR = 0;
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GPIOB->AFR[0] = AFRf(2, 0) | AFRf(7, 3) | AFRf(10, 5);
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GPIOB->AFR[1] = AFRf(1, 8) | AFRf(7, 10) | AFRf(5, 13) | AFRf(5, 14) | AFRf(5, 15);
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GPIOB->MODER = MODER_AF(0) | MODER_O(1) | MODER_O(2) | MODER_AF(3) | MODER_O(4) | MODER_AF(5) | MODER_O(6)
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| MODER_I(7) | MODER_AF(8) | MODER_I(9) | MODER_AF(10) | MODER_I(11) | MODER_O(12) | MODER_AF(13)
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| MODER_AF(14) | MODER_AF(15);
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GPIOB->OSPEEDR = OSPEED_HI(0) | OSPEED_HI(5) | OSPEED_HI(8) | OSPEED_MED(13) | OSPEED_MED(14) | OSPEED_MED(15);
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GPIOB->OTYPER = 0;
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GPIOB->PUPDR = PUPD_PU(7) | PUPD_PU(9) | PUPD_PU(11);
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GPIOC->ODR = 0;
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GPIOC->AFR[0] = AFRf(7, 4) | AFRf(7, 5) | AFRf(4, 6);
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GPIOC->MODER = MODER_O(0) | MODER_O(1) | MODER_O(2) | MODER_O(3) | MODER_AF(4) | MODER_AF(5) | MODER_AF(6)
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| MODER_I(7) | MODER_O(8) | MODER_O(9) | MODER_I(10) | MODER_I(11) | MODER_O(12) | MODER_I(13)
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| MODER_I(14) | MODER_O(15);
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GPIOC->OSPEEDR = OSPEED_HI(6);
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GPIOC->OTYPER = 0;
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GPIOC->PUPDR = PUPD_PU(7) | PUPD_PU(10) | PUPD_PU(11) | PUPD_PU(13) | PUPD_PU(14);
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GPIOD->ODR = 0;
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GPIOD->AFR[0] = AFRf(7, 0) | AFRf(7, 1);
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GPIOD->AFR[1] = AFRf(2, 12);
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GPIOD->MODER = MODER_AF(0) | MODER_AF(1) | MODER_O(2) | MODER_I(3) | MODER_I(4) | MODER_I(5) | MODER_I(6)
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| MODER_I(7) | MODER_O(8) | MODER_O(9) | MODER_I(10) | MODER_I(11) | MODER_AF(12) | MODER_O(13)
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| MODER_O(14) | MODER_I(15);
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GPIOD->OSPEEDR = OSPEED_HI(0) | OSPEED_HI(1) | OSPEED_HI(12);
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GPIOD->OTYPER = 0;
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GPIOD->PUPDR = PUPD_PU(3) | PUPD_PU(4) | PUPD_PU(5) | PUPD_PU(6) | PUPD_PU(7) | PUPD_PU(10) | PUPD_PU(11)
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| PUPD_PU(15);
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GPIOE->ODR = 0;
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GPIOE->AFR[1] = AFRf(2, 9);
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GPIOE->MODER = MODER_O(0) | MODER_O(1) | MODER_I(2) | MODER_O(3) | MODER_O(4) | MODER_O(5) | MODER_O(6)
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| MODER_I(7) | MODER_I(8) | MODER_AF(9) | MODER_I(10) | MODER_I(11) | MODER_O(12) | MODER_O(13)
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| MODER_I(14) | MODER_I(15);
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GPIOE->OSPEEDR = OSPEED_HI(9);
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GPIOE->OTYPER = 0;
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GPIOE->PUPDR = PUPD_PU(2) | PUPD_PU(7) | PUPD_PU(8) | PUPD_PU(10) | PUPD_PU(11) | PUPD_PU(14) | PUPD_PU(15);
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GPIOF->ODR = 0;
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/*GPIOF->AFR[0] = AFRf(4, 6);*/
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GPIOF->AFR[1] = AFRf(3, 9);
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GPIOF->MODER = MODER_I(6) | MODER_AF(9) | MODER_O(10);
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GPIOF->OSPEEDR = OSPEED_HI(9);
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GPIOF->OTYPER = 0;
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GPIOF->PUPDR = PUPD_PU(6);
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USBPU_OFF();
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}
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#ifndef EBUG
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TRUE_INLINE void iwdg_setup(){
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uint32_t tmout = 16000000;
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 2s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 1250; /* (4) */
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tmout = 16000000;
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while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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#endif
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void hw_setup(){
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gpio_setup();
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#ifndef EBUG
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iwdg_setup();
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#endif
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}
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