mirror of
https://github.com/eddyem/stm32samples.git
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70 lines
2.5 KiB
C
70 lines
2.5 KiB
C
/*
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* This file is part of the pwmtest project.
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* Copyright 2020 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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static inline void gpio_setup(){
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// Enable clocks to the GPIO subsystems (PB for ADC), turn on AFIO clocking to disable SWD/JTAG
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
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// turn off SWJ/JTAG
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// AFIO->MAPR = AFIO_MAPR_SWJ_CFG_DISABLE;
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AFIO->MAPR = AFIO_MAPR_SWJ_CFG_JTAGDISABLE; // for PA15
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// Set led as opendrain output
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GPIOC->CRH |= CRH(13, CNF_ODOUTPUT|MODE_SLOW);
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// USB pullup (PA15) - pushpull output
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GPIOA->CRH = CRH(15, CNF_PPOUTPUT|MODE_SLOW) | CRH(8, CNF_AFPP | MODE_FAST);
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}
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void hw_setup(){
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gpio_setup();
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable TIM1 clocking
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TIM1->ARR = 8; // 9 ticks till UEV
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#ifdef HIGHSPEED
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TIM1->PSC = 7;
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#else
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TIM1->PSC = 6999;
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#endif
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// PWM mode 1 (active->inactive)
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TIM1->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
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// main output
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TIM1->BDTR = TIM_BDTR_MOE;
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// main PWM output
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TIM1->CCER = TIM_CCER_CC1E;
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#ifndef HIGHSPEED
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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#endif
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RCC->AHBENR |= RCC_AHBENR_DMA1EN; // DMA1 clocking
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// memsize 8bit, periphsize 16bit, memincr, circular, mem2periph, half & full transfer interrupt
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DMA1_Channel5->CCR = DMA_CCR_PSIZE_0 | DMA_CCR_CIRC | DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE | DMA_CCR_HTIE;
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DMA1_Channel5->CPAR = (uint32_t)&TIM1->CCR1;
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NVIC_EnableIRQ(DMA1_Channel5_IRQn);
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}
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void iwdg_setup(){
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uint32_t tmout = 16000000;
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RCC->CSR |= RCC_CSR_LSION;
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
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IWDG->KR = IWDG_START;
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IWDG->KR = IWDG_WRITE_ACCESS;
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IWDG->PR = IWDG_PR_PR_1;
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IWDG->RLR = 1250;
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tmout = 16000000;
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while(IWDG->SR){if(--tmout == 0) break;}
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IWDG->KR = IWDG_REFRESH;
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}
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