mirror of
https://github.com/eddyem/stm32samples.git
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179 lines
6.4 KiB
C
179 lines
6.4 KiB
C
/*
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* This file is part of the Chiller project.
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* Copyright 2018 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adc.h"
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/**
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* @brief ADCx_array - arrays for ADC channels with median filtering:
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* ADC1:
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* 0 - Rvar - ADC1_IN1
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* 1 - Rvar/2 - ADC1_IN2
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* 2 - internal Tsens - ADC1_IN16
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* 3 - Vref - ADC1_IN18
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* ADC2:
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* 4 - AIN5/DAC_OUT1 - PA4 - DAC1_OUT1, PA5 - ADC2_IN2
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*/
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static uint16_t ADC_array[NUMBER_OF_ADC_CHANNELS*9];
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TRUE_INLINE void calADC(ADC_TypeDef *chnl){
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// calibration
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// enable voltage regulator
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chnl->CR = 0;
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chnl->CR = ADC_CR_ADVREGEN_0;
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// wait for 10us
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uint16_t ctr = 0;
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while(++ctr < 1000){nop();}
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// ADCALDIF=0 (single channels)
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if((chnl->CR & ADC_CR_ADEN)){
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chnl->CR |= ADC_CR_ADSTP;
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chnl->CR |= ADC_CR_ADDIS;
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}
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chnl->CR |= ADC_CR_ADCAL;
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while((chnl->CR & ADC_CR_ADCAL) != 0 && ++ctr < 0xfff0){};
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chnl->CR = ADC_CR_ADVREGEN_0;
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// enable ADC
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ctr = 0;
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do{
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chnl->CR |= ADC_CR_ADEN;
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}while((chnl->ISR & ADC_ISR_ADRDY) == 0 && ++ctr < 0xfff0);
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}
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TRUE_INLINE void enADC(ADC_TypeDef *chnl){
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// ADEN->1, wait ADRDY
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chnl->CR |= ADC_CR_ADEN;
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uint16_t ctr = 0;
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while(!(chnl->ISR & ADC_ISR_ADRDY) && ++ctr < 0xffff){}
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chnl->CR |= ADC_CR_ADSTART; /* start the ADC conversions */
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}
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/**
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* ADC1 - DMA1_ch1
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* ADC2 - DMA2_ch1
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*/
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// Setup ADC and DAC
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void adc_setup(){
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RCC->AHBENR |= RCC_AHBENR_ADC12EN; // Enable clocking
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ADC12_COMMON->CCR = ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_CKMODE; // enable Tsens and Vref, HCLK/4
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calADC(ADC1);
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calADC(ADC2);
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// ADC1: channels 1,2,16,18; ADC2: channel 2
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ADC1->SMPR1 = ADC_SMPR1_SMP0 | ADC_SMPR1_SMP1;
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ADC1->SMPR2 = ADC_SMPR2_SMP15 | ADC_SMPR2_SMP17;
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// 4 conversions in group: 1->2->16->18
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ADC1->SQR1 = (1<<6) | (2<<12) | (16<<18) | (18<<24) | (4-1);
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ADC2->SMPR1 = ADC_SMPR1_SMP1;
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ADC2->SQR1 = (2<<6) | (1-1);
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// configure DMA for ADC
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RCC->AHBENR |= RCC_AHBENR_DMA1EN | RCC_AHBENR_DMA2EN;
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ADC1->CFGR = ADC_CFGR_CONT | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG;
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ADC2->CFGR = ADC_CFGR_CONT | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG;
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DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR));
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array);
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DMA1_Channel1->CNDTR = NUMBER_OF_ADC1_CHANNELS * 9;
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DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_CIRC;
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DMA1_Channel1->CCR |= DMA_CCR_EN;
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DMA2_Channel1->CPAR = (uint32_t) (&(ADC2->DR));
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DMA2_Channel1->CMAR = (uint32_t)(&ADC_array[ADC2START]);
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DMA2_Channel1->CNDTR = NUMBER_OF_ADC2_CHANNELS * 9;
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DMA2_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_CIRC;
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DMA2_Channel1->CCR |= DMA_CCR_EN;
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enADC(ADC1);
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enADC(ADC2);
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// configure DAC to generate a triangle wave on DAC1_OUT synchronized by TIM6 HW trigger
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/* (1) Enable the peripheral clock of the DAC */
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/* (2) Configure WAVEx at 10,
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Configure mask amplitude for ch1 (MAMP1) at 1011 for a 4095-bits amplitude
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enable the DAC ch1, disable buffer on ch1,
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and select TIM6 as trigger by keeping 000 in TSEL1 */
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RCC->APB1ENR |= RCC_APB1ENR_DAC1EN; /* (1) */
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// DAC simple throw out constant value: output buffer disable, DAC ch1 enable
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DAC->CR = DAC_CR_BOFF1 | DAC_CR_EN1;
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// starting value: 1v
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DAC1->DHR12R1 = 1241;
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#if 0
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DAC->CR |= DAC_CR_WAVE1_1
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| DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0
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| DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_EN1; /* (2) */
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// configure the Timer 6 to generate an external trigger on TRGO each microsecond
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/* (1) Enable the peripheral clock of the TIM6 */
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/* (2) Configure MMS=010 to output a rising edge at each update event */
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/* (3) Select PCLK/2 i.e. 48MHz/2=24MHz */
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/* (4) Set one update event each 1 microsecond */
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/* (5) Enable TIM6 */
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RCC->APB1ENR |= RCC_APB1ENR_TIM6EN; /* (1) */
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TIM6->CR2 |= TIM_CR2_MMS_1; /* (2) */
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TIM6->PSC = 1; /* (3) */
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TIM6->ARR = (uint16_t)24; /* (4) */
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TIM6->CR1 |= TIM_CR1_CEN; /* (5) */
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#endif
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}
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/**
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* @brief getADCval - calculate median value for `nch` channel
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* @param nch - number of channel
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* @return
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*/
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uint16_t getADCval(int nch){
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register uint16_t temp;
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#define PIX_SORT(a,b) { if ((a)>(b)) PIX_SWAP((a),(b)); }
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#define PIX_SWAP(a,b) { temp=(a);(a)=(b);(b)=temp; }
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uint16_t p[9];
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int adval = (nch >= NUMBER_OF_ADC1_CHANNELS) ? NUMBER_OF_ADC2_CHANNELS : NUMBER_OF_ADC1_CHANNELS;
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int addr = (nch >= NUMBER_OF_ADC1_CHANNELS) ? nch - NUMBER_OF_ADC2_CHANNELS + ADC2START: nch;
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for(int i = 0; i < 9; ++i, addr += adval) // first we should prepare array for optmed
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p[i] = ADC_array[addr];
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PIX_SORT(p[1], p[2]) ; PIX_SORT(p[4], p[5]) ; PIX_SORT(p[7], p[8]) ;
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PIX_SORT(p[0], p[1]) ; PIX_SORT(p[3], p[4]) ; PIX_SORT(p[6], p[7]) ;
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PIX_SORT(p[1], p[2]) ; PIX_SORT(p[4], p[5]) ; PIX_SORT(p[7], p[8]) ;
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PIX_SORT(p[0], p[3]) ; PIX_SORT(p[5], p[8]) ; PIX_SORT(p[4], p[7]) ;
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PIX_SORT(p[3], p[6]) ; PIX_SORT(p[1], p[4]) ; PIX_SORT(p[2], p[5]) ;
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PIX_SORT(p[4], p[7]) ; PIX_SORT(p[4], p[2]) ; PIX_SORT(p[6], p[4]) ;
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PIX_SORT(p[4], p[2]) ;
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return p[4];
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#undef PIX_SORT
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#undef PIX_SWAP
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}
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// get voltage @input nch (V)
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float getADCvoltage(int nch){
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float v = getADCval(nch);
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v *= getVdd();
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v /= 4096.f; // 12bit ADC
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return v;
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}
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// return MCU temperature (degrees of celsius)
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float getMCUtemp(){
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// make correction on Vdd value
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int32_t ADval = getADCval(ADC_TS);
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float temperature = (float) *TEMP30_CAL_ADDR - ADval;
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temperature *= (110.f - 30.f);
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temperature /= (float)(*TEMP30_CAL_ADDR - *TEMP110_CAL_ADDR);
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temperature += 30.f;
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return(temperature);
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}
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// return Vdd (V)
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float getVdd(){
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float vdd = ((float) *VREFINT_CAL_ADDR) * 3.3f; // 3.3V
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vdd /= getADCval(ADC_VREF);
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return vdd;
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}
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