mirror of
https://github.com/eddyem/stm32samples.git
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127 lines
5.5 KiB
C
127 lines
5.5 KiB
C
/*
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* This file is part of the canrelay project.
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* Copyright 2021 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "can.h"
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uint16_t CANID = 0xFFFF; // self CAN ID (read @ init)
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// LEDS: 0 - PB12, 1 - PB13, 2 - PB14, 3 - PB15
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GPIO_TypeDef *LEDports[LEDSNO] = {GPIOB, GPIOB, GPIOB, GPIOB};
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const uint32_t LEDpins[LEDSNO] = {1<<12, 1<<13, 1<<14, 1<<15};
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// Buttons: PA2..PA5, pullup
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GPIO_TypeDef *BTNports[BTNSNO] = {GPIOA, GPIOA, GPIOA, GPIOA};
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const uint32_t BTNpins[BTNSNO] = {1<<2, 1<<3, 1<<4, 1<<5};
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// relays: PA0/1
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GPIO_TypeDef *R_ports[RelaysNO] = {GPIOA, GPIOA};
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const uint32_t R_pins[RelaysNO] = {1<<0, 1<<1};
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void gpio_setup(void){
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN;
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// Set LEDS (PB12..15) as output, ADDR (PB0..7) - pullup inputs
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// WARNING! All code here is hardcore!
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pin_set(GPIOB, 0xf<<12); // clear LEDs
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GPIOB->MODER = GPIO_MODER_MODER12_O | GPIO_MODER_MODER13_O | GPIO_MODER_MODER14_O | GPIO_MODER_MODER15_O;
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GPIOB->PUPDR = GPIO_PUPDR0_PU | GPIO_PUPDR1_PU | GPIO_PUPDR2_PU | GPIO_PUPDR3_PU | GPIO_PUPDR4_PU |
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GPIO_PUPDR5_PU | GPIO_PUPDR6_PU | GPIO_PUPDR7_PU;
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// relays (PA0..1) as outputs, buttons (PA2..5) as pullup inputs
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// PA6,7 - ADC IN, PA8..10 - PWM @ TIM1
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GPIOA->MODER = GPIO_MODER_MODER0_O | GPIO_MODER_MODER1_O | GPIO_MODER_MODER6_AI | GPIO_MODER_MODER7_AI |
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GPIO_MODER_MODER8_AF | GPIO_MODER_MODER9_AF | GPIO_MODER_MODER10_AF;
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GPIOA->PUPDR = GPIO_PUPDR2_PU | GPIO_PUPDR3_PU | GPIO_PUPDR4_PU | GPIO_PUPDR5_PU;
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CANID = (~READ_INV_CAN_ADDR()) & CAN_INV_ID_MASK;
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// alternate functions @TIM1 PWM (AF2), PA8..10
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GPIOA->AFR[1] = (2 << (0*4)) | (2 << (1*4)) | (2 << (2*4));
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}
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void iwdg_setup(){
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uint32_t tmout = 16000000;
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 2s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 1250; /* (4) */
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tmout = 16000000;
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while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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void tim1_setup(){
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// TIM1 channels 1..3 - PWM output
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable clocking
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TIM1->PSC = 9; // F=48/10 = 4.8MHz
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TIM1->ARR = 255; // PWM frequency = 4800/256 = 18.75kHz
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// PWM mode 1 (OCxM = 110), preload enable
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TIM1->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE |
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TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE;
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TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE;
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TIM1->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E; // active high (CC1P=0), enable outputs
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TIM1->BDTR |= TIM_BDTR_MOE; // enable main output
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TIM1->CR1 |= TIM_CR1_CEN; // enable timer
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TIM1->EGR |= TIM_EGR_UG; // force update generation
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}
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// pause in milliseconds for some purposes
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void pause_ms(uint32_t pause){
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uint32_t Tnxt = Tms + pause;
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while(Tms < Tnxt) nop();
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}
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#ifndef STM32F072xB
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#warning "Only F072 can jump to bootloader"
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#endif
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void Jump2Boot(){ // for STM32F072
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void (*SysMemBootJump)(void);
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volatile uint32_t addr = 0x1FFFC800;
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// reset systick
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SysTick->CTRL = 0;
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// reset clocks
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RCC->APB1RSTR = RCC_APB1RSTR_CECRST | RCC_APB1RSTR_DACRST | RCC_APB1RSTR_PWRRST | RCC_APB1RSTR_CRSRST |
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RCC_APB1RSTR_CANRST | RCC_APB1RSTR_USBRST | RCC_APB1RSTR_I2C2RST | RCC_APB1RSTR_I2C1RST |
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RCC_APB1RSTR_USART4RST | RCC_APB1RSTR_USART3RST | RCC_APB1RSTR_USART2RST | RCC_APB1RSTR_SPI2RST |
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RCC_APB1RSTR_WWDGRST | RCC_APB1RSTR_TIM14RST | RCC_APB1RSTR_TIM7RST | RCC_APB1RSTR_TIM6RST |
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RCC_APB1RSTR_TIM3RST | RCC_APB1RSTR_TIM2RST;
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RCC->APB2RSTR = RCC_APB2RSTR_DBGMCURST | RCC_APB2RSTR_TIM17RST | RCC_APB2RSTR_TIM16RST | RCC_APB2RSTR_TIM15RST |
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RCC_APB2RSTR_USART1RST | RCC_APB2RSTR_SPI1RST | RCC_APB2RSTR_TIM1RST | RCC_APB2RSTR_ADCRST | RCC_APB2RSTR_SYSCFGRST;
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RCC->AHBRSTR = 0;
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RCC->APB1RSTR = 0;
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RCC->APB2RSTR = 0;
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// Enable the SYSCFG peripheral.
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
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// remap memory to 0 (only for STM32F0)
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SYSCFG->CFGR1 = 0x01; __DSB(); __ISB();
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SysMemBootJump = (void (*)(void)) (*((uint32_t *)(addr + 4)));
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// set main stack pointer
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__set_MSP(*((uint32_t *)addr));
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// jump to bootloader
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SysMemBootJump();
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}
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