mirror of
https://github.com/eddyem/stm32samples.git
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123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/*
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* usart.c
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*
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* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <string.h>
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#include "stm32f1.h"
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#include "usart.h"
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#include "ringbuffer.h"
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extern volatile uint32_t Tms;
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static uint8_t buf[UARTBUFSZO], txbuf[UARTBUFSZO];
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static ringbuffer ringbuf = {.data = buf, .length = UARTBUFSZO};
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static volatile int usart_txrdy = 1; // transmission done
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// transmit current tbuf
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void usart_transmit(){
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if(RB_hasbyte(&ringbuf, '\n') < 0 || !usart_txrdy) return;
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int L = 0, l = 0;
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do{
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l = RB_readto(&ringbuf, '\n', txbuf + L, UARTBUFSZO - L);
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if(l > 0) L += l;
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}while(l > 0 && L < UARTBUFSZO);
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if(L < 1) return;
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usart_txrdy = 0;
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if(L < UARTBUFSZO-1){
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txbuf[L++] = '$'; txbuf[L++] = '\n';
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}
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DMA1_Channel4->CCR &= ~DMA_CCR_EN;
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DMA1_Channel4->CMAR = (uint32_t) txbuf; // mem
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DMA1_Channel4->CNDTR = L;
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DMA1_Channel4->CCR |= DMA_CCR_EN;
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}
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void usart_putchar(const char ch){
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RB_write(&ringbuf, (const uint8_t*)&ch, 1);
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}
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void usart_send(const char *str){
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int l = strlen(str);
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RB_write(&ringbuf, (const uint8_t*)str, l);
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}
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/*
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* USART speed: baudrate = Fck/(USARTDIV)
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* USARTDIV stored in USART->BRR
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*
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* for 72MHz USARTDIV=72000/f(kboud); so for 115200 USARTDIV=72000/115.2=625 -> BRR=0x271
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* 9600: BRR = 7500 (0x1D4C)
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*/
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void usart_setup(){
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uint32_t tmout = 16000000;
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// PA9 - Tx, PA10 - Rx
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_AFIOEN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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GPIOA->CRH |= CRH(9, CNF_AFPP|MODE_NORMAL) | CRH(10, CNF_FLINPUT|MODE_INPUT);
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// USART1 Tx DMA - Channel4 (Rx - channel 5)
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DMA1_Channel4->CPAR = (uint32_t) &USART1->DR; // periph
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DMA1_Channel4->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
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// Tx CNDTR set @ each transmission due to data size
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NVIC_SetPriority(DMA1_Channel4_IRQn, 3);
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NVIC_EnableIRQ(DMA1_Channel4_IRQn);
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NVIC_SetPriority(USART1_IRQn, 0);
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// setup usart1
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USART1->BRR = 72000000 / 4000000;
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USART1->CR1 = USART_CR1_TE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART
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while(!(USART1->SR & USART_SR_TC)){if(--tmout == 0) break;} // polling idle frame Transmission
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USART1->SR = 0; // clear flags
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USART1->CR1 |= USART_CR1_RXNEIE; // allow Rx IRQ
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USART1->CR3 = USART_CR3_DMAT; // enable DMA Tx
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}
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void dma1_channel4_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF4){ // Tx
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DMA1->IFCR = DMA_IFCR_CTCIF4; // clear TC flag
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usart_txrdy = 1;
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}
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}
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char *uhex2str(uint32_t val){
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static char abuf[12] = "0x";
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int npos = 2;
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uint8_t *ptr = (uint8_t*)&val + 3;
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int8_t i, j, z=1;
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for(i = 0; i < 4; ++i, --ptr){
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if(*ptr == 0){ // omit leading zeros
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if(i == 3) z = 0;
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if(z) continue;
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}
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else z = 0;
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for(j = 1; j > -1; --j){
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uint8_t half = (*ptr >> (4*j)) & 0x0f;
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if(half < 10) abuf[npos++] = half + '0';
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else abuf[npos++] = half - 10 + 'a';
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}
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}
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abuf[npos] = 0;
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return abuf;
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}
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