mirror of
https://github.com/eddyem/stm32samples.git
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114 lines
3.8 KiB
C
114 lines
3.8 KiB
C
/*
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* This file is part of the ir-allsky project.
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* Copyright 2025 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "spi.h"
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#include <string.h> // memcpy
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#include "usb_dev.h"
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#ifdef EBUG
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#include "strfunc.h"
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#endif
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spiStatus spi_status = SPI_NOTREADY;
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#define WAITX(x) do{volatile uint32_t wctr = 0; while((x) && (++wctr < 360000)) IWDG->KR = IWDG_REFRESH; if(wctr==360000){ DBG("timeout"); return 0;}}while(0)
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// init SPI @ ~280kHz (36MHz/128)
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void spi_setup(){
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SPI1->CR1 = 0; // clear EN
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SPI1->CR2 = 0;
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// PB3 - SCK, BP4 - MISO, PB5 - MOSI; AF5 @PB3-5
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GPIOB->AFR[0] = (GPIOB->AFR[0] & ~(GPIO_AFRL_AFRL3 | GPIO_AFRL_AFRL4 | GPIO_AFRL_AFRL5)) |
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AFRf(5, 3) | AFRf(5, 4) | AFRf(5, 5);
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GPIOB->MODER = (GPIOB->MODER & (MODER_CLR(3) & MODER_CLR(4) & MODER_CLR(5))) |
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MODER_AF(3) | MODER_AF(4) | MODER_AF(5);
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RCC->APB1RSTR = RCC_APB2RSTR_SPI1RST;
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RCC->APB1RSTR = 0; // clear reset
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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// software slave management (without hardware NSS pin); RX only; Baudrate = 0b110 - fpclk/128
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// CPOL=1, CPHA=1:
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SPI1->CR1 = SPI_CR1_CPOL | SPI_CR1_CPHA | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR | SPI_CR1_BR_2 | SPI_CR1_BR_1;
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// hardware NSS management, RXNE after 8bit; 8bit transfer (default)
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// DS=8bit; RXNE generates after 8bit of data in FIFO;
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SPI1->CR2 = SPI_CR2_SSOE | SPI_CR2_FRXTH | SPI_CR2_DS_2|SPI_CR2_DS_1|SPI_CR2_DS_0;
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spi_status = SPI_READY;
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DBG("SPI works");
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}
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void spi_onoff(uint8_t on){
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if(on) SPI1->CR1 |= SPI_CR1_SPE;
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else SPI1->CR1 &= ~SPI_CR1_SPE;
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}
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// turn off given SPI channel and release GPIO
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void spi_deinit(){
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SPI1->CR1 = 0;
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SPI1->CR2 = 0;
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RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
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GPIOB->AFR[0] = GPIOB->AFR[0] & ~(GPIO_AFRL_AFRL3 | GPIO_AFRL_AFRL4 | GPIO_AFRL_AFRL5);
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GPIOB->MODER = GPIOB->MODER & (MODER_CLR(3) & MODER_CLR(4) & MODER_CLR(5));
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spi_status = SPI_NOTREADY;
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}
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uint8_t spi_waitbsy(){
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WAITX(SPI1->SR & SPI_SR_BSY);
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return 1;
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}
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/**
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* @brief spi_writeread - send data over SPI (change data array with received bytes)
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* @param data - data to write/read
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* @param n - length of data
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* @return 0 if failed
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*/
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uint8_t spi_writeread(uint8_t *data, uint8_t n){
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if(spi_status != SPI_READY || !data || !n){
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DBG("not ready");
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return 0;
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}
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// clear SPI Rx FIFO
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spi_onoff(TRUE);
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for(int i = 0; i < 4; ++i) (void) SPI1->DR;
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for(int x = 0; x < n; ++x){
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WAITX(!(SPI1->SR & SPI_SR_TXE));
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*((volatile uint8_t*)&SPI1->DR) = data[x];
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WAITX(!(SPI1->SR & SPI_SR_RXNE));
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data[x] = *((volatile uint8_t*)&SPI1->DR);
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}
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spi_onoff(FALSE); // turn off SPI
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return 1;
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}
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// read data through SPI
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uint8_t spi_read(uint8_t *data, uint8_t n){
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if(spi_status != SPI_READY || !data || !n){
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DBG("not ready");
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return 0;
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}
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// clear SPI Rx FIFO
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for(int i = 0; i < 4; ++i) (void) SPI1->DR;
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spi_onoff(TRUE);
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for(int x = 0; x < n; ++x){
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WAITX(!(SPI1->SR & SPI_SR_RXNE));
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data[x] = *((volatile uint8_t*)&SPI1->DR);
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}
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spi_onoff(FALSE); // turn off SPI
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return 1;
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}
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