mirror of
https://github.com/eddyem/stm32samples.git
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74 lines
2.6 KiB
C
74 lines
2.6 KiB
C
/*
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* This file is part of the Chiller project.
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* Copyright 2018 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "usart.h"
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volatile uint8_t tim3upd = 0;
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/**
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* @brief gpio_setup - setup GPIOs for external IO
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* GPIO pinout:
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* PA4 - open drain - onboard LED (always ON when board works)
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* PA6, PA7 - TIM3_CH1/CH2 - encoder input
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*/
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static inline void gpio_setup(){
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// Enable clocks to the GPIO subsystems
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOFEN;
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// PA6/7 - AF; PB1 - AF
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GPIOA->MODER = GPIO_MODER_MODER4_O | GPIO_MODER_MODER6_AF | GPIO_MODER_MODER7_AF;
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GPIOA->OTYPER = GPIO_OTYPER_OT_4;
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// alternate functions:
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// PA6 - TIM3_CH1, PA7 - TIM3_CH2
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GPIOA->AFR[0] = (GPIOA->AFR[0] &~ (GPIO_AFRL_AFRL6 | GPIO_AFRL_AFRL7)) \
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| (1 << (6 * 4)) | (1 << (7 * 4));
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}
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static inline void timers_setup(){
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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/* (1) Configure TI1FP1 on TI1 (CC1S = 01)
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configure TI1FP2 on TI2 (CC2S = 01) */
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/* (2) Configure TI1FP1 and TI1FP2 non inverted (CC1P = CC2P = 0, reset value) */
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/* (3) Configure both inputs are active on both rising and falling edges
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(SMS = 011), set external trigger filter to f_DTS/8, N=6 (ETF=1000) */
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/* (4) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
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TIM3->CCMR1 = TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; /* (1)*/
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//TIMx->CCER &= (uint16_t)(~(TIM_CCER_CC21 | TIM_CCER_CC2P); /* (2) */
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TIM3->SMCR = TIM_SMCR_ETF_3 | TIM_SMCR_SMS_0 | TIM_SMCR_SMS_1; /* (3) */
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// enable update interrupt
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TIM3->DIER = TIM_DIER_UIE;
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// set ARR to 79 - generate interrupt each 80 counts (one revolution)
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TIM3->ARR = 79;
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// enable timer
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TIM3->CR1 = TIM_CR1_CEN; /* (4) */
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NVIC_EnableIRQ(TIM3_IRQn);
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}
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void hw_setup(){
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sysreset();
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gpio_setup();
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timers_setup();
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USART1_config();
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}
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void tim3_isr(){
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if(TIM3->SR & TIM_SR_UIF){
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tim3upd = 1;
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}
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TIM3->SR = 0;
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}
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