mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 18:55:13 +03:00
269 lines
9.4 KiB
C
269 lines
9.4 KiB
C
/*
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* This file is part of the Chiller project.
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* Copyright 2018 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adc.h"
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#include "effects.h"
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#include "hardware.h"
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#include "usart.h"
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uint32_t sg90step = SG90DEFSTEP;
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static inline void iwdg_setup(){
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY); /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 1s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 625; /* (4) */
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while(IWDG->SR); /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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static inline void adc_setup(){
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uint16_t ctr = 0; // 0xfff0 - more than 1.3ms
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// Enable clocking
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/* (1) Enable the peripheral clock of the ADC */
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/* (2) Start HSI14 RC oscillator */
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/* (3) Wait HSI14 is ready */
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; /* (1) */
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RCC->CR2 |= RCC_CR2_HSI14ON; /* (2) */
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while ((RCC->CR2 & RCC_CR2_HSI14RDY) == 0 && ++ctr < 0xfff0){}; /* (3) */
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// calibration
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/* (1) Ensure that ADEN = 0 */
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/* (2) Clear ADEN */
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/* (3) Launch the calibration by setting ADCAL */
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/* (4) Wait until ADCAL=0 */
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if ((ADC1->CR & ADC_CR_ADEN) != 0){ /* (1) */
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ADC1->CR &= (uint32_t)(~ADC_CR_ADEN); /* (2) */
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}
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ADC1->CR |= ADC_CR_ADCAL; /* (3) */
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ctr = 0; // ADC calibration time is 5.9us
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while ((ADC1->CR & ADC_CR_ADCAL) != 0 && ++ctr < 0xfff0){}; /* (4) */
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// enable ADC
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ctr = 0;
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do{
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ADC1->CR |= ADC_CR_ADEN;
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}while ((ADC1->ISR & ADC_ISR_ADRDY) == 0 && ++ctr < 0xfff0);
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// configure ADC
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/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
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/* (2) Select the continuous mode */
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/* (3) Select CHSEL0..3 - ADC inputs, 16,17 - t. sensor and vref */
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/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than 17.1us */
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/* (5) Wake-up the VREFINT and Temperature sensor (only for VBAT, Temp sensor and VRefInt) */
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// ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
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ADC1->CFGR1 |= ADC_CFGR1_CONT; /* (2)*/
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ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2 |
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ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17; /* (3)*/
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ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
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ADC->CCR |= ADC_CCR_TSEN | ADC_CCR_VREFEN; /* (5) */
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// configure DMA for ADC
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// DMA for AIN
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/* (1) Enable the peripheral clock on DMA */
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/* (2) Enable DMA transfer on ADC and circular mode */
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/* (3) Configure the peripheral data register address */
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/* (4) Configure the memory address */
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/* (5) Configure the number of DMA tranfer to be performs on DMA channel 1 */
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/* (6) Configure increment, size, interrupts and circular mode */
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/* (7) Enable DMA Channel 1 */
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RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
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ADC1->CFGR1 |= ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG; /* (2) */
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DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
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DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNELS * 9; /* (5) */
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DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_CIRC; /* (6) */
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DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */
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ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversions */
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}
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/**
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* @brief gpio_setup - setup GPIOs for external IO
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* GPIO pinout:
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* PF1 - open drain - ext. LED/laser
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* PA0..PA3 - ADC_IN0..3
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* PA4 - open drain - onboard LED (always ON when board works)
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* PB1, PA6, PA7 - Alt. F. - PWM outputs
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* Registers
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* MODER - input/output/alternate/analog (2 bit)
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* OTYPER - 0 pushpull, 1 opendrain
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* OSPEEDR - x0 low, 01 medium, 11 high
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* PUPDR - no/pullup/pulldown/resr (2 bit)
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* IDR - input
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* ODR - output
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* BSRR - 0..15 - set, 16..31 - reset
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* BRR - 0..15 - reset
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* AFRL/AFRH - alternate functions (4 bit, AF: 0..7); L - AFR0..7, H - ARF8..15
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*/
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static inline void gpio_setup(){
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// Enable clocks to the GPIO subsystems
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOFEN;
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// PA6/7 - AF; PB1 - AF
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GPIOA->MODER = GPIO_MODER_MODER6_AF | GPIO_MODER_MODER7_AF |
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GPIO_MODER_MODER0_AI | GPIO_MODER_MODER1_AI |
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GPIO_MODER_MODER2_AI | GPIO_MODER_MODER3_AI |
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GPIO_MODER_MODER4_O;
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GPIOA->OTYPER = GPIO_OTYPER_OT_4;
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GPIOB->MODER = GPIO_MODER_MODER1_AF;
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//RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // enable syscfg clock for EXTI
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GPIOF->ODR = 1<<1;
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GPIOF->MODER = GPIO_MODER_MODER1_O;
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GPIOF->OTYPER = GPIO_OTYPER_OT_1;
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// alternate functions:
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// PA6 - TIM3_CH1, PA7 - TIM3_CH2, PB1 - TIM3_CH4 (all - AF1)
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GPIOA->AFR[0] = (GPIOA->AFR[0] &~ (GPIO_AFRL_AFRL6 | GPIO_AFRL_AFRL7)) \
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| (1 << (6 * 4)) | (1 << (7 * 4));
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GPIOB->AFR[0] = (GPIOB->AFR[0] &~ (GPIO_AFRL_AFRL1)) \
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| (1 << (1 * 4)) ;
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}
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// change period of PWM
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// MAX freq - 200Hz!!!
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void setTIM3T(uint32_t T){
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if(T < 1000 || T > 65536) return;
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TIM3->ARR = T - 1;
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// step = ampl / freq(Hz) * 3
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sg90step = SG90_AMPL * T;
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sg90step >>= 18; // /262144
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}
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static inline void timers_setup(){
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// timer 3 ch1, 2, 4 PWM for three servos
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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// PWM mode 1 (active -> inactive) on all three channels
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TIM3->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 |
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TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1;
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TIM3->CCMR2 = TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1;
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// frequency
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TIM3->PSC = 47; // 1MHz -> 1us per tick
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// ARR for 8-bit PWM
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TIM3->ARR = 19999; // 50Hz
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// enable main output
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TIM3->BDTR |= TIM_BDTR_MOE;
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// enable PWM output
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TIM3->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC4E;
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TIM3->DIER = TIM_DIER_UIE; //TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC4IE;
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// enable timer & ARR buffering
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TIM3->CR1 |= TIM_CR1_CEN | TIM_CR1_ARPE;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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// DMA for more effects (channel 3 -> TIM3_UP)
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DMA1_Channel3->CPAR = (uint32_t)(&(TIM3->DMAR)); // each writing to DMAR will change next register
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// memsiz 16bit, psiz 32bit, memincrement, from memory, circulate
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DMA1_Channel3->CCR |= DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_1
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| DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_CIRC;
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TIM3->DCR = (1 << 8) | // DBL=1 -- two transfers
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(((uint32_t)&TIM3->CCR1 - (uint32_t)&TIM3->CR1) >> 2); // reg = (DBA + TIM3->CR1)/4
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NVIC_EnableIRQ(TIM3_IRQn);
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}
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void hw_setup(){
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sysreset();
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gpio_setup();
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adc_setup();
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timers_setup();
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USART1_config();
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iwdg_setup();
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}
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static uint32_t target_Val[3] = {SG90_MIDPULSE, SG90_MIDPULSE, SG90_MIDPULSE};
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static uint32_t target_Speed[3] = {SG90DEFSTEP, SG90DEFSTEP, SG90DEFSTEP};
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static uint8_t onpos[3] = {0,0,0};
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volatile uint32_t *addr[3] = {&TIM3->CCR1, &TIM3->CCR2, &TIM3->CCR4};
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int32_t getPWM(int nch){
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return *addr[nch];
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}
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// return current value
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int32_t setPWM(int nch, uint32_t val, uint32_t speed){
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if(nch < 0 || nch > 2) return 0;
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if(speed > 0){
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if(speed > SG90_STEP) speed = SG90_STEP;
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target_Speed[nch] = speed;
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}
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uint8_t ch = 1;
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if(val >= SG90_MINPULSE && val <= SG90_MAXPULSE) target_Val[nch] = val;
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else if(val == 0) target_Val[nch] = SG90_MINPULSE;
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else if(val == 1) target_Val[nch] = SG90_MAXPULSE;
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else if(val == 2) target_Val[nch] = SG90_MIDPULSE;
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else ch = 0;
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if(ch){
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onpos[nch] = 0;
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}
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return *addr[nch];
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}
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uint8_t onposition(int nch){
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return onpos[nch];
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}
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static void chkPWM(int n){
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if(n < 0 || n > 2) return;
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uint32_t cur = *addr[n], tg = target_Val[n];
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if(cur == tg){
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onpos[n] = 1;
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return;
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}
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uint32_t diff = tg - cur;
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int sign = 1;
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if(cur > tg){
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diff = cur - tg;
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sign = -1;
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}
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if(diff > target_Speed[n]) diff = target_Speed[n];
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*addr[n] = cur + sign*diff;
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}
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void tim3_isr(){
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/*
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if(TIM3->SR & TIM_SR_CC1IF){ // 1st channel
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chkPWM(0);
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}
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if(TIM3->SR & TIM_SR_CC2IF){ // 2nd channel
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chkPWM(1);
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}
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if(TIM3->SR & TIM_SR_CC4IF){ // 3rd channel
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chkPWM(2);
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}*/
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if(TIM3->SR & TIM_SR_UIF){
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if(!dma_eff){
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chkPWM(0);
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chkPWM(1);
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chkPWM(2);
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}
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}
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TIM3->SR = 0;
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}
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/*
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void exti0_1_isr(){
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if (EXTI->PR & EXTI_PR_PR1){
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EXTI->PR |= EXTI_PR_PR1; // Clear the pending bit
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;
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}
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}
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*/
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