mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 18:55:13 +03:00
124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
/*
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* main.c
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*
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* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include "hardware.h"
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#include "usart.h"
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#include "can.h"
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volatile uint32_t Tms = 0;
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/* Called when systick fires */
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void sys_tick_handler(void){
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++Tms;
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}
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void iwdg_setup(){
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY); /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 2s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 1250; /* (4) */
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while(IWDG->SR); /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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int main(void){
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uint32_t lastT = 0;
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int L;
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char *txt;
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sysreset();
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SysTick_Config(6000, 1);
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gpio_setup();
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usart_setup();
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iwdg_setup();
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readCANaddr();
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CAN_setup();
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SEND("Greetings! My address is ");
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printu(getCANaddr());
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newline();
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if(RCC->CSR & RCC_CSR_IWDGRSTF){ // watchdog reset occured
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SEND("WDGRESET=1\n");
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}
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if(RCC->CSR & RCC_CSR_SFTRSTF){ // software reset occured
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SEND("SOFTRESET=1\n");
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}
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RCC->CSR |= RCC_CSR_RMVF; // remove reset flags
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while (1){
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IWDG->KR = IWDG_REFRESH; // refresh watchdog
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if(lastT > Tms || Tms - lastT > 499){
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LED_blink(LED0);
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lastT = Tms;
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}
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can_proc();
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if(usartrx()){ // usart1 received data, store in in buffer
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L = usart_getline(&txt);
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char _1st = txt[0];
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if(L == 2 && txt[1] == '\n'){
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L = 0;
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switch(_1st){
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case 'C':
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can_send_dummy();
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break;
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case 'G':
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SEND("Can address: ");
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printu(getCANaddr());
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newline();
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break;
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case 'R':
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NVIC_SystemReset();
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break;
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case 'W':
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SEND("Wait for reboot\n");
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while(1){nop();};
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break;
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default: // help
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SEND(
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"'C' - send dummy byte over CAN\n"
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"'G' - get CAN address\n"
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"'R' - software reset\n"
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"'W' - test watchdog\n"
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);
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break;
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}
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}
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}
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if(L){ // text waits for sending
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while(LINE_BUSY == usart_send(txt, L));
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L = 0;
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}
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}
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return 0;
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}
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