mirror of
https://github.com/eddyem/stm32samples.git
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79 lines
2.5 KiB
C
79 lines
2.5 KiB
C
/*
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* spi.c
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*
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* Copyright 2014 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include "main.h"
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#include "spi.h"
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/*
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* Configure SPI ports
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*/
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/*
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* SPI1 remapped:
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* SCK - PB3
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* MISO - PB4
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* MOSI - PB5
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*
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*/
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void SPI_init(){
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// enable AFIO & other clocking
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rcc_peripheral_enable_clock(&RCC_APB2ENR,
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RCC_APB2ENR_SPI1EN | RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPBEN);
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// remap SPI1 (change pins from PA5..7 to PB3..5); also turn off JTAG
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gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF, AFIO_MAPR_SPI1_REMAP);
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// SCK, MOSI - push-pull output
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gpio_set_mode(GPIO_BANK_SPI1_RE_SCK, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_RE_SCK);
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gpio_set_mode(GPIO_BANK_SPI1_RE_MOSI, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_RE_MOSI);
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// MISO - opendrain in
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gpio_set_mode(GPIO_BANK_SPI1_RE_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI1_RE_MISO);
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_DIV4);
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spi_reset(SPI1);
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/* Set up SPI in Master mode with:
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* for Canon lens SPI settings are: f~78kHz, CPOL=1, CPHA=1
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* Clock baud rate: 1/256 of peripheral clock frequency (APB2, 72MHz/4 = 18MHz) - ~70kHz
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* Clock polarity: CPOL=1, CPHA=1
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* Data frame format: 8-bit
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* Frame format: MSB First
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*/
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spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
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SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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//nvic_enable_irq(NVIC_SPI1_IRQ); // enable SPI interrupt
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spi_enable(SPI1);
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}
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/**
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* send 1 byte blocking
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* return readed byte on success
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*/
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uint8_t spi_write_byte(uint8_t data){
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while(!(SPI_SR(SPI1) & SPI_SR_TXE));
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SPI_DR(SPI1) = data;
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while(!(SPI_SR(SPI1) & SPI_SR_TXE));
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while(!(SPI_SR(SPI1) & SPI_SR_RXNE));
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uint8_t rd = SPI_DR(SPI1);
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while(!(SPI_SR(SPI1) & SPI_SR_TXE));
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while(SPI_SR(SPI1) & SPI_SR_BSY);
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return rd;
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}
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