mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 18:55:13 +03:00
237 lines
7.9 KiB
C
237 lines
7.9 KiB
C
/*
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* This file is part of the si7005 project.
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* Copyright 2021 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "i2c.h"
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#ifdef EBUG
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#include "usb.h"
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#include "proto.h"
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#define DBG(x) do{USB_send(x);}while(0)
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#else
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#define DBG(x)
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#endif
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extern volatile uint32_t Tms;
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// current addresses for read/write (should be set with i2c_set_addr7)
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static uint8_t addr7r = 0, addr7w = 0;
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/*
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* PB10/PB6 - I2C_SCL, PB11/PB7 - I2C_SDA or remap @ PB8 & PB9
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*/
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void i2c_setup(){
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I2C1->CR1 = 0;
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I2C1->SR1 = 0;
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RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
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GPIOB->CRL = (GPIOB->CRL & ~(GPIO_CRL_CNF6 | GPIO_CRL_CNF7)) |
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CRL(6, CNF_AFOD | MODE_NORMAL) | CRL(7, CNF_AFOD | MODE_NORMAL);
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
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I2C1->CR2 = 8; // FREQR=8MHz, T=125ns
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I2C1->TRISE = 9; // (9-1)*125 = 1mks
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I2C1->CCR = 40; // normal mode, 8MHz/2/40 = 100kHz
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I2C1->CR1 |= I2C_CR1_PE; // enable periph
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}
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void i2c_set_addr7(uint8_t addr){
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addr7w = addr << 1;
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addr7r = addr7w | 1;
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}
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// wait for event evt no more than 2 ms
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#define I2C_WAIT(evt) do{ register uint32_t wait4 = Tms + 2; \
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while(Tms < wait4 && !(evt)) IWDG->KR = IWDG_REFRESH; \
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if(!(evt)){ret = I2C_TMOUT; goto eotr;}}while(0)
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// wait for !busy
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#define I2C_LINEWAIT() do{ register uint32_t wait4 = Tms + 2; \
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while(Tms < wait4 && (I2C1->SR2 & I2C_SR2_BUSY)) IWDG->KR = IWDG_REFRESH; \
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if(I2C1->SR2 & I2C_SR2_BUSY){I2C1->CR1 |= I2C_CR1_SWRST; return I2C_LINEBUSY;}\
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}while(0)
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// start writing
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static i2c_status i2c_7bit_startw(){
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i2c_status ret = I2C_LINEBUSY;
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DBG("SR1="); DBG(u2str(I2C1->SR1)); DBG("\n");
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DBG("CR1="); DBG(u2str(I2C1->CR1)); DBG("\n");
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DBG("CR2="); DBG(u2str(I2C1->CR2)); DBG("\n");
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if(I2C1->CR1 != I2C_CR1_PE) i2c_setup();
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if(I2C1->SR1) I2C1->SR1 = 0; // clear NACK and other problems
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(void) I2C1->SR2;
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I2C_LINEWAIT();
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DBG("linew\n");
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I2C1->CR1 |= I2C_CR1_START; // generate start sequence
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("SB\n");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7w; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag (timeout @ NACK)
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DBG("ADDR\n");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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return I2C_NACK;
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}
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DBG("ACK\n");
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(void) I2C1->SR2; // clear ADDR
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ret = I2C_OK;
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eotr:
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return ret;
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}
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/**
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* send one byte in 7bit address mode
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* @param data - data to write
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* @param stop - ==1 to send stop event
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* @return status
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*/
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i2c_status i2c_7bit_send_onebyte(uint8_t data, uint8_t stop){
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i2c_status ret = i2c_7bit_startw();
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if(ret != I2C_OK){
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I2C1->CR1 |= I2C_CR1_STOP;
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goto eotr;
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}
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I2C1->DR = data; // init data send register
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DBG("TxE\n");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_TXE); // wait for TxE (timeout when NACK)
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ret = I2C_OK;
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DBG("OK\n");
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if(stop){
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF); // wait for BTF
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DBG("BTF\n");
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}
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eotr:
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if(stop){
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I2C1->CR1 |= I2C_CR1_STOP; // generate stop event
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}
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return ret;
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}
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// send data array
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i2c_status i2c_7bit_send(const uint8_t *data, int datalen){
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i2c_status ret = i2c_7bit_startw();
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if(ret != I2C_OK){
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I2C1->CR1 |= I2C_CR1_STOP;
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goto eotr;
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}
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for(int i = 0; i < datalen; ++i){
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I2C1->DR = data[i];
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I2C_WAIT(I2C1->SR1 & I2C_SR1_TXE);
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}
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ret = I2C_OK;
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF);
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eotr:
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I2C1->CR1 |= I2C_CR1_STOP;
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return ret;
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}
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i2c_status i2c_7bit_receive_onebyte(uint8_t *data, uint8_t stop){
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i2c_status ret = I2C_LINEBUSY;
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//I2C_LINEWAIT();
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I2C1->CR1 |= I2C_CR1_START; // generate start sequence
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("Rx SB\n");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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DBG("Rx addr\n");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("Rx ack\n");
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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DBG("Rx nak\n");
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ret = I2C_NACK;
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goto eotr;
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}
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(void) I2C1->SR2; // clear ADDR
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DBG("Rx stop\n");
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if(stop) I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait for RxNE
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DBG("Rx OK\n");
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*data = I2C1->DR; // read data & clear RxNE
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ret = I2C_OK;
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eotr:
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return ret;
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}
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i2c_status i2c_7bit_receive_twobytes(uint8_t *data){
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i2c_status ret = I2C_LINEBUSY;
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//I2C_LINEWAIT();
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I2C1->CR1 |= I2C_CR1_START | I2C_CR1_POS | I2C_CR1_ACK; // generate start sequence, set pos & ack
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("2 Rx sb\n");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("2 ADDR\n");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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ret = I2C_NACK;
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goto eotr;
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}
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DBG("2 ACK\n");
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(void) I2C1->SR2; // clear ADDR
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF); // wait for BTF
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DBG("2 BTF\n");
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I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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*data++ = I2C1->DR; *data = I2C1->DR; // read data & clear RxNE
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ret = I2C_OK;
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eotr:
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return ret;
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}
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// receive any amount of bytes
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i2c_status i2c_7bit_receive(uint8_t *data, uint16_t nbytes){
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if(nbytes == 0) return I2C_HWPROBLEM;
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I2C1->SR1 = 0; // clear previous NACK flag & other error flags
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if(nbytes == 1) return i2c_7bit_receive_onebyte(data, 1);
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else if(nbytes == 2) return i2c_7bit_receive_twobytes(data);
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i2c_status ret = I2C_LINEBUSY;
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//I2C_LINEWAIT();
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I2C1->CR1 |= I2C_CR1_START | I2C_CR1_ACK; // generate start sequence, set pos & ack
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("got SB\n");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("send addr\n");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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DBG("NACKed\n");
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ret = I2C_NACK;
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goto eotr;
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}
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DBG("ACKed\n");
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(void) I2C1->SR2; // clear ADDR
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for(uint16_t x = nbytes - 3; x > 0; --x){
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait next byte
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*data++ = I2C1->DR; // get data
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}
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DBG("three left\n");
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// three bytes remain to be read
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait dataN-2
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DBG("dataN-2\n");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF); // wait for BTF
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DBG("BTF\n");
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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*data++ = I2C1->DR; // read dataN-2
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I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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*data++ = I2C1->DR; // read dataN-1
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait next byte
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*data = I2C1->DR; // read dataN
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DBG("got it\n");
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ret = I2C_OK;
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eotr:
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return ret;
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}
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