mirror of
https://github.com/eddyem/stm32samples.git
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84 lines
3.5 KiB
C
84 lines
3.5 KiB
C
/*
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* This file is part of the canbus4bta project.
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* Copyright 2023 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adc.h"
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#include "hardware.h"
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#include "usart.h"
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#include "usbhw.h"
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#ifndef EBUG
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TRUE_INLINE void iwdg_setup(){
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uint32_t tmout = 16000000;
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 2s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 1250; /* (4) */
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tmout = 16000000;
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while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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#endif
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static inline void gpio_setup(){
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RELAY_OFF(); MUL_OFF(0); MUL_OFF(1);
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN;
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// PWM - AF1 @PA7; USB - alternate function 14 @ pins PA11/PA12; SWD - AF0 @PA13/14
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GPIOA->AFR[0] = AFRf(1, 7);
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GPIOA->AFR[1] = AFRf(14, 11) | AFRf(14, 12);
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// PA4 - din (PU in); USB - PA11, PA12; SWDIO - PA13, PA14; PA8 & PA15 - PU in
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GPIOA->PUPDR = (GPIOA->PUPDR & PUPD_CLR(4) & PUPD_CLR(8) & PUPD_CLR(10) & PUPD_CLR(15)) |
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PUPD_PU(4) | PUPD_PU(8) | PUPD_PU(10) | PUPD_PU(15);
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GPIOA->MODER = MODER_AI(0) | MODER_AI(1) | MODER_AI(2) | MODER_AI(3) | MODER_I(4) | MODER_O(5) |
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MODER_O(6) | MODER_AF(7) | MODER_I(8) | MODER_AF(11) |
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MODER_AF(12) | MODER_AF(13) | MODER_AF(14) | MODER_I(15);
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GPIOA->OSPEEDR = OSPEED_HI(4) | OSPEED_MED(7) | OSPEED_MED(9) | OSPEED_MED(10) | OSPEED_HI(11) |
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OSPEED_HI(12) | OSPEED_HI(13) | OSPEED_HI(14);
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// I2C1: AF4 @PB6, PB7; CAN: AF9 @PB8, PB9; SPI2: AF5 @PB12..PB15
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GPIOB->AFR[0] = AFRf(5, 3) | AFRf(5, 4) | AFRf(4, 6) | AFRf(4, 7);
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GPIOB->AFR[1] = AFRf(9, 8) | AFRf(9, 9);
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// PB10,11 - PU in
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GPIOB->PUPDR = PUPD_PU(10) | PUPD_PU(11);
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GPIOB->MODER = MODER_O(0) | MODER_O(1) | MODER_O(2) | MODER_AF(6) | MODER_AF(7) |
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MODER_AF(8) | MODER_AF(9) | MODER_I(10) | MODER_I(11);
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GPIOB->OSPEEDR = OSPEED_HI(3) | OSPEED_HI(4) | OSPEED_HI(6) | OSPEED_HI(7) | OSPEED_HI(8) | OSPEED_HI(9) |
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OSPEED_HI(12) | OSPEED_HI(13) | OSPEED_HI(14) | OSPEED_HI(15);
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GPIOC->MODER = MODER_O(13) | MODER_O(14) | MODER_O(15);
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}
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void hw_setup(){
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gpio_setup();
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adc_setup();
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USB_setup();
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#ifndef EBUG
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iwdg_setup();
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#endif
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}
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