mirror of
https://github.com/eddyem/stm32samples.git
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204 lines
8.0 KiB
C
204 lines
8.0 KiB
C
/*
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* This file is part of the Chiller project.
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* Copyright 2018 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "usart.h"
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#include "adc.h"
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static inline void iwdg_setup(){
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY); /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 1s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 625; /* (4) */
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while(IWDG->SR); /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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static inline void adc_setup(){
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uint16_t ctr = 0; // 0xfff0 - more than 1.3ms
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// Enable clocking
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/* (1) Enable the peripheral clock of the ADC */
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/* (2) Start HSI14 RC oscillator */
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/* (3) Wait HSI14 is ready */
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; /* (1) */
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RCC->CR2 |= RCC_CR2_HSI14ON; /* (2) */
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while ((RCC->CR2 & RCC_CR2_HSI14RDY) == 0 && ++ctr < 0xfff0){}; /* (3) */
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// calibration
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/* (1) Ensure that ADEN = 0 */
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/* (2) Clear ADEN */
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/* (3) Launch the calibration by setting ADCAL */
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/* (4) Wait until ADCAL=0 */
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if ((ADC1->CR & ADC_CR_ADEN) != 0){ /* (1) */
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ADC1->CR &= (uint32_t)(~ADC_CR_ADEN); /* (2) */
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}
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ADC1->CR |= ADC_CR_ADCAL; /* (3) */
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ctr = 0; // ADC calibration time is 5.9us
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while ((ADC1->CR & ADC_CR_ADCAL) != 0 && ++ctr < 0xfff0){}; /* (4) */
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// enable ADC
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ctr = 0;
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do{
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ADC1->CR |= ADC_CR_ADEN;
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}while ((ADC1->ISR & ADC_ISR_ADRDY) == 0 && ++ctr < 0xfff0);
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// configure ADC
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/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
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/* (2) Select the continuous mode */
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/* (3) Select CHSEL0..3 - ADC inputs, 16,17 - t. sensor and vref */
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/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than 17.1us */
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/* (5) Wake-up the VREFINT and Temperature sensor (only for VBAT, Temp sensor and VRefInt) */
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// ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
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ADC1->CFGR1 |= ADC_CFGR1_CONT; /* (2)*/
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ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2 |
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ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17; /* (3)*/
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ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
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ADC->CCR |= ADC_CCR_TSEN | ADC_CCR_VREFEN; /* (5) */
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// configure DMA for ADC
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// DMA for AIN
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/* (1) Enable the peripheral clock on DMA */
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/* (2) Enable DMA transfer on ADC and circular mode */
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/* (3) Configure the peripheral data register address */
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/* (4) Configure the memory address */
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/* (5) Configure the number of DMA tranfer to be performs on DMA channel 1 */
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/* (6) Configure increment, size, interrupts and circular mode */
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/* (7) Enable DMA Channel 1 */
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RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
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ADC1->CFGR1 |= ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG; /* (2) */
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DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
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DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNELS * 9; /* (5) */
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DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_CIRC; /* (6) */
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DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */
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ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversions */
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}
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/**
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* @brief gpio_setup - setup GPIOs for external IO
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* GPIO pinout:
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* PA5 - floating input - Ef of TLE5205
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* PA13 - open drain - IN1 of TLE5205
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* PA14 - open drain - IN2 of TLE5205
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* PF0 - floating input - water level alert
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* PF1 - push-pull - external alarm
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* PA0..PA3 - ADC_IN0..3
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* PA4, PA6, PA7 - PWM outputs
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* Registers
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* MODER - input/output/alternate/analog (2 bit)
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* OTYPER - 0 pushpull, 1 opendrain
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* OSPEEDR - x0 low, 01 medium, 11 high
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* PUPDR - no/pullup/pulldown/resr (2 bit)
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* IDR - input
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* ODR - output
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* BSRR - 0..15 - set, 16..31 - reset
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* BRR - 0..15 - reset
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* AFRL/AFRH - alternate functions (4 bit, AF: 0..7); L - AFR0..7, H - ARF8..15
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*/
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static inline void gpio_setup(){
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// Enable clocks to the GPIO subsystems
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOFEN;
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GPIOA->MODER =
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GPIO_MODER_MODER13_O | GPIO_MODER_MODER14_O |
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GPIO_MODER_MODER4_AF | GPIO_MODER_MODER6_AF |
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GPIO_MODER_MODER7_AF |
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GPIO_MODER_MODER0_AI | GPIO_MODER_MODER1_AI |
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GPIO_MODER_MODER2_AI | GPIO_MODER_MODER3_AI;
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // enable syscfg clock for EXTI
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GPIOA->OTYPER = 3 << 13; // 13/14 opendrain
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GPIOF->MODER = GPIO_MODER_MODER1_O;
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// PB1 - interrupt input
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/* (2) Select Port B for pin 1 external interrupt by writing 0001 in EXTI1*/
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/* (3) Configure the corresponding mask bit in the EXTI_IMR register */
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/* (4) Configure the Trigger Selection bits of the Interrupt line on rising edge*/
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/* (5) Configure the Trigger Selection bits of the Interrupt line on falling edge*/
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SYSCFG->EXTICR[0] = SYSCFG_EXTICR1_EXTI1_PB; /* (2) */
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EXTI->IMR = EXTI_IMR_MR1; /* (3) */
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//EXTI->RTSR = 0x0000; /* (4) */
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EXTI->FTSR = EXTI_FTSR_TR1; /* (5) */
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/* (6) Enable Interrupt on EXTI0_1 */
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/* (7) Set priority for EXTI0_1 */
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NVIC_EnableIRQ(EXTI0_1_IRQn); /* (6) */
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NVIC_SetPriority(EXTI0_1_IRQn, 3); /* (7) */
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// alternate functions:
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// PA4 - TIM14_CH1 (AF4)
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// PA6 - TIM16_CH1 (AF5), PA7 - TIM17_CH1 (AF5)
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GPIOA->AFR[0] = (GPIOA->AFR[0] &~ (GPIO_AFRL_AFRL4 | GPIO_AFRL_AFRL6 | GPIO_AFRL_AFRL7)) \
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| (4 << (4 * 4)) | (5 << (6 * 4)) | (5 << (7 * 4));
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}
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static inline void timers_setup(){
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// timer 14 ch1 - cooler PWM
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// timer 16 ch1 - heater PWM
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// timer 17 ch1 - pump PWM
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_TIM14EN; // enable clocking for timers 3 and 14
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RCC->APB2ENR |= RCC_APB2ENR_TIM16EN | RCC_APB2ENR_TIM17EN; // & timers 16/17
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// PWM mode 1 (active -> inactive)
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TIM14->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
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TIM16->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
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TIM17->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
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// frequency
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TIM14->PSC = 59; // 0.8MHz for 3kHz PWM
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TIM16->PSC = 18749; // 2.56kHz for 10Hz PWM
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TIM17->PSC = 5; // 8MHz for 31kHz PWM
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// ARR for 8-bit PWM
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TIM14->ARR = 254;
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TIM16->ARR = 254;
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TIM17->ARR = 254;
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// start in OFF state
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// TIM14->CCR1 = 0; and so on
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// enable main output
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TIM14->BDTR |= TIM_BDTR_MOE;
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TIM16->BDTR |= TIM_BDTR_MOE;
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TIM17->BDTR |= TIM_BDTR_MOE;
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// enable PWM output
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TIM14->CCER = TIM_CCER_CC1E;
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TIM16->CCER = TIM_CCER_CC1E;
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TIM17->CCER = TIM_CCER_CC1E;
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// enable timers
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TIM14->CR1 |= TIM_CR1_CEN;
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TIM16->CR1 |= TIM_CR1_CEN;
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TIM17->CR1 |= TIM_CR1_CEN;
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}
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void hw_setup(){
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sysreset();
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gpio_setup();
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adc_setup();
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timers_setup();
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USART1_config();
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iwdg_setup();
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}
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/*
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* Flow sensor counter
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*/
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void exti0_1_isr(){
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if (EXTI->PR & EXTI_PR_PR1){
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EXTI->PR |= EXTI_PR_PR1; /* Clear the pending bit */
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++flow_cntr;
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}
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}
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