mirror of
https://github.com/eddyem/stm32samples.git
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120 lines
4.3 KiB
C
120 lines
4.3 KiB
C
/*
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* This file is part of the F0testbrd project.
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* Copyright 2021 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h> // memcpy
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#include "usart.h"
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#include "spi.h"
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// buffers for DMA rx/tx
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static uint8_t inbuff[SPIBUFSZ], outbuff[SPIBUFSZ];
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static uint8_t rxrdy = 0;
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// SPI1 (AF0): PB3 - SCK, PB4 - MISO, PB5 - MOSI; RxDMA - ch2
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void spi_setup(){
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // uncomment in common case
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/* (1) Select AF mode on pins */
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/* (2) AF0 for SPI1 signals */
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GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER3 | GPIO_MODER_MODER4)) |
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GPIO_MODER_MODER3_AF | GPIO_MODER_MODER4_AF; /* (1) */
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GPIOB->AFR[0] = (GPIOB->AFR[0] & ~(GPIO_AFRL_AFRL3 | GPIO_AFRL_AFRL4)); /* (2) */
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// enable clocking
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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// Configure DMA SPI
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/* SPI_RX DMA config */
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/* (1) Peripheral address */
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/* (2) Memory address */
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/* (3) Data size */
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/* (4) Memory increment */
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/* Peripheral to memory */
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/* 8-bit transfer */
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/* Overflow IR */
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DMA1_Channel2->CCR &= ~DMA_CCR_EN;
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DMA1_Channel2->CPAR = (uint32_t)&(SPI1->DR); /* (1) */
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DMA1_Channel2->CMAR = (uint32_t)inbuff; /* (2) */
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DMA1_Channel2->CNDTR = SPIBUFSZ; /* (3) */
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DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_EN; /* (4) */
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/* (5) Peripheral address */
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/* (6) Memory address */
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/* (7) Memory increment */
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/* Memory to peripheral*/
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/* 8-bit transfer */
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/* Transfer complete IT */
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DMA1_Channel3->CCR &= ~DMA_CCR_EN;
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DMA1_Channel3->CPAR = (uint32_t)&(SPI1->DR); /* (5) */
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DMA1_Channel3->CMAR = (uint32_t)outbuff; /* (6) */
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DMA1_Channel3->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_DIR; /* (7) */
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NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0);
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
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/* Configure SPI */
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/* (1) Master selection, BR: Fpclk/256 CPOL and CPHA at zero (rising first edge) */
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/* (1a) software slave management (SSI inactive) */
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/* (2) TX and RX with DMA, 8-bit Rx fifo */
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/* (3) Enable SPI */
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SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR | SPI_CR1_SSM | SPI_CR1_SSI; /* (1) */
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SPI1->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN | SPI_CR2_FRXTH | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
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SPI1->CR1 |= SPI_CR1_SPE; /* (3) */
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SPI_prep_receive();
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}
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// prepare to receive data
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void SPI_prep_receive(){
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DMA1_Channel3->CCR &= ~DMA_CCR_EN;
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DMA1_Channel2->CCR &= ~DMA_CCR_EN;
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rxrdy = 0;
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(void)SPI1->DR; // read DR and SR to clear OVR flag
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(void)SPI1->SR;
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DMA1_Channel2->CNDTR = SPIBUFSZ;
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DMA1_Channel3->CNDTR = SPIBUFSZ;
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DMA1_Channel2->CCR |= DMA_CCR_EN;
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DMA1_Channel3->CCR |= DMA_CCR_EN;
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}
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/**
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* @brief SPI_getdata - get data received by DMA & reload receiver
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* @param buf - buffer for data (with length maxlen) or NULL
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* @param maxlen - (I) - amount of received bytes (or 0 if buffer is empty),
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* (O) - amount of real bytes amount in buffer (could be > maxlen if maxlen < SPIBUFSZ)
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* @return 1 if got data
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*/
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uint8_t SPI_getdata(uint8_t *buf, uint8_t *maxlen){
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if(!rxrdy) return 0;
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//SEND("def\n", 4);
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uint8_t remain = DMA1_Channel2->CNDTR;
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if(remain) return 0;
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rxrdy = 0;
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if(maxlen){
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if(buf && *maxlen) memcpy(buf, inbuff, *maxlen);
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*maxlen = SPIBUFSZ; // bytes received
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}
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return 1;
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}
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void dma1_channel2_3_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF3){
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DMA1->IFCR |= DMA_IFCR_CTCIF3;
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DMA1_Channel3->CCR &= ~DMA_CCR_EN;
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rxrdy = 1;
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}
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if(DMA1->ISR & DMA_ISR_TEIF2){ // receiver overflow
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DMA1->IFCR |= DMA_IFCR_CTEIF2;
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DMA1_Channel2->CCR &= ~DMA_CCR_EN;
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}
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}
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