mirror of
https://github.com/eddyem/stm32samples.git
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95 lines
2.7 KiB
C
95 lines
2.7 KiB
C
/*
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* This file is part of the TETRIS project.
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* Copyright 2021 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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// random numbers generator based on ADC values of Tsens and Vref
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#include "adcrandom.h"
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#define ADC_CHANNELS_NO (2)
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// 16-Tsens, 17-Vref
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static uint8_t const ADCchno[ADC_CHANNELS_NO] = {16, 17};
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uint16_t getADCval(uint8_t ch){
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if(ch >= ADC_CHANNELS_NO) return 0;
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ADC1->SQR3 = ADCchno[ch];
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ADC1->SR = 0;
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// turn ON ADC
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ADC1->CR2 |= ADC_CR2_ADON;
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while(!(ADC1->SR & ADC_SR_EOC)); // wait end of conversion
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return ADC1->DR;
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}
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struct xorshift128_state {
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uint32_t a, b, c, d;
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} state = {0};
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static uint32_t xorshift128(){
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/* Algorithm "xor128" from p. 5 of Marsaglia, "Xorshift RNGs" */
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uint32_t t = state.d;
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uint32_t const s = state.a;
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state.d = state.c;
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state.c = state.b;
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state.b = s;
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t ^= t << 11;
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t ^= t >> 8;
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return state.a = t ^ s ^ (s >> 19);
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}
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static uint32_t rnd(){
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uint32_t r = 0;
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for(int i = 0; i < 32; ++i){
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r <<= 1;
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//r |= (getADCval(0) & 1) ^ (getADCval(1) & 1);
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r |= getADCval(0) & 1;
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}
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return r;
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}
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uint32_t getRand(){
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static uint8_t g = 0;
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if(g++ == 0){
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state.a = rnd();
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state.b = rnd();
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state.c = rnd();
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state.d = rnd();
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}
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return xorshift128();
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}
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void adc_setup(){
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//GPIOC->CRL |= CRL(0, CNF_ANALOG|MODE_INPUT);
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uint32_t ctr = 0;
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// Enable clocking
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
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RCC->CFGR &= ~(RCC_CFGR_ADCPRE);
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RCC->CFGR |= RCC_CFGR_ADCPRE_DIV2; // ADC clock = RCC / 2
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// sampling time - 1.5 cycles for all chanels
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//ADC1->SMPR1 = ADC_SMPR1_SMP10_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP17_0;//channels 10, 16 and 17
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// single mode, enable vref & Tsens; wake up ADC
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ADC1->CR2 |= ADC_CR2_TSVREFE | ADC_CR2_ADON;
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// wait for Tstab - at least 1us
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while(++ctr < 0xff) nop();
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// calibration
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ADC1->CR2 |= ADC_CR2_RSTCAL;
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ctr = 0; while((ADC1->CR2 & ADC_CR2_RSTCAL) && ++ctr < 0xfffff);
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ADC1->CR2 |= ADC_CR2_CAL;
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ctr = 0; while((ADC1->CR2 & ADC_CR2_CAL) && ++ctr < 0xfffff);
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}
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