mirror of
https://github.com/eddyem/stm32samples.git
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108 lines
3.4 KiB
C
108 lines
3.4 KiB
C
/*
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* usart.c
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*
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* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <string.h>
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#include "stm32f1.h"
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#include "usart.h"
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// magick starting sequence
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#define ENC_MAGICK (204)
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// buffers for out ringbuffer and DMA send
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static uint8_t txbuf[UARTBUFSZ];
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static volatile int usart_txrdy = 1; // transmission done
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void usart_send(const uint8_t *buf, int buflen){
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while(!usart_txrdy);
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if(buflen > UARTBUFSZ) buflen = UARTBUFSZ;
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memcpy(txbuf, buf, buflen);
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DMA1_Channel7->CCR &= ~DMA_CCR_EN;
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DMA1_Channel7->CMAR = (uint32_t) txbuf; // mem
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DMA1_Channel7->CNDTR = buflen;
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usart_txrdy = 0;
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DMA1_Channel7->CCR |= DMA_CCR_EN;
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}
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// encoders raw data
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typedef struct __attribute__((packed)){
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uint8_t magick;
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uint32_t encY;
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uint32_t encX;
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uint8_t crc[4];
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} enc_t;
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void usart_send_enc(uint32_t encX, uint32_t encY){
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enc_t edata;
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uint8_t *databuf = (uint8_t*) &edata;
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uint32_t POS_SUM = 0;
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for(int i = 1; i < 9; ++i) POS_SUM += databuf[i];
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edata.crc[0] = POS_SUM >> 8;
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edata.crc[1] = ((0xFFFF - POS_SUM) & 0xFF) - edata.crc[0];
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edata.crc[2] = (0xFFFF - POS_SUM) >> 8;
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edata.crc[3] = 0;
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edata.magick = ENC_MAGICK;
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edata.encX = encX;
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edata.encY = encY;
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usart_send(databuf, sizeof(enc_t));
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}
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/*
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* USART2 speed: baudrate = Fck/(USARTDIV)
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* USARTDIV stored in USART->BRR
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*
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* for 36MHz USARTDIV=36000/f(kboud)
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*/
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void usart_setup(){
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uint32_t tmout = 16000000;
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// PA9 - Tx, PA10 - Rx
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN;
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RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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GPIOA->CRL = (GPIOA->CRL & ~(GPIO_CRL_CNF2 | GPIO_CRL_CNF3)) |
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CRL(2, CNF_AFPP|MODE_NORMAL) | CRL(3, CNF_FLINPUT|MODE_INPUT);
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// USART1 Tx DMA - Channel4 (Rx - channel 5)
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DMA1_Channel7->CPAR = (uint32_t) &USART2->DR; // periph
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DMA1_Channel7->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
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// Tx CNDTR set @ each transmission due to data size
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NVIC_SetPriority(DMA1_Channel7_IRQn, 3);
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NVIC_EnableIRQ(DMA1_Channel7_IRQn);
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//NVIC_SetPriority(USART1_IRQn, 0);
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// setup usart1
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USART2->BRR = 36000000 / 153000;
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USART2->CR1 = USART_CR1_TE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART
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while(!(USART1->SR & USART_SR_TC)){
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IWDG->KR = IWDG_REFRESH;
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if(--tmout == 0) break;
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} // polling idle frame Transmission
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USART2->SR = 0; // clear flags
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USART2->CR1 |= USART_CR1_RXNEIE; // allow Rx IRQ
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USART2->CR3 = USART_CR3_DMAT; // enable DMA Tx
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}
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void dma1_channel7_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF7){ // Tx
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DMA1->IFCR = DMA_IFCR_CTCIF7; // clear TC flag
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usart_txrdy = 1;
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}
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}
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