mirror of
https://github.com/eddyem/stm32samples.git
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88 lines
3.2 KiB
C
88 lines
3.2 KiB
C
/*
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* This file is part of the MAX7219 project.
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* Copyright 2021 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "spi.h"
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#include "hardware.h"
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spiStatus SPI_status = SPI_NOTREADY;
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// 16 bit SPI transfer setup
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void SPI_setup(){
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// setup SPI GPIO - alternate function PP (PA4 - NSS, PA5 - SCK, PA7 - MOSI)
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GPIOA->CRL |= CRL(5, CNF_AFPP|MODE_FAST) | CRL(7, CNF_AFPP|MODE_FAST);
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// configure SPI (transmit only)
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/* Enable the peripheral clock SPI1 */
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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/* Configure SPI1 in master */
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/* (1) Master selection, BR: Fpclk/16
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CPOL and CPHA at zero (rising first edge), 16 bit (DFF) */
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/* (2) TX with DMA, slave select output disabled (software managed - SPI_CR1_SSM | SPI_CR1_SSI?) */
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/* (3) Enable SPI1 */
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SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_DFF; /* (1) */
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SPI1->CR2 = SPI_CR2_TXDMAEN; /* (2) */
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// setup SPI1 DMA
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/* Enable the peripheral clock DMA1 */
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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/* DMA1 Channel3 SPI1_TX config */
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/* (5) Peripheral address */
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/* (7) Memory increment */
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/* Memory to peripheral */
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/* 16-bit transfer (both memory & periph) */
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/* Transfer complete IRQ enable */
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DMA_SPI_Channel->CPAR = (uint32_t)&(SPI1->DR); /* (5) */
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DMA_SPI_Channel->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_TCIE; /* (7) */
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NVIC_SetPriority(DMA1_Channel3_IRQn, 0);
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NVIC_EnableIRQ(DMA1_Channel3_IRQn);
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//NVIC_EnableIRQ(SPI1_IRQn);
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SPI_status = SPI_READY;
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SPI1->CR1 |= SPI_CR1_SPE; /* (3) */
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}
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/**
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* @brief SPI_transmit - transmit data over SPI DMA
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* @param buf - data to transmit
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* @param len - its length
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* @return 0 if all OK
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*/
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uint8_t SPI_transmit(const uint16_t *buf, uint8_t len){
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if(!buf || !len) return 1; // bad data format
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if(SPI_status != SPI_READY) return 2; // spi not ready to transmit data
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DMA_SPI_Channel->CCR &=~ DMA_CCR_EN;
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DMA_SPI_Channel->CMAR = (uint32_t)buf;
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DMA_SPI_Channel->CNDTR = len;
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SPI_status = SPI_BUSY;
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DMA_SPI_Channel->CCR |= DMA_CCR_EN;
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return 0;
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}
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// blocking transmission of one data portion
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void SPI_blocktransmit(const uint16_t data){
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while(SPI_status == SPI_BUSY);
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*(uint16_t *)&(SPI1->DR) = data;
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while(!(SPI1->SR & SPI_SR_TXE));
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while(SPI1->SR & SPI_SR_BSY);
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}
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// SPI DMA Tx interrupt
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void dma1_channel3_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF3){
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DMA1->IFCR |= DMA_IFCR_CTCIF3; // Clear TC flag
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SPI_status = SPI_READY;
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}
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}
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