mirror of
https://github.com/eddyem/stm32samples.git
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417 lines
18 KiB
C
417 lines
18 KiB
C
/*
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* This file is part of the MultiInterface project.
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* Copyright 2022 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stm32f3.h>
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#include <string.h>
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#include "Debug.h"
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#include "hardware.h"
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#include "strfunc.h"
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#include "usart.h"
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#include "usb_descr.h" // InterfacesAmount, IFx, bufsz
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#include "usb_dev.h" // get fresh USB input data
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// !!!!! INDEXED BY INTERFACE NUMBER (just to not check IF6 and IF7) !!!!!
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#define USARTSNO 5
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typedef struct {
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volatile USART_TypeDef *instance; // U[S]ARTx
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uint32_t pclk_freq; // APB1/APB2 frequency
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int16_t UIRQn; // USART IRQ number
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int16_t DIRQn; // DMA Tx IRQ number (for DMA-driven)
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volatile DMA_TypeDef *dma_controller; // DMA1/DMA2 or NULL if not used
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volatile DMA_Channel_TypeDef *dma_rx_channel; // e.g., DMA_Channel_5 or NULL if not used
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volatile DMA_Channel_TypeDef *dma_tx_channel; // e.g., DMA_Channel_4 or NULL if not used
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uint32_t TTCflag; // Tx transfer complete flag
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volatile GPIO_TypeDef *DEport; // if RS485 - DE GPIO port (NULL for RS-232 or RS-422)
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uint32_t DEpin; // -//- pin
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} USART_Config;
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// IF U[S]ART bus freq TxDMA RxDMA DE (if 485)
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// maybe DMA1ch2 would be for SPI1Rx (or SSI should be @ SPI3), in this case USART3 would be interrupt-driven
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// IF1[0]: USART3 APB2 72 MHz DMA1ch2 DMA1ch3 PB14
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// IF2[1]: USART1 APB1 36 MHz DMA1ch4 DMA1ch5 PB0
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// IF3[2]: USART2 APB2 72 MHz DMA1ch7 DMA1ch6 PA1
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// IF4[3]: UART4 APB2 72 MHz DMA2ch5 DMA2ch3
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// IF5[4]: UART5 APB2 72 MHz - - - interrupt-driven
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// IF6[5]: (CAN)
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// IF7[6]: (SPI)
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static const USART_Config UC[USARTSNO] = {
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[0] = {.instance = USART3, .pclk_freq = 36000000, .UIRQn = USART3_IRQn, .DIRQn = DMA1_Channel2_IRQn, .dma_controller = DMA1, .dma_rx_channel = DMA1_Channel3, .dma_tx_channel = DMA1_Channel2, .TTCflag = DMA_ISR_TCIF2, .DEport = GPIOB, .DEpin = 1<<14 },
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[1] = {.instance = USART1, .pclk_freq = 72000000, .UIRQn = USART1_IRQn, .DIRQn = DMA1_Channel4_IRQn, .dma_controller = DMA1, .dma_rx_channel = DMA1_Channel5, .dma_tx_channel = DMA1_Channel4, .TTCflag = DMA_ISR_TCIF4, .DEport = GPIOB, .DEpin = 1<<0 },
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[2] = {.instance = USART2, .pclk_freq = 36000000, .UIRQn = USART2_IRQn, .DIRQn = DMA1_Channel7_IRQn, .dma_controller = DMA1, .dma_rx_channel = DMA1_Channel6, .dma_tx_channel = DMA1_Channel7, .TTCflag = DMA_ISR_TCIF7, .DEport = GPIOA, .DEpin = 1<<1 },
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[3] = {.instance = UART4, .pclk_freq = 36000000, .UIRQn = UART4_IRQn, .DIRQn = DMA2_Channel5_IRQn, .dma_controller = DMA2, .dma_rx_channel = DMA2_Channel3, .dma_tx_channel = DMA2_Channel5, .TTCflag = DMA_ISR_TCIF5 },
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[4] = {.instance = UART5, .pclk_freq = 36000000, .UIRQn = UART5_IRQn }, // no DMA
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};
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// buffers for DMA or interrupt-driven data management
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static uint8_t inbuffers[USARTSNO][DMARXBUFSZ];
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static uint16_t inbufidx[USARTSNO] = {0}; // for interrupt-driven - index of next character (also amount of received bytes)
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static uint8_t outbuffers[USARTSNO][DMATXBUFSZ];
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static uint16_t outbufidx[USARTSNO] = {0}; // index of next char to transmit over interrupt
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static uint16_t outbuflen[USARTSNO] = {0}; // length of data to transmit over interrupt [equal 0 if nothing to send]
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static uint8_t need2send[USARTSNO] = {0}; // flags from IDLE interrupt to send data portion
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static uint8_t TXrdy[USARTSNO] = {1,1,1,1,1}; // TX DMA ready
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static int dma_read_idx[USARTSNO] = {0}; // start of data in DMA inbuffers
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// there's no way to tell recipient about overfull, so we will just "eat" spare data!
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/**
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* @brief usart_config - configure US[A]RT based on usb_LineCoding
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* @param ifNo - interface index [0..4]
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* @param lc (io) - linecoding (modified to real speeds)
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*/
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void usart_config(uint8_t ifNo, usb_LineCoding *lc){
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// all clocking and GPIO config should be done in gpio_setup()!
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if(ifNo >= USARTSNO || UC[ifNo].instance == NULL) return;
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const USART_Config *cfg = &UC[ifNo];
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volatile USART_TypeDef *U = cfg->instance;
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uint32_t peripheral_clock = cfg->pclk_freq;
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// Disable USART while configuring
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U->CR1 = 0;
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U->ICR = 0xFFFFFFFF; // Clear all interrupt flags
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// Assuming oversampling by 16 (default after reset). For higher baud rates you might use by 8.
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U->BRR = peripheral_clock / lc->dwDTERate;
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lc->dwDTERate = peripheral_clock / U->BRR;
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DBGs("New speed: "); DBGs(u2str(lc->dwDTERate)); DBGn();
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// ----- Data bits & Parity -----
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uint32_t cr1 = 0;
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uint32_t data_bits = lc->bDataBits;
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uint32_t parity_type = lc->bParityType;
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// Parity enable/disable and type
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if(parity_type != USB_CDC_NO_PARITY){
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cr1 |= USART_CR1_PCE; // Parity enabled
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if(parity_type == USB_CDC_ODD_PARITY){
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cr1 |= USART_CR1_PS; // Odd parity
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// MARK and SPACE parity are not natively supported; treat as even or ignore.
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}else if(parity_type == USB_CDC_MARK_PARITY || parity_type == USB_CDC_SPACE_PARITY){
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lc->bParityType = USB_CDC_EVEN_PARITY;
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}
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}
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DBGs("Parity: "); DBGch('0'+lc->bParityType); DBGn();
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// Word length (M bits) depends on data bits and parity
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// M[1:0] encoding: 00 = 8 bits, 01 = 9 bits, 10 = 7 bits
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if(cr1 & USART_CR1_PCE){
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// Parity enabled -> total frame length = data bits + 1 parity bit
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if(data_bits == 6){
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// 6 data + 1 parity = 7 bits total -> M=10 (7-bit mode)
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cr1 |= USART_CR1_M1;
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}else if(data_bits == 7){
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// 7 data + 1 parity = 8 bits total -> M=00 (8-bit mode)
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// do nothing
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}else{
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// 8 or 9 data bits with parity would be 9/10 bits total
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// Fallback to 8 data + parity
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cr1 |= USART_CR1_M0;
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lc->bDataBits = 8; // ??? need to be tested
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}
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}else{
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// Parity disabled
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if(data_bits == 7){
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cr1 |= USART_CR1_M1; // M1=1, M0=0 -> 7-bit mode
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}else if(data_bits == 8){
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// do nothing M=00
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}else{
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// Unsupported (5,6 or bits) -> fallback to 8 bits
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lc->bDataBits = 8;
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}
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}
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DBGs("Data bits: "); DBGch('0' + lc->bDataBits); DBGn();
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// ----- Stop bits -----
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uint32_t cr2 = 0;
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switch(lc->bCharFormat){ // usb_LineCoding have no 0.5 stop bits field
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case USB_CDC_1_5_STOP_BITS:
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cr2 |= USART_CR2_STOP_0 | USART_CR2_STOP_1; // 1.5 stop bits -> CR2=11
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break;
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case USB_CDC_2_STOP_BITS:
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cr2 |= USART_CR2_STOP_1; // 2 stop bits -> CR2=10
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break;
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default:
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// do nothing: default to 1 stop bit -> CR2=00
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break;
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}
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DBGs("Stop bits: "); DBGch('0'+lc->bCharFormat); DBGn();
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// Write CR2 (stop bits)
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U->CR2 = cr2;
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// Enable transmitter, receiver, and interrupts (optional)
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cr1 |= USART_CR1_RE | USART_CR1_IDLEIE; // enable idle interrupt to force small portions of data into ringbuffer
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if(cfg->DEport){
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DBG("485 -> RX");
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RX485(cfg->DEport, cfg->DEpin);
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cr1 |= USART_CR1_TCIE;
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}else cr1 |= USART_CR1_TE;
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// ----- DMA -----
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if(cfg->dma_controller){ // DMA-driven
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DBG("DMA-driven");
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volatile DMA_Channel_TypeDef *T = cfg->dma_tx_channel, *R = cfg->dma_rx_channel;
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// Tx DMA
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T->CCR = 0;
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T->CPAR = (uint32_t) &U->TDR;
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T->CCR = DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE;
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// Rx DMA
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R->CCR = 0;
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R->CPAR = (uint32_t) &U->RDR;
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R->CMAR = (uint32_t) inbuffers[ifNo];
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R->CNDTR = DMARXBUFSZ;
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R->CCR = DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_EN; // manage circular buffer in polling
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// enable U[S]ART DMA
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U->CR3 = USART_CR3_DMAT | USART_CR3_DMAR;
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}else{
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DBG("IRQ-driven");
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cr1 |= USART_CR1_RXNEIE; // interrupt-driven
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inbufidx[ifNo] = 0;
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outbufidx[ifNo] = 0;
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}
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U->CR1 = cr1;
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// Wait for the idle frame to complete (optional)
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uint32_t tmout = 16000000;
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while(!(U->ISR & USART_ISR_TC)){
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if (--tmout == 0) break;
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}
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U->ICR = 0xFFFFFFFF; // Clear flags again
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TXrdy[ifNo] = 1;
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DBGch('0' + ifNo);
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DBG("U[S]ART configured");
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}
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// start when received DTR
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void usart_start(uint8_t ifNo){
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if(ifNo >= USARTSNO || UC[ifNo].instance == NULL) return;
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const USART_Config *cfg = &UC[ifNo];
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cfg->instance->CR1 |= USART_CR1_UE;
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NVIC_EnableIRQ(cfg->UIRQn);
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if(cfg->dma_controller){ // reset Rx DMA
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volatile DMA_Channel_TypeDef *R = cfg->dma_rx_channel;
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dma_read_idx[ifNo] = 0;
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R->CCR = 0;
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R->CPAR = (uint32_t) &cfg->instance->RDR;
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R->CMAR = (uint32_t) inbuffers[ifNo];
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R->CNDTR = DMARXBUFSZ;
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R->CCR = DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_EN;
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NVIC_EnableIRQ(cfg->DIRQn);
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}
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DBGch('0' + ifNo);
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DBG("U[S]ART started");
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}
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/**
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* @brief usart_stop - turn off U[S]ART for given interface
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* @param ifNo - interface number
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*/
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void usart_stop(uint8_t ifNo){
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if(ifNo >= USARTSNO || UC[ifNo].instance == NULL) return;
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const USART_Config *cfg = &UC[ifNo];
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cfg->instance->CR1 &= ~USART_CR1_UE;
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if(cfg->dma_controller){
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NVIC_DisableIRQ(cfg->DIRQn);
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}
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NVIC_DisableIRQ(cfg->UIRQn);
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if(cfg->DEport) RX485(cfg->DEport, cfg->DEpin);
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DBGch('0' + ifNo);
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DBG("U[S]ART stopped");
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}
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/**
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* @brief usarts_process - send/receive processing
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* Try to send data from output ringbuffer, check input DMA buffer and full input ringbuffer
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*/
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void usarts_process(){
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for(int i = 0; i < USARTSNO; ++i){ // index by interfaces number!!!
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const USART_Config *cfg = &UC[i];
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if(!(cfg->instance->CR1 & USART_CR1_UE)) continue; // USART disabled
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if(cfg->dma_controller){ // DMA-driven
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// Input data
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int write_idx = DMARXBUFSZ - cfg->dma_rx_channel->CNDTR; // next symbol to be written
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int available = (write_idx - dma_read_idx[i] + DMARXBUFSZ) % DMARXBUFSZ; // length of data available
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if(need2send[i] && available == 0) need2send[i] = 0;
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if(available >= USB_TXBUFSZ || need2send[i]){ // enough data or lonely couple of bytes
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// copy data in one or two chunks (wrap handling)
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if(dma_read_idx[i] + available <= DMARXBUFSZ){ // head before tail
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USB_send(i, &inbuffers[i][dma_read_idx[i]], available);
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}else{ // head after tail - two chunks
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uint32_t first = DMARXBUFSZ - dma_read_idx[i];
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USB_send(i, &inbuffers[i][dma_read_idx[i]], first);
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USB_send(i, inbuffers[i], available - first);
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}
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DBG("USART -> USB over DMA");
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dma_read_idx[i] = write_idx; // update read pointer
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}
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#if 0
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if(DMARXBUFSZ - cfg->dma_rx_channel->CNDTR > DMARXBUFSZ/2 || need2send[i]){
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volatile DMA_Channel_TypeDef *R = cfg->dma_rx_channel;
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R->CCR &= ~DMA_CCR_EN; // pause DMA input transactions
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register int l = DMARXBUFSZ - R->CNDTR;
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if(l){ // have some input data -> send and restart DMA
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DBG("need");
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if(USB_send(i, inbuffers[i], l)){
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DBG("USART -> USB over DMA");
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// restart DMA only in case of succesfull sent or if failed, but have ability of buffer overfull
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R->CMAR = (uint32_t) inbuffers[i];
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R->CNDTR = DMARXBUFSZ;
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need2send[i] = 0;
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}
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}
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R->CCR |= DMA_CCR_EN; // re-enable DMA
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}
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#endif
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// Output data
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if(TXrdy[i]){ // ready to send new data
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int got = USB_receive(i, outbuffers[i], DMATXBUFSZ);
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if(got > 0){ // send next data portion
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volatile DMA_Channel_TypeDef *T = cfg->dma_tx_channel;
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//cfg->dma_controller->IFCR = cfg->TTCflag; // now we can clear TC flag (TC and CTC are the same)
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T->CCR &= ~DMA_CCR_EN;
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T->CMAR = (uint32_t) outbuffers[i];
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T->CNDTR = got;
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if(cfg->DEport){ // switch to Tx
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DBG("485 -> TX");
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TX485(cfg->DEport, cfg->DEpin);
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cfg->instance->CR1 &= ~USART_CR1_RE;
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cfg->instance->CR1 |= USART_CR1_TE;
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}
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TXrdy[i] = 0;
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T->CCR |= DMA_CCR_EN; // start new transmission
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DBG("USB -> USART over DMA");
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}
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}
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}else{ // interrupt-driven
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// Input data
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volatile USART_TypeDef *U = cfg->instance;
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U->CR1 &= ~USART_CR1_RXNEIE; // temporarily disable interrupt
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register int l = inbufidx[i];
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if(l > DMARXBUFSZ/2 || need2send[i]){
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if(l && USB_send(i, inbuffers[i], l)){
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need2send[i] = 0;
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inbufidx[i] = 0;
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DBG("USART -> USB over irq");
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}
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}
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U->CR1 |= USART_CR1_RXNEIE; // restore irq reaction
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// output data
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if(TXrdy[i]){
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int got = USB_receive(i, outbuffers[i], DMATXBUFSZ);
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if(got > 0){
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if(cfg->DEport){ // switch to Tx
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DBG("485 -> TX");
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TX485(cfg->DEport, cfg->DEpin);
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U->CR1 &= ~USART_CR1_RE;
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U->CR1 |= USART_CR1_TE;
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}
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outbufidx[i] = 1; // continue from next symbol
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outbuflen[i] = got;
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TXrdy[i] = 0;
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U->TDR = outbuffers[i][0]; // start transmission
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U->CR1 |= USART_CR1_TXEIE; // enable TXE interrupt
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DBG("USB -> USART over irq");
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}
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}
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}
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}
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}
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// Use this function only for debug purpose
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int usart_send(uint8_t ifNo, const uint8_t *data, int len){
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if(ifNo >= USARTSNO || !data || len < 1) return 0;
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const USART_Config *cfg = &UC[ifNo];
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if(TXrdy[ifNo] == 0 || !(cfg->instance->CR1 & USART_CR1_UE)) return -1; // busy or not active
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if(len > DMATXBUFSZ) len = DMATXBUFSZ;
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memcpy(outbuffers[ifNo], data, len);
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if(cfg->dma_controller){
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volatile DMA_Channel_TypeDef *T = cfg->dma_tx_channel;
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//cfg->dma_controller->IFCR = cfg->TTCflag; // now we can clear TC flag (TC and CTC are the same)
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T->CCR &= ~DMA_CCR_EN;
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T->CMAR = (uint32_t) outbuffers[ifNo];
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T->CNDTR = len;
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if(cfg->DEport){ // switch to Tx
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DBG("485 -> TX");
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TX485(cfg->DEport, cfg->DEpin);
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cfg->instance->CR1 &= ~USART_CR1_RE;
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cfg->instance->CR1 |= USART_CR1_TE;
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}
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TXrdy[ifNo] = 0;
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T->CCR |= DMA_CCR_EN; // start new transmission
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}else{
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volatile USART_TypeDef *U = cfg->instance;
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if(cfg->DEport){ // switch to Tx
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DBG("485 -> TX");
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TX485(cfg->DEport, cfg->DEpin);
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U->CR1 &= ~USART_CR1_RE;
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U->CR1 |= USART_CR1_TE;
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}
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outbufidx[ifNo] = 1; // continue from next symbol
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outbuflen[ifNo] = len;
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U->TDR = outbuffers[ifNo][0]; // start transmission
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U->CR1 |= USART_CR1_TXEIE; // enable TXE interrupt
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}
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return len;
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}
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/**
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* @brief usart_isr - U[S]ART interrupt: IDLE (for DMA-driven) or
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* @param ifno - interface index
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*/
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static void usart_isr(uint8_t ifno){
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const USART_Config *cfg = &UC[ifno];
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volatile USART_TypeDef *U = cfg->instance;
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// for every flag we should also check if it's IRQ active
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if((U->ISR & USART_ISR_RXNE) && (U->CR1 & USART_CR1_RXNEIE)){ // got new byte
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if(inbufidx[ifno] == DMARXBUFSZ) (void) U->RDR; // throw away data: buffer overfull
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else inbuffers[ifno][ inbufidx[ifno]++ ] = U->RDR; // put new byte into buffer
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}
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// IDLE active for both DMA- and interrupt-driven transitions
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if(U->ISR & USART_ISR_IDLE){ // try to send collected data (DMA-driven)
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need2send[ifno] = 1; // seems like data portion is over - try to send it
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U->ICR = USART_ICR_IDLECF;
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}
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if((U->ISR & USART_ISR_TXE) && (U->CR1 & USART_CR1_TXEIE)){ // send next byte if need (interrupt-driven)
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if(outbuflen[ifno] > outbufidx[ifno]){
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U->TDR = outbuffers[ifno][ outbufidx[ifno]++ ];
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}else if(U->CR1 & USART_CR1_TXEIE){
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U->CR1 &= ~USART_CR1_TXEIE; // disable interrupt: no data to send
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TXrdy[ifno] = 1;
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|
}
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}
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if(U->ISR & USART_ISR_TC){ // switch RS-485 to Rx after transmission complete
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|
if(cfg->DEport){
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|
RX485(cfg->DEport, cfg->DEpin);
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|
U->CR1 &= ~USART_CR1_TE;
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|
U->CR1 |= USART_CR1_RE;
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}
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|
U->ICR = USART_ICR_TCCF;
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|
}
|
|
}
|
|
|
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// U[S]ART interrupts (for DMA-driven - only IDLE, for interrupt-driven: RXNE and TXE)
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void usart1_exti25_isr(){ usart_isr(1); }
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void usart2_exti26_isr(){ usart_isr(2); }
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void usart3_exti28_isr(){ usart_isr(0); }
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void uart4_exti34_isr(){ usart_isr(3); }
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void uart5_exti35_isr(){ usart_isr(4); }
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|
|
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// DMA Tx interrupts (to arm ready flag)
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void dma1_channel2_isr(){ TXrdy[0] = 1; DMA1->IFCR = DMA_IFCR_CTCIF2; }
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void dma1_channel4_isr(){ TXrdy[1] = 1; DMA1->IFCR = DMA_IFCR_CTCIF4; }
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void dma1_channel7_isr(){ TXrdy[2] = 1; DMA1->IFCR = DMA_IFCR_CTCIF7; }
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void dma2_channel5_isr(){ TXrdy[3] = 1; DMA2->IFCR = DMA_IFCR_CTCIF5; }
|