mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 10:45:11 +03:00
273 lines
9.1 KiB
C
273 lines
9.1 KiB
C
/*
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* This file is part of the F1_testbrd project.
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* Copyright 2022 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "i2c.h"
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#include "proto.h"
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#include "usart.h"
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#include "usb.h"
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I2C_SPEED curI2Cspeed = LOW_SPEED;
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extern volatile uint32_t Tms;
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volatile uint8_t I2C_scan_mode = 0; // == 1 when I2C is in scan mode
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static uint8_t i2caddr = I2C_ADDREND; // current address for scan mode (not active)
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static uint8_t addr7r = 0, addr7w = 0;
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void i2c_set_addr7(uint8_t addr){
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#ifdef EBUG
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usart_send("Change I2C address to ");
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usart_send(uhex2str(addr));
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usart_putchar('\n');
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#endif
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addr7w = addr << 1;
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addr7r = addr7w | 1;
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}
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/*
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* GPIO Resources: I2C1_SCL - PB6, I2C1_SDA - PB7
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*/
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void i2c_setup(I2C_SPEED speed){
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if(speed >= CURRENT_SPEED){
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speed = curI2Cspeed;
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}else{
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curI2Cspeed = speed;
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}
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I2C1->CR1 = 0;
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I2C1->SR1 = 0;
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RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
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GPIOB->CRL = (GPIOB->CRL & ~(GPIO_CRL_CNF6 | GPIO_CRL_CNF7)) |
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CRL(6, CNF_AFOD | MODE_NORMAL) | CRL(7, CNF_AFOD | MODE_NORMAL);
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
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I2C1->CR2 = 8; // FREQR=8MHz, T=125ns
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I2C1->TRISE = 9; // (9-1)*125 = 1mks
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if(speed == LOW_SPEED){ // 10kHz
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I2C1->CCR = 400;
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}else if(speed == HIGH_SPEED){ // 100kHz
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I2C1->CCR = 40; // normal mode, 8MHz/2/40 = 100kHz
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}else{ // VERYLOW_SPEED - 976.8Hz
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I2C1->CCR = 0xfff;
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}
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I2C1->CR1 = I2C_CR1_PE;
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}
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// wait for event evt no more than 2 ms
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#define I2C_WAIT(evt) do{ register uint32_t wait4 = Tms + 2; \
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while(Tms < wait4 && !(evt)) IWDG->KR = IWDG_REFRESH; \
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if(!(evt)){DBG("WAIT!\n"); return FALSE;}}while(0)
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// wait for !busy
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#define I2C_LINEWAIT() do{ register uint32_t wait4 = Tms + 2; \
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while(Tms < wait4 && (I2C1->SR2 & I2C_SR2_BUSY)) IWDG->KR = IWDG_REFRESH; \
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if(I2C1->SR2 & I2C_SR2_BUSY){I2C1->CR1 |= I2C_CR1_SWRST; DBG("LINE!\n"); return FALSE;}\
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}while(0)
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// start writing, return FALSE @ error
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static int i2c_7bit_startw(){
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if(I2C1->CR1 != I2C_CR1_PE) i2c_setup(CURRENT_SPEED);
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if(I2C1->SR1) I2C1->SR1 = 0; // clear NACK and other problems
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(void) I2C1->SR2;
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I2C_LINEWAIT();
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DBG("linew\n");
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I2C1->CR1 |= I2C_CR1_START; // generate start sequence
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("SB\n");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7w; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag (timeout @ NACK)
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DBG("ADDR\n");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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return FALSE;
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}
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DBG("ACK\n");
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(void) I2C1->SR2; // clear ADDR
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return TRUE;
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}
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/**
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* send one byte in 7bit address mode
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* @param data - data to write
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* @param stop - ==1 to send stop event
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* @return TRUE if OK
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*
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static int i2c_7bit_send_onebyte(uint8_t data, uint8_t stop){
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int ret = i2c_7bit_startw();
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if(!ret){
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I2C1->CR1 |= I2C_CR1_STOP;
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return FALSE;
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}
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I2C1->DR = data; // init data send register
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DBG("TxE\n");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_TXE); // wait for TxE (timeout when NACK)
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DBG("OK\n");
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if(stop){
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF); // wait for BTF
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DBG("BTF\n");
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}
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if(stop){
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I2C1->CR1 |= I2C_CR1_STOP; // generate stop event
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}else{ DBG("No STOP\n");}
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return TRUE;
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}*/
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int i2c_7bit_receive_onebyte(uint8_t *data, uint8_t stop){
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I2C1->CR1 |= I2C_CR1_START; // generate start sequence
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("got SB\n");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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DBG("Rx addr\n");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("Rx ack\n");
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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DBG("Rx nak\n");
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return FALSE;
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}
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(void) I2C1->SR2; // clear ADDR
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DBG("Rx stop\n");
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if(stop) I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait for RxNE
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DBG("Rx OK\n");
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*data = I2C1->DR; // read data & clear RxNE
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return TRUE;
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}
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int i2c_7bit_receive_twobytes(uint8_t *data){
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I2C1->CR1 |= I2C_CR1_START | I2C_CR1_POS | I2C_CR1_ACK; // generate start sequence, set pos & ack
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("2 got sb\n");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("2 ADDR\n");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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return FALSE;
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}
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DBG("2 ACK\n");
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(void) I2C1->SR2; // clear ADDR
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF); // wait for BTF
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DBG("2 BTF\n");
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I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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*data++ = I2C1->DR; *data = I2C1->DR; // read data & clear RxNE
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return TRUE;
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}
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/**
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* write command byte to I2C
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* @param data - bytes to write
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* @param nbytes - amount of bytes to write
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* @param stop - to set STOP
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* @return 0 if error
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*/
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static uint8_t write_i2cs(uint8_t *data, uint8_t nbytes, uint8_t stop){
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int ret = i2c_7bit_startw();
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if(!ret){
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DBG("NACK!\n");
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I2C1->CR1 |= I2C_CR1_STOP;
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return FALSE;
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}
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for(int i = 0; i < nbytes; ++i){
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I2C1->DR = data[i];
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I2C_WAIT(I2C1->SR1 & I2C_SR1_TXE);
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}
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DBG("GOOD\n");
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if(nbytes) I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF);
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if(stop) I2C1->CR1 |= I2C_CR1_STOP;
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return TRUE;
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}
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uint8_t write_i2c(uint8_t *data, uint8_t nbytes){
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return write_i2cs(data, nbytes, 1);
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}
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/**
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* read nbytes of data from I2C line
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* `data` should be an array with at least `nbytes` length
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* @return 1 if all OK, 0 if NACK or no device found
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*/
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static uint8_t read_i2cb(uint8_t *data, uint8_t nbytes, uint8_t wait){
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if(wait) I2C_LINEWAIT();
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I2C1->SR1 = 0; // clear previous NACK flag & other error flags
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if(nbytes == 1) return i2c_7bit_receive_onebyte(data, 1);
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else if(nbytes == 2) return i2c_7bit_receive_twobytes(data);
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I2C1->CR1 |= I2C_CR1_START | I2C_CR1_ACK; // generate start sequence, set pos & ack
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("n got SB\n");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("n send addr\n");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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DBG("n NACKed\n");
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return FALSE;
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}
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DBG("n ACKed\n");
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(void) I2C1->SR2; // clear ADDR
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for(uint16_t x = nbytes - 3; x > 0; --x){
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait next byte
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*data++ = I2C1->DR; // get data
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}
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DBG("n three left\n");
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// three bytes remain to be read
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait dataN-2
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DBG("n dataN-2\n");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF); // wait for BTF
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DBG("n BTF\n");
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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*data++ = I2C1->DR; // read dataN-2
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I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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*data++ = I2C1->DR; // read dataN-1
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait next byte
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*data = I2C1->DR; // read dataN
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DBG("n got it\n");
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return TRUE;
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}
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uint8_t read_i2c(uint8_t *data, uint8_t nbytes){
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return read_i2cb(data, nbytes, 1);
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}
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// read register reg
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uint8_t read_i2c_reg(uint8_t reg, uint8_t *data, uint8_t nbytes){
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if(nbytes == 0) return write_i2cs(®, 1, 1);
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DBG("wrote address, now read data\n");
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if(!write_i2cs(®, 1, 0)) return FALSE;
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return read_i2cb(data, nbytes, 0);
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}
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void i2c_init_scan_mode(){
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i2caddr = 0;
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I2C_scan_mode = 1;
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}
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// return 1 if next addr is active & return in as `addr`
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// if addresses are over, return 1 and set addr to I2C_NOADDR
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// if scan mode inactive, return 0 and set addr to I2C_NOADDR
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int i2c_scan_next_addr(uint8_t *addr){
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*addr = i2caddr;
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if(i2caddr == I2C_ADDREND){
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*addr = I2C_ADDREND;
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I2C_scan_mode = 0;
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return 0;
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}
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i2c_set_addr7(i2caddr++);
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if(!read_i2c_reg(0, NULL, 0)) return FALSE;
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return TRUE;
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}
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