mirror of
https://github.com/eddyem/stm32samples.git
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98 lines
3.7 KiB
C
98 lines
3.7 KiB
C
/*
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* geany_encoding=koi8-r
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* hardware.c - hardware-dependent macros & functions
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*
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* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*
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*/
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#include "hardware.h"
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uint8_t ledsON = 0;
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void gpio_setup(void){
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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// Set LEDS (PB0/1) as output
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pin_set(LED0_port, LED0_pin); // clear LEDs
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pin_set(LED1_port, LED1_pin);
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GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER0 | GPIO_MODER_MODER1)
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) |
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GPIO_MODER_MODER0_O | GPIO_MODER_MODER1_O;
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}
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void iwdg_setup(){
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uint32_t tmout = 16000000;
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 2s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 1250; /* (4) */
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tmout = 16000000;
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while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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// pause in milliseconds for some purposes
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void pause_ms(uint32_t pause){
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uint32_t Tnxt = Tms + pause;
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while(Tms < Tnxt) nop();
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}
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void Jump2Boot(){
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void (*SysMemBootJump)(void);
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volatile uint32_t addr = 0x1FFFC800;
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// reset systick
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SysTick->CTRL = 0;
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// reset clocks
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RCC->APB1RSTR = RCC_APB1RSTR_CECRST | RCC_APB1RSTR_DACRST | RCC_APB1RSTR_PWRRST | RCC_APB1RSTR_CRSRST |
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RCC_APB1RSTR_CANRST | RCC_APB1RSTR_USBRST | RCC_APB1RSTR_I2C2RST | RCC_APB1RSTR_I2C1RST |
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RCC_APB1RSTR_USART4RST | RCC_APB1RSTR_USART3RST | RCC_APB1RSTR_USART2RST | RCC_APB1RSTR_SPI2RST |
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RCC_APB1RSTR_WWDGRST | RCC_APB1RSTR_TIM14RST |
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#ifdef STM32F072xB
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RCC_APB1RSTR_TIM7RST | RCC_APB1RSTR_TIM6RST |
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#endif
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RCC_APB1RSTR_TIM3RST | RCC_APB1RSTR_TIM2RST;
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RCC->APB2RSTR = RCC_APB2RSTR_DBGMCURST | RCC_APB2RSTR_TIM17RST | RCC_APB2RSTR_TIM16RST |
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#ifdef STM32F072xB
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RCC_APB2RSTR_TIM15RST |
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#endif
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RCC_APB2RSTR_USART1RST | RCC_APB2RSTR_SPI1RST | RCC_APB2RSTR_TIM1RST | RCC_APB2RSTR_ADCRST | RCC_APB2RSTR_SYSCFGRST;
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RCC->AHBRSTR = 0;
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RCC->APB1RSTR = 0;
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RCC->APB2RSTR = 0;
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// remap memory to 0 (only for STM32F0)
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SYSCFG->CFGR1 = 0x01; __DSB(); __ISB();
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SysMemBootJump = (void (*)(void)) (*((uint32_t *)(addr + 4)));
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// set main stack pointer
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__set_MSP(*((uint32_t *)addr));
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// jump to bootloader
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SysMemBootJump();
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}
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