mirror of
https://github.com/eddyem/stm32samples.git
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176 lines
7.5 KiB
C
176 lines
7.5 KiB
C
/*
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* geany_encoding=koi8-r
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* hardware.c - hardware-dependent macros & functions
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*
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* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*
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*/
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#include "adc.h"
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#include "hardware.h"
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#include "proto.h"
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void iwdg_setup(){
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uint32_t tmout = 16000000;
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 2s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 1250; /* (4) */
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tmout = 16000000;
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while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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static inline void gpio_setup(){
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// here we turn on clocking for all periph.
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_DMAEN;
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// Set LEDS (PA6-8, PB0/1) as Out & AF (PWM); PA0,1,5 - AIN, PA4 - DAC
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GPIOA->MODER = GPIO_MODER_MODER0_AI | GPIO_MODER_MODER1_AI | GPIO_MODER_MODER4_AI |
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GPIO_MODER_MODER5_AI | GPIO_MODER_MODER6_AF | GPIO_MODER_MODER7_AF | GPIO_MODER_MODER8_AF;
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GPIOB->MODER = GPIO_MODER_MODER0_AF | GPIO_MODER_MODER1_AF;
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// alternate functions: PA6-8: TIM3CH1,2 and TIM1_CH1 (AF1, AF1, AF2)
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// PB0-1: TIM3CH3,4 (AF1, AF1),
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GPIOA->AFR[0] = (1 << (6 * 4)) | (1 << (7 * 4));
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GPIOA->AFR[1] = (2 << (0 * 4));
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GPIOB->AFR[0] = (1 << (0 * 4)) | (1 << (1 * 4));
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}
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// Setup ADC and DAC
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static inline void adc_setup(){
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uint16_t ctr = 0; // 0xfff0 - more than 1.3ms
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// Enable clocking
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/* (1) Enable the peripheral clock of the ADC */
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/* (2) Start HSI14 RC oscillator */
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/* (3) Wait HSI14 is ready */
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; /* (1) */
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RCC->CR2 |= RCC_CR2_HSI14ON; /* (2) */
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while ((RCC->CR2 & RCC_CR2_HSI14RDY) == 0 && ++ctr < 0xfff0){}; /* (3) */
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// calibration
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/* (1) Ensure that ADEN = 0 */
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/* (2) Clear ADEN */
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/* (3) Launch the calibration by setting ADCAL */
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/* (4) Wait until ADCAL=0 */
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if ((ADC1->CR & ADC_CR_ADEN) != 0){ /* (1) */
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ADC1->CR &= (uint32_t)(~ADC_CR_ADEN); /* (2) */
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}
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ADC1->CR |= ADC_CR_ADCAL; /* (3) */
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ctr = 0; // ADC calibration time is 5.9us
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while ((ADC1->CR & ADC_CR_ADCAL) != 0 && ++ctr < 0xfff0){}; /* (4) */
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// enable ADC
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ctr = 0;
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do{
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ADC1->CR |= ADC_CR_ADEN;
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}while ((ADC1->ISR & ADC_ISR_ADRDY) == 0 && ++ctr < 0xfff0);
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// configure ADC to generate a triangle wave on DAC1_OUT synchronized by TIM6 HW trigger
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/* (1) Select HSI14 by writing 00 in CKMODE (reset value) */
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/* (2) Select the continuous mode */
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/* (3) Select CHSEL0,1,5 - ADC inputs, 16,17 - t. sensor and vref */
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/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than 17.1us */
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/* (5) Wake-up the VREFINT and Temperature sensor (only for VBAT, Temp sensor and VRefInt) */
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// ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
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ADC1->CFGR1 |= ADC_CFGR1_CONT; /* (2)*/
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ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17; /* (3)*/
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ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
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ADC->CCR |= ADC_CCR_TSEN | ADC_CCR_VREFEN; /* (5) */
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// configure DMA for ADC
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// DMA for AIN
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/* (1) Enable the peripheral clock on DMA */
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/* (2) Enable DMA transfer on ADC and circular mode */
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/* (3) Configure the peripheral data register address */
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/* (4) Configure the memory address */
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/* (5) Configure the number of DMA tranfer to be performs on DMA channel 1 */
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/* (6) Configure increment, size, interrupts and circular mode */
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/* (7) Enable DMA Channel 1 */
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RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
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ADC1->CFGR1 |= ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG; /* (2) */
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DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
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DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNELS * 9; /* (5) */
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DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_CIRC; /* (6) */
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DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */
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ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversions */
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// DAC
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/* (1) Enable the peripheral clock of the DAC */
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/* (2) Configure WAVEx at 10,
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Configure mask amplitude for ch1 (MAMP1) at 1011 for a 4095-bits amplitude
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enable the DAC ch1, disable buffer on ch1,
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and select TIM6 as trigger by keeping 000 in TSEL1 */
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RCC->APB1ENR |= RCC_APB1ENR_DACEN; /* (1) */
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DAC->CR |= DAC_CR_WAVE1_1
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| DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0
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| DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_EN1; /* (2) */
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// configure the Timer 6 to generate an external trigger on TRGO each microsecond
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/* (1) Enable the peripheral clock of the TIM6 */
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/* (2) Configure MMS=010 to output a rising edge at each update event */
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/* (3) Select PCLK/2 i.e. 48MHz/2=24MHz */
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/* (4) Set one update event each 1 microsecond */
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/* (5) Enable TIM6 */
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RCC->APB1ENR |= RCC_APB1ENR_TIM6EN; /* (1) */
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TIM6->CR2 |= TIM_CR2_MMS_1; /* (2) */
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TIM6->PSC = 1; /* (3) */
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TIM6->ARR = (uint16_t)24; /* (4) */
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TIM6->CR1 |= TIM_CR1_CEN; /* (5) */
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}
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static inline void pwm_setup(){
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// enable clocking for tim1 & tim3
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
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// PWM mode 2
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TIM1->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0;
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TIM3->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 |
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TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_0;
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TIM3->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 |
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TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_0;
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// frequency - 8MHz for 31kHz PWM
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TIM1->PSC = 5;
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TIM3->PSC = 5;
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// ARR for 8-bit PWM
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TIM1->ARR = 254;
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TIM3->ARR = 254;
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TIM1->CCR1 = 127;
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TIM3->CCR1 = 63; TIM3->CCR2 = 127; TIM3->CCR3 = 191; TIM3->CCR4 = 250;
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// enable main output
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TIM1->BDTR |= TIM_BDTR_MOE;
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TIM3->BDTR |= TIM_BDTR_MOE;
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// enable PWM outputs
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TIM1->CCER = TIM_CCER_CC1E;
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TIM3->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E;
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// start timers
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TIM1->CR1 |= TIM_CR1_CEN;
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TIM3->CR1 |= TIM_CR1_CEN;
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}
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void hw_setup(){
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gpio_setup();
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adc_setup();
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pwm_setup();
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}
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