mirror of
https://github.com/eddyem/stm32samples.git
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195 lines
8.4 KiB
C
195 lines
8.4 KiB
C
/*
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* geany_encoding=koi8-r
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* hardware.c - hardware-dependent macros & functions
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*
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* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*
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*/
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#include "adc.h"
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#include "hardware.h"
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uint8_t ledsON = 0;
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void adc_setup(){
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uint16_t ctr = 0; // 0xfff0 - more than 1.3ms
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ADC1->CR &= ~ADC_CR_ADEN;
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DMA1_Channel1->CCR &= ~DMA_CCR_EN;
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // Enable the peripheral clock of the ADC
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RCC->CR2 |= RCC_CR2_HSI14ON; // Start HSI14 RC oscillator
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while ((RCC->CR2 & RCC_CR2_HSI14RDY) == 0 && ++ctr < 0xfff0){}; // Wait HSI14 is ready
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// calibration
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if(ADC1->CR & ADC_CR_ADEN){ // Ensure that ADEN = 0
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ADC1->CR &= (uint32_t)(~ADC_CR_ADEN); // Clear ADEN
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}
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ADC1->CR |= ADC_CR_ADCAL; // Launch the calibration by setting ADCAL
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ctr = 0; // ADC calibration time is 5.9us
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while(ADC1->CR & ADC_CR_ADCAL && ++ctr < 0xfff0); // Wait until ADCAL=0
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// enable ADC
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ctr = 0;
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do{
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ADC1->CR |= ADC_CR_ADEN;
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}while((ADC1->ISR & ADC_ISR_ADRDY) == 0 && ++ctr < 0xfff0);
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// configure ADC
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ADC1->CFGR1 |= ADC_CFGR1_CONT; // Select the continuous mode
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ADC1->CHSELR = ADC_CHSELR_CHSEL0 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL2 |
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ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL4 | ADC_CHSELR_CHSEL5 |
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ADC_CHSELR_CHSEL16 | ADC_CHSELR_CHSEL17; // Select CHSEL0..5 - ADC inputs, 16,17 - t. sensor and vref
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ADC1->SMPR |= ADC_SMPR_SMP; // Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than 17.1us
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ADC->CCR |= ADC_CCR_TSEN | ADC_CCR_VREFEN; // Wake-up the VREFINT and Temperature sensor
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// configure DMA for ADC
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RCC->AHBENR |= RCC_AHBENR_DMA1EN; // Enable the peripheral clock on DMA
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ADC1->CFGR1 |= ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG; // Enable DMA transfer on ADC and circular mode
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DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); // Configure the peripheral data register address
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DMA1_Channel1->CMAR = (uint32_t)(ADC_array); // Configure the memory address
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DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNELS * 9; // Configure the number of DMA tranfer to be performs on DMA channel 1
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DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_CIRC; // Configure increment, size, interrupts and circular mode
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DMA1_Channel1->CCR |= DMA_CCR_EN; // Enable DMA Channel 1
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ADC1->CR |= ADC_CR_ADSTART; // start the ADC conversions
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}
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static inline void gpio_setup(void){
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN;
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OFF(BUZZER); OFF(RELAY); OFF(COOLER0); OFF(COOLER1);
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// All outputs are pullups
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// PA0..5 - ADC, PA6, PA8..10 - timers (PA6, PA7 - pullup, PA7 - exti), PA14 - buzzer
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GPIOA->MODER = GPIO_MODER_MODER0_AI | GPIO_MODER_MODER1_AI |
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GPIO_MODER_MODER2_AI | GPIO_MODER_MODER3_AI |
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GPIO_MODER_MODER4_AI | GPIO_MODER_MODER5_AI |
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GPIO_MODER_MODER6_AF | GPIO_MODER_MODER8_AF |
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GPIO_MODER_MODER9_AF | GPIO_MODER_MODER10_AF|
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GPIO_MODER_MODER14_O;
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GPIOA->PUPDR = GPIO_PUPDR6_PU | GPIO_PUPDR7_PU;
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// EXTI @ PA7
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SYSCFG->EXTICR[1] = SYSCFG_EXTICR2_EXTI7_PA; // PORTA for EXTI
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EXTI->IMR = EXTI_IMR_MR7; // select pin 7
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EXTI->RTSR = EXTI_RTSR_TR7; // rising edge @ pin 7
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NVIC_EnableIRQ(EXTI4_15_IRQn); // enable interrupt
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NVIC_SetPriority(EXTI4_15_IRQn, 4); // set low priority
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// PB4/5 - cooler, PB14/15 - buttons (pullup)
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GPIOB->MODER = GPIO_MODER_MODER4_O | GPIO_MODER_MODER5_O;
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GPIOB->PUPDR = GPIO_PUPDR14_PU | GPIO_PUPDR15_PU;
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// PC13 - relay
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GPIOC->MODER = GPIO_MODER_MODER13_O;
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/* Alternate functions:
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* PA6 - TIM3_CH1 AF1
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* PA8 - TIM1_CH1 AF2
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* PA9 - TIM1_CH2 AF2
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* PA10 - TIM1_CH3 AF2
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*/
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GPIOA->AFR[0] = (1 << (6*4));
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GPIOA->AFR[1] = (2 << (0*4)) | (2 << (1*4)) | (2 << (2*4));
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}
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static inline void timers_setup(){
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// TIM1 channels 1..3 - PWM output
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable clocking
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TIM1->PSC = 19; // F=48/20 = 2.4MHz
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TIM1->ARR = 100; // PWM frequency = 2.4/101 = 23.76kHz
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TIM1->CCR1 = 20; // near 20% PWM duty cycle
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TIM1->CCR2 = 20; // near 20% PWM duty cycle
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//TIM1->CCR3 = 20; // CCR3 is zero - should be activated on cooler3 settings
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// PWM mode 1 (OCxM = 110), preload enable
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TIM1->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE |
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TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE;
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TIM1->CCMR2 = TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE;
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TIM1->CCER = TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E; // active high (CC1P=0), enable outputs
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TIM1->BDTR |= TIM_BDTR_MOE; // enable main output
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TIM1->CR1 |= TIM_CR1_CEN; // enable timer
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TIM1->EGR |= TIM_EGR_UG; // force update generation
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// TIM3 channel 1 - external counter on channel1
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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TIM3->SMCR = TIM_SMCR_TS_2 | TIM_SMCR_TS_0 | TIM_SMCR_SMS; // TS=101, SMS=111 - external trigger on input1
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TIM3->CCMR1 = TIM_CCMR1_CC1S_0; // CC1 is input mapped on channel TI1
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TIM3->CR1 = TIM_CR1_CEN;
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}
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void HW_setup(){
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gpio_setup();
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adc_setup();
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timers_setup();
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}
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void iwdg_setup(){
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uint32_t tmout = 16000000;
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 2s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 1250; /* (4) */
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tmout = 16000000;
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while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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// pause in milliseconds for some purposes
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void pause_ms(uint32_t pause){
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uint32_t Tnxt = Tms + pause;
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while(Tms < Tnxt) nop();
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}
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void Jump2Boot(){
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void (*SysMemBootJump)(void);
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volatile uint32_t addr = SystemMem;
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// reset systick
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SysTick->CTRL = 0;
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// reset clocks
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RCC->APB1RSTR = RCC_APB1RSTR_CECRST | RCC_APB1RSTR_DACRST | RCC_APB1RSTR_PWRRST | RCC_APB1RSTR_CRSRST |
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RCC_APB1RSTR_CANRST | RCC_APB1RSTR_USBRST | RCC_APB1RSTR_I2C2RST | RCC_APB1RSTR_I2C1RST |
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RCC_APB1RSTR_USART4RST | RCC_APB1RSTR_USART3RST | RCC_APB1RSTR_USART2RST | RCC_APB1RSTR_SPI2RST |
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RCC_APB1RSTR_WWDGRST | RCC_APB1RSTR_TIM14RST |
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#ifdef STM32F072xB
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RCC_APB1RSTR_TIM7RST | RCC_APB1RSTR_TIM6RST |
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#endif
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RCC_APB1RSTR_TIM3RST | RCC_APB1RSTR_TIM2RST;
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RCC->APB2RSTR = RCC_APB2RSTR_DBGMCURST | RCC_APB2RSTR_TIM17RST | RCC_APB2RSTR_TIM16RST |
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#ifdef STM32F072xB
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RCC_APB2RSTR_TIM15RST |
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#endif
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RCC_APB2RSTR_USART1RST | RCC_APB2RSTR_SPI1RST | RCC_APB2RSTR_TIM1RST | RCC_APB2RSTR_ADCRST | RCC_APB2RSTR_SYSCFGRST;
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RCC->AHBRSTR = 0;
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RCC->APB1RSTR = 0;
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RCC->APB2RSTR = 0;
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// remap memory to 0 (only for STM32F0)
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SYSCFG->CFGR1 = 0x01; __DSB(); __ISB();
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SysMemBootJump = (void (*)(void)) (*((uint32_t *)(addr + 4)));
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// set main stack pointer
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__set_MSP(*((uint32_t *)addr));
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// jump to bootloader
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SysMemBootJump();
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}
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void exti4_15_isr(){
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EXTI->PR |= EXTI_PR_PR7; // clear pending bit
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++Cooler1RPM;
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}
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