mirror of
https://github.com/eddyem/stm32samples.git
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113 lines
4.1 KiB
C
113 lines
4.1 KiB
C
/*
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* This file is part of the Stepper project.
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* Copyright 2020 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "proto.h"
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#include "spi.h"
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#include <string.h> // memcpy
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// buffers for DMA rx/tx
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static uint8_t inbuff[SPIBUFSZ], outbuf[SPIBUFSZ];
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spiStatus SPI_status = SPI_NOTREADY;
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//SPI: PA5 - SCK, PA6 -MISO, PA7 - MOSI, PC14 - ~CS
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void spi_setup(){
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/* (1) Select AF mode on PA5, PA6, PA7 */
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/* (2) AF0 for SPI1 signals */
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GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER5 | GPIO_MODER_MODER6 | GPIO_MODER_MODER7)) |
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(GPIO_MODER_MODER5_AF | GPIO_MODER_MODER6_AF | GPIO_MODER_MODER7_AF); /* (1) */
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GPIOA->AFR[0] = (GPIOA->AFR[0] & ~(GPIO_AFRL_AFRL5 | GPIO_AFRL_AFRL6 | GPIO_AFRL_AFRL7)); /* (2) */
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// Configure DMA SPI
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/* Enable the peripheral clock DMA11 */
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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/* DMA1 Channel2 SPI1_RX config */
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/* (1) Peripheral address */
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/* (2) Memory address */
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/* (3) Data size */
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/* (4) Memory increment */
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/* Peripheral to memory */
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/* 8-bit transfer */
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DMA1_Channel2->CPAR = (uint32_t)&(SPI1->DR); /* (1) */
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DMA1_Channel2->CMAR = (uint32_t)inbuff; /* (2) */
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DMA1_Channel2->CNDTR = SPIBUFSZ; /* (3) */
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DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_EN; /* (4) */
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/* DMA1 Channel3 SPI1_TX config */
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/* (5) Peripheral address */
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/* (6) Memory address */
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/* (7) Memory increment */
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/* Memory to peripheral*/
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/* 8-bit transfer */
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/* Transfer complete IT */
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DMA1_Channel3->CPAR = (uint32_t)&(SPI1->DR); /* (5) */
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DMA1_Channel3->CMAR = (uint32_t)outbuf; /* (6) */
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DMA1_Channel3->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_DIR; /* (7) */
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/* Configure IT */
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/* (8) Set priority for DMA1_Channel2_3_IRQn */
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/* (9) Enable DMA1_Channel2_3_IRQn */
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NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0); /* (8) */
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); /* (9) */
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// configure SPI (transmit only)
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/* Enable the peripheral clock SPI1 */
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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/* Configure SPI1 in master */
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/* (1) Master selection, BR: Fpclk/256 CPOL and CPHA at zero (rising first edge) */
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/* (2) TX and RX with DMA, slave select output enabled, 8-bit Rx fifo */
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/* (3) Enable SPI1 */
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SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR; /* (1) */
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SPI1->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
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SPI1->CR1 |= SPI_CR1_SPE; /* (3) */
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SPI_status = SPI_READY;
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}
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void dma1_channel2_3_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF3){
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DMA1->IFCR |= DMA_IFCR_CTCIF3;
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SPI_status = SPI_READY;
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#ifdef EBUG
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SEND("rxCNDTR="); printu(DMA1_Channel2->CNDTR); SEND(", txCNDTR="); printu(DMA1_Channel3->CNDTR); newline(); sendbuf();
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#endif
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}
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}
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/**
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* @brief SPI_transmit - transmit data over SPI DMA
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* @param buf - data to transmit
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* @param len - its length
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* @return 0 if all OK
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*/
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uint8_t SPI_transmit(const uint8_t *buf, uint8_t len){
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if(!buf || !len || len > SPIBUFSZ) return 1; // bad data format
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if(SPI_status != SPI_READY) return 2; // spi not ready to transmit data
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DMA1_Channel3->CCR &=~ DMA_CCR_EN;
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memcpy(outbuf, buf, len);
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DMA1_Channel3->CNDTR = len;
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SPI_status = SPI_BUSY;
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#ifdef EBUG
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SEND("SPI tx "); printu(len); SEND(" bytes\n"); sendbuf();
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#endif
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DMA1_Channel3->CCR |= DMA_CCR_EN;
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return 0;
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}
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/*
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static uint8_t *SPI_receive(uint8_t *len){
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if(!len || SPI_status != SPI_READY) return NULL;
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*len =
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}*/
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