mirror of
https://github.com/eddyem/stm32samples.git
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220 lines
6.7 KiB
C
220 lines
6.7 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>,
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* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "vector.h"
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typedef void (*vector_table_entry_t)(void);
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typedef void (*funcp_t) (void);
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void main(void);
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void blocking_handler(void);
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void null_handler(void);
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/* Initialization template for the interrupt vector table. This definition is
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* used by the startup code generator (vector.c) to set the initial values for
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* the interrupt handling routines to the chip family specific _isr weak
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* symbols. */
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#if defined STM32G0
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#include "stm32g0xx.h"
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#define NVIC_WWDG_IRQ 0
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#define NVIC_RTC_IRQ 2
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#define NVIC_FLASH_IRQ 3
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#define NVIC_RCC_IRQ 4
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#define NVIC_EXTI0_1_IRQ 5
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#define NVIC_EXTI2_3_IRQ 6
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#define NVIC_EXTI4_15_IRQ 7
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#define NVIC_DMA1_CHANNEL1_IRQ 9
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#define NVIC_DMA1_CHANNEL2_3_IRQ 10
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#define NVIC_DMAMUX_IRQ 11
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#define NVIC_ADC_COMP_IRQ 12
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#define NVIC_TIM1_BRK_UP_TRG_COM_IRQ 13
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#define NVIC_TIM1_CC_IRQ 14
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#define NVIC_TIM3_4_IRQ 16
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#define NVIC_TIM6_DAC_IRQ 17
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#define NVIC_TIM7_IRQ 18
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#define NVIC_TIM14_IRQ 19
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#define NVIC_TIM15_IRQ 20
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#define NVIC_TIM16_IRQ 21
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#define NVIC_TIM17_IRQ 22
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#define NVIC_I2C1_IRQ 23
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#define NVIC_I2C2_3_IRQ 24
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#define NVIC_SPI1_IRQ 25
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#define NVIC_SPI2_3_IRQ 26
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#define NVIC_USART1_IRQ 27
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#define NVIC_USART2_IRQ 28
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#define NVIC_USART3_6_IRQ 29
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#define NVIC_CEC_CAN_IRQ 30
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#define NVIC_USB_IRQ 31
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#define NVIC_IRQ_COUNT 32
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#define IRQ_HANDLERS \
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[NVIC_WWDG_IRQ] = wwdg_isr, \
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[NVIC_RTC_IRQ] = rtc_isr, \
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[NVIC_FLASH_IRQ] = flash_isr, \
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[NVIC_RCC_IRQ] = rcc_isr, \
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[NVIC_EXTI0_1_IRQ] = exti0_1_isr, \
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[NVIC_EXTI2_3_IRQ] = exti2_3_isr, \
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[NVIC_EXTI4_15_IRQ] = exti4_15_isr, \
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[NVIC_DMA1_CHANNEL1_IRQ] = dma1_channel1_isr, \
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[NVIC_DMA1_CHANNEL2_3_IRQ] = dma1_channel2_3_isr, \
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[NVIC_DMAMUX_IRQ] = dmamux_isr, \
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[NVIC_ADC_COMP_IRQ] = adc_comp_isr, \
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[NVIC_TIM1_BRK_UP_TRG_COM_IRQ] = tim1_brk_up_trg_com_isr, \
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[NVIC_TIM1_CC_IRQ] = tim1_cc_isr, \
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[NVIC_TIM3_4_IRQ] = tim3_4_isr, \
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[NVIC_TIM6_DAC_IRQ] = tim6_dac_isr, \
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[NVIC_TIM7_IRQ] = tim7_isr, \
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[NVIC_TIM14_IRQ] = tim14_isr, \
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[NVIC_TIM15_IRQ] = tim15_isr, \
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[NVIC_TIM16_IRQ] = tim16_isr, \
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[NVIC_TIM17_IRQ] = tim17_isr, \
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[NVIC_I2C1_IRQ] = i2c1_isr, \
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[NVIC_I2C2_3_IRQ] = i2c2_3_isr, \
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[NVIC_SPI1_IRQ] = spi1_isr, \
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[NVIC_SPI2_3_IRQ] = spi2_3_isr, \
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[NVIC_USART1_IRQ] = usart1_isr, \
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[NVIC_USART2_IRQ] = usart2_isr, \
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[NVIC_USART3_6_IRQ] = usart3_6_isr, \
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[NVIC_CEC_CAN_IRQ] = cec_can_isr, \
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[NVIC_USB_IRQ] = usb_isr
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#else
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#error "Not supported STM32 family"
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#endif
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typedef struct {
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unsigned int *initial_sp_value; /**< Initial stack pointer value. */
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vector_table_entry_t reset;
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vector_table_entry_t nmi;
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vector_table_entry_t hard_fault;
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vector_table_entry_t reserved1[7];
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vector_table_entry_t sv_call;
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vector_table_entry_t reserved2[2];
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vector_table_entry_t pend_sv;
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vector_table_entry_t systick;
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vector_table_entry_t irq[NVIC_IRQ_COUNT];
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} vector_table_t;
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extern unsigned _stack;
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vector_table_t vector_table __attribute__ ((section(".vector_table"))) = {
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.initial_sp_value = &_stack,
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.reset = reset_handler,
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.nmi = nmi_handler,
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.hard_fault = hard_fault_handler,
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/* Those are defined only on CM3 or CM4 */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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.memory_manage_fault = mem_manage_handler,
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.bus_fault = bus_fault_handler,
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.usage_fault = usage_fault_handler,
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.debug_monitor = debug_monitor_handler,
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#endif
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.sv_call = sv_call_handler,
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.pend_sv = pend_sv_handler,
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.systick = sys_tick_handler,
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.irq = {
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IRQ_HANDLERS
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}
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};
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void WEAK __attribute__ ((naked)) __attribute__ ((noreturn)) reset_handler(void){
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extern char _sdata; // .data section start
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extern char _edata; // .data section end
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extern char _sbss; // .bss section start
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extern char _ebss; // .bss section end
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extern char _ldata; // .data load address
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char *dst = &_sdata;
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char *src = &_ldata;
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// copy initialized variables data
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while ( dst < &_edata ) { *dst++ = *src++; }
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// clear uninitialized variables
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for ( dst = &_sbss; dst < &_ebss; dst++ ) { *dst = 0; }
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// call main
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main();
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// halt
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for(;;) {}
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}
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void blocking_handler(void)
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{
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while (1);
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}
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void null_handler(void)
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{
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/* Do nothing. */
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}
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#pragma weak nmi_handler = null_handler
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#pragma weak hard_fault_handler = blocking_handler
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#pragma weak sv_call_handler = null_handler
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#pragma weak pend_sv_handler = null_handler
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#pragma weak sys_tick_handler = null_handler
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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#pragma weak mem_manage_handler = blocking_handler
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#pragma weak bus_fault_handler = blocking_handler
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#pragma weak usage_fault_handler = blocking_handler
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#pragma weak debug_monitor_handler = null_handler
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#endif
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#if defined STM32G0
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#pragma weak wwdg_isr = blocking_handler
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#pragma weak rtc_isr = blocking_handler
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#pragma weak flash_isr = blocking_handler
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#pragma weak rcc_isr = blocking_handler
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#pragma weak exti0_1_isr = blocking_handler
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#pragma weak exti2_3_isr = blocking_handler
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#pragma weak exti4_15_isr = blocking_handler
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#pragma weak dma1_channel1_isr = blocking_handler
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#pragma weak dma1_channel2_3_isr = blocking_handler
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#pragma weak dmamux_isr = blocking_handler
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#pragma weak adc_comp_isr = blocking_handler
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#pragma weak tim1_brk_up_trg_com_isr = blocking_handler
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#pragma weak tim1_cc_isr = blocking_handler
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#pragma weak tim3_4_isr = blocking_handler
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#pragma weak tim6_dac_isr = blocking_handler
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#pragma weak tim7_isr = blocking_handler
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#pragma weak tim14_isr = blocking_handler
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#pragma weak tim15_isr = blocking_handler
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#pragma weak tim16_isr = blocking_handler
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#pragma weak tim17_isr = blocking_handler
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#pragma weak i2c1_isr = blocking_handler
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#pragma weak i2c2_3_isr = blocking_handler
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#pragma weak spi1_isr = blocking_handler
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#pragma weak spi2_3_isr = blocking_handler
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#pragma weak usart1_isr = blocking_handler
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#pragma weak usart2_isr = blocking_handler
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#pragma weak usart3_6_isr = blocking_handler
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#pragma weak cec_can_isr = blocking_handler
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#pragma weak usb_isr = blocking_handler
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#endif
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