mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 02:35:23 +03:00
311 lines
9.4 KiB
C
311 lines
9.4 KiB
C
/*
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* This file is part of the nitrogen project.
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* Copyright 2023 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stm32f3.h>
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#include <string.h>
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#include "i2c.h"
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#include "strfunc.h" // hexdump
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#include "usb.h"
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I2C_SPEED curI2Cspeed = LOW_SPEED;
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extern volatile uint32_t Tms;
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static uint32_t cntr;
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static uint8_t i2c_got_DMA_Rx = 0;
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volatile uint8_t I2C_scan_mode = 0; // == 1 when I2C is in scan mode
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static uint8_t i2caddr = I2C_ADDREND; // current address in scan mode
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static volatile int I2Cbusy = 0, goterr = 0; // busy==1 when DMA active, goterr==1 if 't was error @ last sent
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static uint8_t I2Cbuf[256], i2cbuflen = 0; // buffer for DMA tx/rx and its len
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// macros for I2C rx/tx
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#define DMARXCCR (DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE)
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#define DMATXCCR (DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE | DMA_CCR_TEIE)
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// macro for I2CCR1
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#define I2CCR1 (I2C_CR1_PE | I2C_CR1_RXDMAEN | I2C_CR1_TXDMAEN)
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// return 1 if I2Cbusy is set & timeout reached
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static inline int isI2Cbusy(){
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cntr = Tms;
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do{
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if(Tms - cntr > I2C_TIMEOUT){ USND("Timeout, DMA transfer in progress?"); return 1;}
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}while(I2Cbusy);
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return 0;
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}
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// GPIO Resources: I2C1_SCL - PB6 (AF4), I2C1_SDA - PB7 (AF4)
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void i2c_setup(I2C_SPEED speed){
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if(speed >= CURRENT_SPEED){
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speed = curI2Cspeed;
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}else{
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curI2Cspeed = speed;
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}
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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I2C1->CR1 = 0;
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I2C1->ICR = 0x3f38; // clear all errors
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GPIOB->AFR[0] = (GPIOB->AFR[0] & ~(GPIO_AFRL_AFRL6 | GPIO_AFRL_AFRL7)) |
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AFRf(4, 6) | AFRf(4, 7);
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GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER6 | GPIO_MODER_MODER7)) |
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GPIO_MODER_MODER6_AF | GPIO_MODER_MODER7_AF;
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GPIOB->PUPDR = (GPIOB->PUPDR & !(GPIO_PUPDR_PUPDR6 | GPIO_PUPDR_PUPDR7)) |
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GPIO_PUPDR6_PU | GPIO_PUPDR7_PU; // pullup (what if there's no external pullup?)
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GPIOB->OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7; // both open-drain outputs
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// I2C (default timing from PCLK - 64MHz)
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // clocking
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if(speed == LOW_SPEED){ // 10kHz
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// PRESC=F, SCLDEL=4, SDADEL=2, SCLH=0xC3, SCLL=0xC7
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I2C1->TIMINGR = (0xF<<28) | (4<<20) | (2<<16) | (0xC3<<8) | (0xC7);
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}else if(speed == HIGH_SPEED){ // 100kHz
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I2C1->TIMINGR = (0xF<<28) | (4<<20) | (2<<16) | (0xF<<8) | (0x13);
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}else{ // VERYLOW_SPEED - the lowest speed by STM register: ~7.7kHz
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I2C1->TIMINGR = (0xF<<28) | (4<<20) | (2<<16) | (0xff<<8) | (0xff);
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}
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I2C1->CR1 = I2CCR1;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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NVIC_EnableIRQ(DMA1_Channel6_IRQn);
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NVIC_EnableIRQ(DMA1_Channel7_IRQn);
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I2Cbusy = 0;
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}
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// setup DMA for rx (tx==0) or tx (tx==1)
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// DMA channels: 7 - I2C1_Rx, 6 - I2C1_Tx
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static void i2cDMAsetup(int tx, uint8_t len){
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if(tx){
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DMA1_Channel6->CCR = DMATXCCR;
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DMA1_Channel6->CPAR = (uint32_t) &I2C1->TXDR;
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DMA1_Channel6->CMAR = (uint32_t) I2Cbuf;
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DMA1_Channel6->CNDTR = i2cbuflen = len;
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}else{
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DMA1_Channel7->CCR = DMARXCCR;
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DMA1_Channel7->CPAR = (uint32_t) &I2C1->RXDR;
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DMA1_Channel7->CMAR = (uint32_t) I2Cbuf;
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DMA1_Channel7->CNDTR = i2cbuflen = len;
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}
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}
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static uint8_t i2c_start(uint8_t busychk){
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if(busychk){
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cntr = Tms;
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while(I2C1->ISR & I2C_ISR_BUSY){
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IWDG->KR = IWDG_REFRESH;
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if(Tms - cntr > I2C_TIMEOUT){
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USND("Line busy");
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return 0; // check busy
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}}
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}
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cntr = Tms;
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while(I2C1->CR2 & I2C_CR2_START){
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IWDG->KR = IWDG_REFRESH;
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if(Tms - cntr > I2C_TIMEOUT){
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USND("No start");
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return 0; // check start
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}}
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return 1;
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}
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// start writing
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static uint8_t i2c_startw(uint8_t addr, uint8_t nbytes, uint8_t stop){
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if(!i2c_start(1)) return 0;
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I2C1->CR2 = nbytes << 16 | addr;
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if(stop) I2C1->CR2 |= I2C_CR2_AUTOEND; // autoend
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// now start transfer
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I2C1->CR2 |= I2C_CR2_START;
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return 1;
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}
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/**
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* write command byte to I2C
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* @param addr - device address (TSYS01_ADDR0 or TSYS01_ADDR1)
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* @param data - bytes to write
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* @param nbytes - amount of bytes to write
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* @param stop - to set STOP
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* @return 0 if error
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*/
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static uint8_t write_i2cs(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t stop){
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if(!i2c_startw(addr, nbytes, stop)) return 0;
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for(int i = 0; i < nbytes; ++i){
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cntr = Tms;
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while(!(I2C1->ISR & I2C_ISR_TXIS)){ // ready to transmit
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IWDG->KR = IWDG_REFRESH;
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if(I2C1->ISR & I2C_ISR_NACKF){
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I2C1->ICR |= I2C_ICR_NACKCF;
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DBG("NAK");
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return 0;
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}
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if(Tms - cntr > I2C_TIMEOUT){
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DBG("Timeout");
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return 0;
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}
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}
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I2C1->TXDR = data[i]; // send data
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}
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return 1;
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}
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uint8_t write_i2c(uint8_t addr, uint8_t *data, uint8_t nbytes){
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if(isI2Cbusy()){
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DBG("I2C busy");
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return 0;
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}
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return write_i2cs(addr, data, nbytes, 1);
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}
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uint8_t write_i2c_dma(uint8_t addr, uint8_t *data, uint8_t nbytes){
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if(!data || nbytes < 1) return 0;
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if(isI2Cbusy()) return 0;
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memcpy((char*)I2Cbuf, (char*)data, nbytes);
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i2cDMAsetup(1, nbytes);
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goterr = 0;
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if(!i2c_startw(addr, nbytes, 1)) return 0;
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I2Cbusy = 1;
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DMA1_Channel6->CCR = DMATXCCR | DMA_CCR_EN; // start transfer
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return 1;
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}
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// start reading
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static uint8_t i2c_startr(uint8_t addr, uint8_t nbytes, uint8_t busychk){
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if(!i2c_start(busychk)) return 0;
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// read N bytes
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I2C1->CR2 = (nbytes<<16) | addr | 1 | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN;
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I2C1->CR2 |= I2C_CR2_START;
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return 1;
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}
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/**
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* read nbytes of data from I2C line
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* all functions with `addr` should have addr = address << 1
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* `data` should be an array with at least `nbytes` length
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* @return 1 if all OK, 0 if NACK or no device found
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*/
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static uint8_t read_i2cb(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t busychk){
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if(!i2c_startr(addr, nbytes, busychk)) return 0;
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uint8_t i;
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for(i = 0; i < nbytes; ++i){
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cntr = Tms;
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while(!(I2C1->ISR & I2C_ISR_RXNE)){ // wait for data
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IWDG->KR = IWDG_REFRESH;
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if(I2C1->ISR & I2C_ISR_NACKF){
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I2C1->ICR |= I2C_ICR_NACKCF;
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//DBG("NAK");
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return 0;
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}
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if(Tms - cntr > I2C_TIMEOUT){
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//DBG("Timeout");
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return 0;
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}
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}
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*data++ = I2C1->RXDR;
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}
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return 1;
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}
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uint8_t read_i2c(uint8_t addr, uint8_t *data, uint8_t nbytes){
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if(isI2Cbusy()) return 0;
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return read_i2cb(addr, data, nbytes, 1);
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}
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uint8_t read_i2c_dma(uint8_t addr, uint8_t nbytes){
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if(nbytes < 1) return 0;
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if(isI2Cbusy()) return 0;
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i2cDMAsetup(0, nbytes);
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goterr = 0;
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if(!i2c_startr(addr, nbytes, 1)) return 0;
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I2Cbusy = 1;
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DMA1_Channel7->CCR = DMARXCCR | DMA_CCR_EN; // start transfer
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return 1;
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}
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// read register reg
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uint8_t read_i2c_reg(uint8_t addr, uint8_t reg, uint8_t *data, uint8_t nbytes){
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if(isI2Cbusy()) return 0;
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if(!write_i2cs(addr, ®, 1, 0)) return 0;
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return read_i2cb(addr, data, nbytes, 0);
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}
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// read 16bit register reg
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uint8_t read_i2c_reg16(uint8_t addr, uint16_t reg16, uint8_t *data, uint8_t nbytes){
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if(isI2Cbusy()) return 0;
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if(!write_i2cs(addr, (uint8_t*)®16, 2, 0)) return 0;
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return read_i2cb(addr, data, nbytes, 0);
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}
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void i2c_init_scan_mode(){
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i2caddr = 1; // start from 1 as 0 is a broadcast address
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I2C_scan_mode = 1;
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DBG("init scan");
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}
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// return 1 if next addr is active & return in as `addr`
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// if addresses are over, return 1 and set addr to I2C_NOADDR
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// if scan mode inactive, return 0 and set addr to I2C_NOADDR
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int i2c_scan_next_addr(uint8_t *addr){
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if(isI2Cbusy()){
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DBG("scan: busy");
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return 0;
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}
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*addr = i2caddr;
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if(i2caddr == I2C_ADDREND){
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I2C_scan_mode = 0;
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return 0;
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}
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uint8_t byte;
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if(!read_i2c((i2caddr++)<<1, &byte, 1)) return 0;
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return 1;
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}
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// dump I2Cbuf
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void i2c_bufdudump(){
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if(goterr){
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USND("Last transfer ends with error!");
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goterr = 0;
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}
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USND("I2C buffer:");
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hexdump(USB_sendstr, I2Cbuf, i2cbuflen);
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}
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void i2c_have_DMA_Rx(){
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if(!i2c_got_DMA_Rx) return;
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i2c_got_DMA_Rx = 0;
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i2c_bufdudump();
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}
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int i2cdma_haderr(){
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int r = goterr;
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goterr = 0;
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return r;
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}
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// Rx (7) /Tx (6) interrupts
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static void I2C_isr(int rx){
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uint32_t isr = DMA1->ISR;
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DMA_Channel_TypeDef *ch = (rx) ? DMA1_Channel7 : DMA1_Channel6;
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if(isr & (DMA_ISR_TEIF6 | DMA_ISR_TEIF6)) goterr = 1;
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if(rx) i2c_got_DMA_Rx = 1; // last transfer was Rx
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ch->CCR = 0;
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I2Cbusy = 0;
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DMA1->IFCR = 0x0ff00000; // clear all flags for channel6/7
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}
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void dma1_channel6_isr(){
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I2C_isr(0);
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}
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void dma1_channel7_isr(){
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I2C_isr(1);
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}
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