mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 18:55:13 +03:00
271 lines
9.2 KiB
C
271 lines
9.2 KiB
C
/*
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* This file is part of the MLX90640 project.
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* Copyright 2022 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "i2c.h"
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/* don't run debugging info */
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#ifdef EBUG
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#undef EBUG
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#endif
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#include "strfunct.h"
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extern volatile uint32_t Tms;
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volatile i2c_dma_status i2cDMAr = I2C_DMA_NOTINIT;
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// current addresses for read/write (should be set with i2c_set_addr7)
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static uint8_t addr7r = 0, addr7w = 0;
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// setup DMA receiver
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static void i2c_DMAr_setup(){
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/* Enable the peripheral clock DMA1 */
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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DMA1_Channel7->CPAR = (uint32_t)&(I2C1->DR);
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DMA1_Channel7->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE;
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NVIC_SetPriority(DMA1_Channel7_IRQn, 0);
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NVIC_EnableIRQ(DMA1_Channel7_IRQn);
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I2C1->CR2 |= I2C_CR2_DMAEN;
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i2cDMAr = I2C_DMA_RELAX;
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}
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/*
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* PB10/PB6 - I2C_SCL, PB11/PB7 - I2C_SDA or remap @ PB8 & PB9
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* @param withDMA == 1 to setup DMA receiver too
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*/
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void i2c_setup(uint8_t withDMA){
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RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
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GPIOB->CRL = (GPIOB->CRL & ~(GPIO_CRL_CNF6 | GPIO_CRL_CNF7)) |
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CRL(6, CNF_AFOD | MODE_NORMAL) | CRL(7, CNF_AFOD | MODE_NORMAL);
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
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I2C1->CR1 = 0; // clear all previous settings
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I2C1->SR1 = 0;
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RCC->APB1RSTR |= RCC_APB1RSTR_I2C1RST; // reset peripherial
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RCC->APB1RSTR &= ~RCC_APB1RSTR_I2C1RST;
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I2C1->CR2 = 8; // FREQR=8MHz, T=125ns
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//I2C1->CR2 = 10; // FREQR=10MHz, T=100ns
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I2C1->TRISE = 9; // (9-1)*125 = 1us
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//I2C1->TRISE = 4; // (4-1)*100 = 300ns
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I2C1->CCR = 40; // normal mode, 8MHz/2/40 = 100kHz
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//I2C1->CCR = I2C_CCR_FS | 10; // fast mode, 10MHz/2/10 = 500kHz
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if(withDMA) i2c_DMAr_setup();
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I2C1->CR1 |= I2C_CR1_PE; // enable periph
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}
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void i2c_set_addr7(uint8_t addr){
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addr7w = addr << 1;
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addr7r = addr7w | 1;
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}
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// wait for event evt no more than 2 ms
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#define I2C_WAIT(evt) do{ register uint32_t wait4 = Tms + 2; \
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while(Tms < wait4 && !(evt)) IWDG->KR = IWDG_REFRESH; \
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if(!(evt)){ret = I2C_TMOUT; goto eotr;}}while(0)
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// wait for !busy
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#define I2C_LINEWAIT() do{ register uint32_t wait4 = Tms + 2; \
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while(Tms < wait4 && (I2C1->SR2 & I2C_SR2_BUSY)) IWDG->KR = IWDG_REFRESH; \
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if(I2C1->SR2 & I2C_SR2_BUSY){I2C1->CR1 |= I2C_CR1_SWRST; return I2C_LINEBUSY;}\
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}while(0)
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// start writing
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static i2c_status i2c_7bit_startw(){
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i2c_status ret = I2C_LINEBUSY;
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if(I2C1->CR1 != I2C_CR1_PE) i2c_setup(i2cDMAr != I2C_DMA_NOTINIT);
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if(I2C1->SR1) I2C1->SR1 = 0; // clear NACK and other problems
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(void) I2C1->SR2;
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I2C_LINEWAIT();
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DBG("linew");
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I2C1->CR1 |= I2C_CR1_START; // generate start sequence
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("SB");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7w; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag (timeout @ NACK)
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DBG("ADDR");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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return I2C_NACK;
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}
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DBG("ACK");
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(void) I2C1->SR2; // clear ADDR
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ret = I2C_OK;
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eotr:
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return ret;
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}
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// send data array
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i2c_status i2c_7bit_send(const uint8_t *data, int datalen, uint8_t stop){
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i2c_status ret = i2c_7bit_startw();
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if(ret != I2C_OK){
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DBG("NACK!");
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I2C1->CR1 |= I2C_CR1_STOP;
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goto eotr;
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}
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for(int i = 0; i < datalen; ++i){
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I2C1->DR = data[i];
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I2C_WAIT(I2C1->SR1 & I2C_SR1_TXE);
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}
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DBG("GOOD");
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ret = I2C_OK;
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if(datalen || stop) I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF);
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eotr:
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if(stop){
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I2C1->CR1 |= I2C_CR1_STOP; // generate stop event
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}else{DBG("No STOP");}
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return ret;
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}
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i2c_status i2c_7bit_receive_onebyte(uint8_t *data, uint8_t stop){
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i2c_status ret = I2C_LINEBUSY;
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I2C1->CR1 |= I2C_CR1_START; // generate start sequence
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("got SB");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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DBG("Rx addr");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("Rx ack");
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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DBG("Rx nak");
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ret = I2C_NACK;
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goto eotr;
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}
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(void) I2C1->SR2; // clear ADDR
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DBG("Rx stop");
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if(stop) I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait for RxNE
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DBG("Rx OK");
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*data = I2C1->DR; // read data & clear RxNE
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ret = I2C_OK;
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eotr:
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return ret;
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}
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i2c_status i2c_7bit_receive_twobytes(uint8_t *data){
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i2c_status ret = I2C_LINEBUSY;
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I2C1->CR1 |= I2C_CR1_START | I2C_CR1_POS | I2C_CR1_ACK; // generate start sequence, set pos & ack
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("2 got sb");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("2 ADDR");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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ret = I2C_NACK;
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DBG("2 NACK");
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goto eotr;
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}
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DBG("2 ACK");
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(void) I2C1->SR2; // clear ADDR
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF); // wait for BTF
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DBG("2 BTF");
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I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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*data++ = I2C1->DR; *data = I2C1->DR; // read data & clear RxNE
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ret = I2C_OK;
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eotr:
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return ret;
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}
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// receive any amount of bytes
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i2c_status i2c_7bit_receive(uint8_t *data, uint16_t nbytes){
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if(nbytes == 0) return I2C_HWPROBLEM;
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//DBG("linew");
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//I2C_LINEWAIT();
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I2C1->SR1 = 0; // clear previous NACK flag & other error flags
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if(nbytes == 1) return i2c_7bit_receive_onebyte(data, 1);
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else if(nbytes == 2) return i2c_7bit_receive_twobytes(data);
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i2c_status ret = I2C_LINEBUSY;
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I2C1->CR1 |= I2C_CR1_START | I2C_CR1_ACK; // generate start sequence, set pos & ack
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB); // wait for SB
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DBG("n got SB");
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(void) I2C1->SR1; // clear SB
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I2C1->DR = addr7r; // set address
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR); // wait for ADDR flag
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DBG("n send addr");
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if(I2C1->SR1 & I2C_SR1_AF){ // NACK
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DBG("n NACKed");
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ret = I2C_NACK;
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goto eotr;
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}
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DBG("n ACKed");
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(void) I2C1->SR2; // clear ADDR
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for(uint16_t x = nbytes - 3; x > 0; --x){
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait next byte
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*data++ = I2C1->DR; // get data
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}
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DBG("n three left");
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// three bytes remain to be read
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait dataN-2
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DBG("n dataN-2");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_BTF); // wait for BTF
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DBG("n BTF");
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I2C1->CR1 &= ~I2C_CR1_ACK; // clear ACK
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*data++ = I2C1->DR; // read dataN-2
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I2C1->CR1 |= I2C_CR1_STOP; // program STOP
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*data++ = I2C1->DR; // read dataN-1
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I2C_WAIT(I2C1->SR1 & I2C_SR1_RXNE); // wait next byte
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*data = I2C1->DR; // read dataN
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DBG("n got it");
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ret = I2C_OK;
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eotr:
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return ret;
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}
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/**
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* @brief i2c_7bit_receive_DMA - receive data using DMA
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* @param data - pointer to external array
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* @param nbytes - data len
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* @return I2C_OK when receiving started; poll end of receiving by flag i2cDMAr;
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*/
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i2c_status i2c_7bit_receive_DMA(uint8_t *data, uint16_t nbytes){
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if(i2cDMAr == I2C_DMA_BUSY) return I2C_LINEBUSY; // previous receiving still works
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if(i2cDMAr == I2C_DMA_NOTINIT) i2c_DMAr_setup();
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i2c_status ret = I2C_LINEBUSY;
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DBG("Conf DMA");
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DMA1_Channel7->CCR &= ~DMA_CCR_EN;
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DMA1_Channel7->CMAR = (uint32_t)data;
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DMA1_Channel7->CNDTR = nbytes;
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// now send address and start I2C receiving
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//DBG("linew");
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//I2C_LINEWAIT();
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I2C1->SR1 = 0;
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I2C1->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
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DBG("wait sb");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_SB);
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(void) I2C1->SR1;
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I2C1->DR = addr7r;
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DBG("wait addr");
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I2C_WAIT(I2C1->SR1 & I2C_SR1_ADDR);
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if(I2C1->SR1 & I2C_SR1_AF) return I2C_NACK;
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(void) I2C1->SR2;
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DBG("start");
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DMA1_Channel7->CCR |= DMA_CCR_EN;
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i2cDMAr = I2C_DMA_BUSY;
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ret = I2C_OK;
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eotr:
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return ret;
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}
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void dma1_channel7_isr(){
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I2C1->CR1 |= I2C_CR1_STOP; // send STOP
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DMA1->IFCR = DMA_IFCR_CTCIF7;
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DMA1_Channel7->CCR &= ~DMA_CCR_EN;
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i2cDMAr = I2C_DMA_READY;
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}
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