mirror of
https://github.com/eddyem/stm32samples.git
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109 lines
3.6 KiB
C
109 lines
3.6 KiB
C
/*
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* This file is part of the multiiface project.
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* Copyright 2026 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "Debug.h"
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#include "hardware.h"
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#include "spi.h"
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typedef enum{
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SPI_NOTREADY,
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SPI_IDLE,
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SPI_READY,
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#ifdef SPIDMA
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SPI_BUSY
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#endif
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} spiStatus;
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static spiStatus spi_status = SPI_NOTREADY;
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static uint32_t spidata = 0;
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#define WAITX(x) do{volatile uint32_t wctr = 0; while((x) && (++wctr < 360000)) IWDG->KR = IWDG_REFRESH; if(wctr==360000){ DBG("timeout"); return 0;}}while(0)
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// init SPI to work with and without DMA
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// DMA1Channel2 - SPI1 Rx
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void spi_setup(){
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SPI1->CR1 = 0; // clear EN
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SPI1->CR2 = 0;
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// SPI for SSI: PA5/PA6, without MOSI; suppose that clocking and GPIO OK (hardware.c)
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RCC->APB2RSTR = RCC_APB2RSTR_SPI1RST; // reset SPI before start
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RCC->APB2RSTR = 0; // clear reset
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SPI1->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_RXONLY; // software slave management (without hardware NSS pin); RX only
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#ifdef SPIDMA
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// setup SPI DMA
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SPI11->CR2 = SPI_CR2_RXDMAEN;
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// Rx
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DMA1_Channel2->CPAR = (uint32_t)&(SPI1->DR);
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DMA1_Channel2->CCR = DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE; // mem inc, hw->mem, Rx complete and error interrupt
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NVIC_EnableIRQ(DMA1_Channel2_IRQn); // enable Rx interrupt
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#endif
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// Master, baudrate = 0b110 - fpclk/128 (562.5 kHz)
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SPI1->CR1 |= SPI_CR1_MSTR | SPI_CR1_BR_2 | SPI_CR1_BR_1;
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// DS=8bit; RXNE generates after 8bit of data in FIFO;
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SPI1->CR2 |= SPI_CR2_FRXTH | SPI_CR2_DS_2|SPI_CR2_DS_1|SPI_CR2_DS_0;
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spi_status = SPI_IDLE;
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DBG("SPI setup OK");
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}
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// return TRUE if data ready and change `encval`
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int spi_read_enc(uint32_t *encval){
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if(spi_status != SPI_READY) return FALSE;
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spi_status = SPI_IDLE;
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#ifndef SPIDMA
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// clear SPI Rx FIFO
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for(int i = 0; i < 4; ++i) (void) SPI1->DR;
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SPI1->CR1 |= SPI_CR1_SPE;
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uint8_t *data = (uint8_t*) &spidata;
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for(uint32_t x = 0; x < ENCODERBYTES; ++x){
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if(x == ENCODERBYTES - 1) SPI1->CR1 &= ~SPI_CR1_RXONLY; // clear RXonly bit to stop CLK generation after next byte
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WAITX(!(SPI1->SR & SPI_SR_RXNE));
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data[x] = *((volatile uint8_t*)&SPI1->DR);
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}
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SPI1->CR1 &= ~SPI_CR1_SPE;
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SPI1->CR1 |= SPI_CR1_RXONLY; // and return RXonly bit
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#endif
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if(encval) *encval = spidata;
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return TRUE;
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}
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#ifdef SPIDMA
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// start encoder reading over DMA
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// @return FALSE if SPI is busy
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int spi_start_enc(){
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if(spi_status == SPI_BUSY || spi_status == SPI_NOTREADY) return FALSE;
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if(SPI1->SR & SPI_SR_BSY) return FALSE;
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DMA1_Channel2->CMAR = (uint32_t) &spidata;
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DMA1_Channel2->CNDTR = 4;
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DMA1_Channel2->CCR |= DMA_CCR_EN;
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SPI1->CR1 |= SPI_CR1_SPE;
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spi_status = SPI_BUSY;
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return TRUE;
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}
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// SSI got fresh data
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void dma1_channel2_isr(){
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SPI1->CR1 &= ~SPI_CR1_SPE;
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spi_status = SPI_READY; // ready independent on errors or Rx ready
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}
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#else
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int spi_start_enc(){ // simple stub
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if(spi_status == SPI_NOTREADY) return FALSE;
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spi_status = SPI_READY; // user asks to read data
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return TRUE;
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}
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#endif
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